[PATCH]: 0d5f4c06bc tcl/target: add Bouffalo Lab BL602 chip series support Adds support for the BL602 series of chips, BL602 and BL602.

[<ge...@op...>]

This is an automated email from Gerrit.

"Marek Kraus <gam...@ou...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8537

-- gerrit

commit 0d5f4c06bcc67793a877d84d8e6f0d841b82b787
Author: Marek Kraus <gam...@ou...>
Date:   Sun Nov 3 14:53:36 2024 +0100

    tcl/target: add Bouffalo Lab BL602 chip series support
    Adds support for the BL602 series of chips, BL602 and BL602.
    
    BL602 is bit older than BL702, which is already upstreamed,
    but both were developed at same time, thus having many things
    in common, such as flash driver and software reset method.
    
    Change-Id: Ieffb7501fa9a34ab597d8fd6a828a0125f6b85d7
    Signed-off-by: Marek Kraus <gam...@ou...>

diff --git a/tcl/target/bl602.cfg b/tcl/target/bl602.cfg
new file mode 100644
index 0000000000..291c88759a
--- /dev/null
+++ b/tcl/target/bl602.cfg
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Bouffalo Labs BL602 target
+#
+# https://en.bouffalolab.com/product/?type=detail&id=1
+#
+# Default JTAG pins: (if not changed by eFuse configuration)
+# TDO - GPIO11
+# TMS - GPIO12
+# TCK - GPIO14
+# TDI - GPIO17
+#
+
+source [find mem_helper.tcl]
+
+transport select jtag
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME bl602
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000c05
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+
+riscv set_mem_access sysbus
+
+# For work-area we use DTCM instead of ITCM, due ITCM is used as buffer for L1 cache and XIP
+$_TARGETNAME configure -work-area-phys 0x42014000 -work-area-size 0xC000 -work-area-backup 1
+
+# Internal RC ticks on 32 MHz, so this speed should be safe to use.
+adapter speed 8000
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME bl602_flash 0x23000000 0 0 0 $_TARGETNAME
+
+$_TARGETNAME configure -event reset-init {
+	# Probing of Flash is required to initialize SFlash from unknown state.
+	flash probe 0
+}
+
+# Debug Module's ndmreset resets only Trust Zone Controller, so we need to do SW reset instead.
+# CTRL_PWRON_RESET triggers full "power-on like" reset.
+# This means that pinmux configuration to access JTAG is reset as well, and configured back early
+# in BootROM.
+$_TARGETNAME configure -event reset-assert-pre {
+	halt
+
+	# Switch clock to internal RC32M
+ 	# In HBN_GLB, set ROOT_CLK_SEL = 0
+ 	mmw 0x4000f030 0x0 0x00000003
+ 	# Wait for clock switch
+ 	sleep 10
+
+ 	# GLB_REG_BCLK_DIS_FALSE
+ 	mww 0x40000ffc 0x0
+
+ 	# HCLK is RC32M, so BCLK/HCLK doesn't need divider
+ 	# In GLB_CLK_CFG0, set BCLK_DIV = 0 and HCLK_DIV = 0
+ 	mmw 0x40000000 0x0 0x00FFFF00
+ 	# Wait for clock to stabilize
+ 	sleep 10
+
+	# Do reset
+	# In GLB_SWRST_CFG2, clear CTRL_SYS_RESET, CTRL_CPU_RESET
+	mmw 0x40000018 0x0 0x00000007
+
+	# Since this full software reset resets GPIO pinmux as well, we will lose access
+	# to JTAG right away after writing to register. This chip doesn't support abstract
+	# memory access, so when this is done by progbuf or sysbus, OpenOCD will fail to read
+	# if write was successful or not, and will print error about that. Since receiving of
+	# this error is expected, we will turn off log printing for a moment,
+	set lvl [lindex [debug_level] 1]
+	debug_level -1
+	# In GLB_SWRST_CFG2, set CTRL_SYS_RESET, CTRL_CPU_RESET and CTRL_PWRON_RESET to 1
+	catch {mmw 0x40000018 0x7 0x0}
+	debug_level $lvl
+}

--