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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-627-g198fecf5e
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From: openocd-gerrit <ope...@us...> - 2024-06-23 09:30:02
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The branch, master has been updated
via 198fecf5e4b03c2024c9d75fd5e6045daf681ed5 (commit)
via b5dfef7577f87c34bd397981c17e5d461d1c217f (commit)
from f39f136e012589212b463af4ef1ac7d855901810 (commit)
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- Log -----------------------------------------------------------------
commit 198fecf5e4b03c2024c9d75fd5e6045daf681ed5
Author: Antonio Borneo <bor...@gm...>
Date: Tue May 14 14:40:07 2024 +0200
target: aarch64: access reg SPSR_EL1 only in EL1, EL2 and EL3
The register SPSR_EL1 is accessible and it's content is relevant
only when the target is in EL1 or EL2 or EL3.
Plus, the register is 64 bits wide.
Without this patch, an error:
Error: Opcode 0xd5384000, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $SPSR_EL1
or through OpenOCD command
reg SPSR_EL1
Detect the EL and return error if the register cannot be accessed.
Handle the register as 64 bits.
Change-Id: Ia0f984d52920cc32b8ee31157d62c13dea616a3a
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8276
Tested-by: jenkins
diff --git a/src/target/armv8.c b/src/target/armv8.c
index 14b172689..b54ef13d3 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -369,9 +369,13 @@ static int armv8_read_reg(struct armv8_common *armv8, int regnum, uint64_t *regv
ARMV8_MRS(SYSTEM_ESR_EL3, 0), &value_64);
break;
case ARMV8_SPSR_EL1:
- retval = dpm->instr_read_data_r0(dpm,
- ARMV8_MRS(SYSTEM_SPSR_EL1, 0), &value);
- value_64 = value;
+ if (curel < SYSTEM_CUREL_EL1) {
+ LOG_DEBUG("SPSR_EL1 not accessible in EL%u", curel);
+ retval = ERROR_FAIL;
+ break;
+ }
+ retval = dpm->instr_read_data_r0_64(dpm,
+ ARMV8_MRS(SYSTEM_SPSR_EL1, 0), &value_64);
break;
case ARMV8_SPSR_EL2:
if (curel < SYSTEM_CUREL_EL2) {
@@ -526,9 +530,13 @@ static int armv8_write_reg(struct armv8_common *armv8, int regnum, uint64_t valu
ARMV8_MSR_GP(SYSTEM_ESR_EL3, 0), value_64);
break;
case ARMV8_SPSR_EL1:
- value = value_64;
- retval = dpm->instr_write_data_r0(dpm,
- ARMV8_MSR_GP(SYSTEM_SPSR_EL1, 0), value);
+ if (curel < SYSTEM_CUREL_EL1) {
+ LOG_DEBUG("SPSR_EL1 not accessible in EL%u", curel);
+ retval = ERROR_FAIL;
+ break;
+ }
+ retval = dpm->instr_write_data_r0_64(dpm,
+ ARMV8_MSR_GP(SYSTEM_SPSR_EL1, 0), value_64);
break;
case ARMV8_SPSR_EL2:
if (curel < SYSTEM_CUREL_EL2) {
@@ -1582,7 +1590,7 @@ static const struct {
NULL},
{ ARMV8_ESR_EL1, "ESR_EL1", 64, ARMV8_64_EL1H, REG_TYPE_UINT64, "banked", "net.sourceforge.openocd.banked",
NULL},
- { ARMV8_SPSR_EL1, "SPSR_EL1", 32, ARMV8_64_EL1H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked",
+ { ARMV8_SPSR_EL1, "SPSR_EL1", 64, ARMV8_64_EL1H, REG_TYPE_UINT64, "banked", "net.sourceforge.openocd.banked",
NULL},
{ ARMV8_ELR_EL2, "ELR_EL2", 64, ARMV8_64_EL2H, REG_TYPE_CODE_PTR, "banked", "net.sourceforge.openocd.banked",
commit b5dfef7577f87c34bd397981c17e5d461d1c217f
Author: Antonio Borneo <bor...@gm...>
Date: Tue May 14 14:23:07 2024 +0200
target: aarch64: access reg ESR_EL1 only in EL1, EL2 and EL3
The register ESR_EL1 is accessible and it's content is relevant
only when the target is in EL1 or EL2 or EL3.
Plus, the register is 64 bits wide.
Without this patch, an error:
Error: Opcode 0xd5385200, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $ESR_EL1
or through OpenOCD command
reg ESR_EL1
Detect the EL and return error if the register cannot be accessed.
Handle the register as 64 bits.
Change-Id: Icd65470c279e5cfd03091db6435cdaa1c447644c
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8275
Tested-by: jenkins
diff --git a/src/target/armv8.c b/src/target/armv8.c
index 176747013..14b172689 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -342,9 +342,13 @@ static int armv8_read_reg(struct armv8_common *armv8, int regnum, uint64_t *regv
ARMV8_MRS(SYSTEM_ELR_EL3, 0), &value_64);
break;
case ARMV8_ESR_EL1:
- retval = dpm->instr_read_data_r0(dpm,
- ARMV8_MRS(SYSTEM_ESR_EL1, 0), &value);
- value_64 = value;
+ if (curel < SYSTEM_CUREL_EL1) {
+ LOG_DEBUG("ESR_EL1 not accessible in EL%u", curel);
+ retval = ERROR_FAIL;
+ break;
+ }
+ retval = dpm->instr_read_data_r0_64(dpm,
+ ARMV8_MRS(SYSTEM_ESR_EL1, 0), &value_64);
break;
case ARMV8_ESR_EL2:
if (curel < SYSTEM_CUREL_EL2) {
@@ -495,9 +499,13 @@ static int armv8_write_reg(struct armv8_common *armv8, int regnum, uint64_t valu
ARMV8_MSR_GP(SYSTEM_ELR_EL3, 0), value_64);
break;
case ARMV8_ESR_EL1:
- value = value_64;
- retval = dpm->instr_write_data_r0(dpm,
- ARMV8_MSR_GP(SYSTEM_ESR_EL1, 0), value);
+ if (curel < SYSTEM_CUREL_EL1) {
+ LOG_DEBUG("ESR_EL1 not accessible in EL%u", curel);
+ retval = ERROR_FAIL;
+ break;
+ }
+ retval = dpm->instr_write_data_r0_64(dpm,
+ ARMV8_MSR_GP(SYSTEM_ESR_EL1, 0), value_64);
break;
case ARMV8_ESR_EL2:
if (curel < SYSTEM_CUREL_EL2) {
@@ -1572,7 +1580,7 @@ static const struct {
{ ARMV8_ELR_EL1, "ELR_EL1", 64, ARMV8_64_EL1H, REG_TYPE_CODE_PTR, "banked", "net.sourceforge.openocd.banked",
NULL},
- { ARMV8_ESR_EL1, "ESR_EL1", 32, ARMV8_64_EL1H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked",
+ { ARMV8_ESR_EL1, "ESR_EL1", 64, ARMV8_64_EL1H, REG_TYPE_UINT64, "banked", "net.sourceforge.openocd.banked",
NULL},
{ ARMV8_SPSR_EL1, "SPSR_EL1", 32, ARMV8_64_EL1H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked",
NULL},
-----------------------------------------------------------------------
Summary of changes:
src/target/armv8.c | 44 ++++++++++++++++++++++++++++++--------------
1 file changed, 30 insertions(+), 14 deletions(-)
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