Menu
▾
▴
[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-625-gf39f136e0
|
From: openocd-gerrit <ope...@us...> - 2024-06-23 09:29:41
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via f39f136e012589212b463af4ef1ac7d855901810 (commit)
via 2a63fabd095044f0a05cf69a34300409809f676b (commit)
via 766a84b79892c1321f3f86d3f1b301519269b4f5 (commit)
from 190176a6bc947fd2516b959217084e531374b9bf (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit f39f136e012589212b463af4ef1ac7d855901810
Author: Antonio Borneo <bor...@gm...>
Date: Tue May 14 14:17:39 2024 +0200
target: aarch64: access reg ELR_EL1 only in EL1, EL2 and EL3
The register ELR_EL1 is accessible and it's content is relevant
only when the target is in EL1 or EL2 or EL3.
Without this patch, an error:
Error: Opcode 0xd5384020, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $ELR_EL1
or through OpenOCD command
reg ELR_EL1
Detect the EL and return error if the register cannot be accessed.
Change-Id: I402dda4cd9dae502b05572fc6c1a8f0edf349bb1
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8274
Tested-by: jenkins
diff --git a/src/target/armv8.c b/src/target/armv8.c
index b622dc990..176747013 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -315,6 +315,11 @@ static int armv8_read_reg(struct armv8_common *armv8, int regnum, uint64_t *regv
value_64 = value;
break;
case ARMV8_ELR_EL1:
+ if (curel < SYSTEM_CUREL_EL1) {
+ LOG_DEBUG("ELR_EL1 not accessible in EL%u", curel);
+ retval = ERROR_FAIL;
+ break;
+ }
retval = dpm->instr_read_data_r0_64(dpm,
ARMV8_MRS(SYSTEM_ELR_EL1, 0), &value_64);
break;
@@ -463,6 +468,11 @@ static int armv8_write_reg(struct armv8_common *armv8, int regnum, uint64_t valu
break;
/* registers clobbered by taking exception in debug state */
case ARMV8_ELR_EL1:
+ if (curel < SYSTEM_CUREL_EL1) {
+ LOG_DEBUG("ELR_EL1 not accessible in EL%u", curel);
+ retval = ERROR_FAIL;
+ break;
+ }
retval = dpm->instr_write_data_r0_64(dpm,
ARMV8_MSR_GP(SYSTEM_ELR_EL1, 0), value_64);
break;
commit 2a63fabd095044f0a05cf69a34300409809f676b
Author: Antonio Borneo <bor...@gm...>
Date: Tue May 14 12:16:13 2024 +0200
target: aarch64: access reg SPSR_EL2 only in EL2 and EL3
The register SPSR_EL2 is accessible and it's content is relevant
only when the target is in EL2 or EL3.
Virtualization SW in EL1 can also access it, but this either
triggers a trap to EL2 or returns SPSR_EL1. Debugger should not
mix the real SPSR_EL2 with the virtual register.
Plus, the register is 64 bits wide.
Without this patch, an error:
Error: Opcode 0xd53c4000, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $SPSR_EL2
or through OpenOCD command
reg SPSR_EL2
Detect the EL and return error if the register cannot be accessed.
Handle the register as 64 bits.
Change-Id: If3792296b36282c08d597dd46cfe044d6b8288ea
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8273
Tested-by: jenkins
diff --git a/src/target/armv8.c b/src/target/armv8.c
index 49fcb7217..b622dc990 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -365,9 +365,13 @@ static int armv8_read_reg(struct armv8_common *armv8, int regnum, uint64_t *regv
value_64 = value;
break;
case ARMV8_SPSR_EL2:
- retval = dpm->instr_read_data_r0(dpm,
- ARMV8_MRS(SYSTEM_SPSR_EL2, 0), &value);
- value_64 = value;
+ if (curel < SYSTEM_CUREL_EL2) {
+ LOG_DEBUG("SPSR_EL2 not accessible in EL%u", curel);
+ retval = ERROR_FAIL;
+ break;
+ }
+ retval = dpm->instr_read_data_r0_64(dpm,
+ ARMV8_MRS(SYSTEM_SPSR_EL2, 0), &value_64);
break;
case ARMV8_SPSR_EL3:
if (curel < SYSTEM_CUREL_EL3) {
@@ -509,9 +513,13 @@ static int armv8_write_reg(struct armv8_common *armv8, int regnum, uint64_t valu
ARMV8_MSR_GP(SYSTEM_SPSR_EL1, 0), value);
break;
case ARMV8_SPSR_EL2:
- value = value_64;
- retval = dpm->instr_write_data_r0(dpm,
- ARMV8_MSR_GP(SYSTEM_SPSR_EL2, 0), value);
+ if (curel < SYSTEM_CUREL_EL2) {
+ LOG_DEBUG("SPSR_EL2 not accessible in EL%u", curel);
+ retval = ERROR_FAIL;
+ break;
+ }
+ retval = dpm->instr_write_data_r0_64(dpm,
+ ARMV8_MSR_GP(SYSTEM_SPSR_EL2, 0), value_64);
break;
case ARMV8_SPSR_EL3:
if (curel < SYSTEM_CUREL_EL3) {
@@ -1563,7 +1571,7 @@ static const struct {
NULL},
{ ARMV8_ESR_EL2, "ESR_EL2", 64, ARMV8_64_EL2H, REG_TYPE_UINT64, "banked", "net.sourceforge.openocd.banked",
NULL},
- { ARMV8_SPSR_EL2, "SPSR_EL2", 32, ARMV8_64_EL2H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked",
+ { ARMV8_SPSR_EL2, "SPSR_EL2", 64, ARMV8_64_EL2H, REG_TYPE_UINT64, "banked", "net.sourceforge.openocd.banked",
NULL},
{ ARMV8_ELR_EL3, "ELR_EL3", 64, ARMV8_64_EL3H, REG_TYPE_CODE_PTR, "banked", "net.sourceforge.openocd.banked",
commit 766a84b79892c1321f3f86d3f1b301519269b4f5
Author: Antonio Borneo <bor...@gm...>
Date: Tue May 14 12:07:58 2024 +0200
target: aarch64: access reg ESR_EL2 only in EL2 and EL3
The register ESR_EL2 is accessible and it's content is relevant
only when the target is in EL2 or EL3.
Virtualization SW in EL1 can also access it, but this either
triggers a trap to EL2 or returns ESR_EL1. Debugger should not mix
the real ESR_EL2 with the virtual register.
Plus, the register is 64 bits wide.
Without this patch, an error:
Error: Opcode 0xd53c5200, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $ESR_EL2
or through OpenOCD command
reg ESR_EL2
Detect the EL and return error if the register cannot be accessed.
Handle the register as 64 bits.
Change-Id: Icb32b44886d50907f29b068ce61e4be8bed10208
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8272
Tested-by: jenkins
diff --git a/src/target/armv8.c b/src/target/armv8.c
index a537d610c..49fcb7217 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -342,9 +342,13 @@ static int armv8_read_reg(struct armv8_common *armv8, int regnum, uint64_t *regv
value_64 = value;
break;
case ARMV8_ESR_EL2:
- retval = dpm->instr_read_data_r0(dpm,
- ARMV8_MRS(SYSTEM_ESR_EL2, 0), &value);
- value_64 = value;
+ if (curel < SYSTEM_CUREL_EL2) {
+ LOG_DEBUG("ESR_EL2 not accessible in EL%u", curel);
+ retval = ERROR_FAIL;
+ break;
+ }
+ retval = dpm->instr_read_data_r0_64(dpm,
+ ARMV8_MRS(SYSTEM_ESR_EL2, 0), &value_64);
break;
case ARMV8_ESR_EL3:
if (curel < SYSTEM_CUREL_EL3) {
@@ -482,9 +486,13 @@ static int armv8_write_reg(struct armv8_common *armv8, int regnum, uint64_t valu
ARMV8_MSR_GP(SYSTEM_ESR_EL1, 0), value);
break;
case ARMV8_ESR_EL2:
- value = value_64;
- retval = dpm->instr_write_data_r0(dpm,
- ARMV8_MSR_GP(SYSTEM_ESR_EL2, 0), value);
+ if (curel < SYSTEM_CUREL_EL2) {
+ LOG_DEBUG("ESR_EL2 not accessible in EL%u", curel);
+ retval = ERROR_FAIL;
+ break;
+ }
+ retval = dpm->instr_write_data_r0_64(dpm,
+ ARMV8_MSR_GP(SYSTEM_ESR_EL2, 0), value_64);
break;
case ARMV8_ESR_EL3:
if (curel < SYSTEM_CUREL_EL3) {
@@ -1553,7 +1561,7 @@ static const struct {
{ ARMV8_ELR_EL2, "ELR_EL2", 64, ARMV8_64_EL2H, REG_TYPE_CODE_PTR, "banked", "net.sourceforge.openocd.banked",
NULL},
- { ARMV8_ESR_EL2, "ESR_EL2", 32, ARMV8_64_EL2H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked",
+ { ARMV8_ESR_EL2, "ESR_EL2", 64, ARMV8_64_EL2H, REG_TYPE_UINT64, "banked", "net.sourceforge.openocd.banked",
NULL},
{ ARMV8_SPSR_EL2, "SPSR_EL2", 32, ARMV8_64_EL2H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked",
NULL},
-----------------------------------------------------------------------
Summary of changes:
src/target/armv8.c | 54 ++++++++++++++++++++++++++++++++++++++++--------------
1 file changed, 40 insertions(+), 14 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
