[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-622-g190176a6b

[openocd-gerrit <ope...@us...>]

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- Log -----------------------------------------------------------------
commit 190176a6bc947fd2516b959217084e531374b9bf
Author: Antonio Borneo <bor...@gm...>
Date:   Tue May 14 11:03:45 2024 +0200

    target: aarch64: access reg ELR_EL2 only in EL2 and EL3
    
    The register ELR_EL2 is accessible and it's content is relevant
    only when the target is in EL2 or EL3.
    Virtualization SW in EL1 can also access it, but this either
    triggers a trap to EL2 or returns ELR_EL1. Debugger should not mix
    the real ELR_EL2 with the virtual register.
    
    Without this patch, an error:
            Error: Opcode 0xd53c4020, DSCR.ERR=1, DSCR.EL=1
    is triggered by GDB register window or through GDB command
            x/p $ELR_EL2
    or through OpenOCD command
            reg ELR_EL2
    
    Detect the EL and return error if the register cannot be accessed.
    
    Change-Id: Idf02b42a7339df83260c1e44ceabbb05fbf392b9
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8271
    Tested-by: jenkins

diff --git a/src/target/armv8.c b/src/target/armv8.c
index e8c189c1c..a537d610c 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -319,6 +319,11 @@ static int armv8_read_reg(struct armv8_common *armv8, int regnum, uint64_t *regv
 				ARMV8_MRS(SYSTEM_ELR_EL1, 0), &value_64);
 		break;
 	case ARMV8_ELR_EL2:
+		if (curel < SYSTEM_CUREL_EL2) {
+			LOG_DEBUG("ELR_EL2 not accessible in EL%u", curel);
+			retval = ERROR_FAIL;
+			break;
+		}
 		retval = dpm->instr_read_data_r0_64(dpm,
 				ARMV8_MRS(SYSTEM_ELR_EL2, 0), &value_64);
 		break;
@@ -454,6 +459,11 @@ static int armv8_write_reg(struct armv8_common *armv8, int regnum, uint64_t valu
 				ARMV8_MSR_GP(SYSTEM_ELR_EL1, 0), value_64);
 		break;
 	case ARMV8_ELR_EL2:
+		if (curel < SYSTEM_CUREL_EL2) {
+			LOG_DEBUG("ELR_EL2 not accessible in EL%u", curel);
+			retval = ERROR_FAIL;
+			break;
+		}
 		retval = dpm->instr_write_data_r0_64(dpm,
 				ARMV8_MSR_GP(SYSTEM_ELR_EL2, 0), value_64);
 		break;

commit 405e78771b7f2a09298b675e7fbd05803672416c
Author: Antonio Borneo <bor...@gm...>
Date:   Tue May 14 10:40:32 2024 +0200

    target: aarch64: access reg SPSR_EL3 only in EL3
    
    The register SPSR_EL3 is accessible and it's content is relevant
    only when the target is in EL3.
    Plus, the register is 64 bits wide.
    
    Without this patch, an error:
            Error: Opcode 0xd53e4000, DSCR.ERR=1, DSCR.EL=1
    is triggered by GDB register window or through GDB command
            x/p $SPSR_EL3
    or through OpenOCD command
            reg SPSR_EL3
    
    Detect the EL and return error if the register cannot be accessed.
    Handle the register as 64 bits.
    
    Change-Id: I00849d99feeb96589c426fcafda98127dbd19a67
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8270
    Tested-by: jenkins

diff --git a/src/target/armv8.c b/src/target/armv8.c
index 383ac3ef4..e8c189c1c 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -361,9 +361,13 @@ static int armv8_read_reg(struct armv8_common *armv8, int regnum, uint64_t *regv
 		value_64 = value;
 		break;
 	case ARMV8_SPSR_EL3:
-		retval = dpm->instr_read_data_r0(dpm,
-				ARMV8_MRS(SYSTEM_SPSR_EL3, 0), &value);
-		value_64 = value;
+		if (curel < SYSTEM_CUREL_EL3) {
+			LOG_DEBUG("SPSR_EL3 not accessible in EL%u", curel);
+			retval = ERROR_FAIL;
+			break;
+		}
+		retval = dpm->instr_read_data_r0_64(dpm,
+				ARMV8_MRS(SYSTEM_SPSR_EL3, 0), &value_64);
 		break;
 	case ARMV8_PAUTH_CMASK:
 	case ARMV8_PAUTH_DMASK:
@@ -492,9 +496,13 @@ static int armv8_write_reg(struct armv8_common *armv8, int regnum, uint64_t valu
 				ARMV8_MSR_GP(SYSTEM_SPSR_EL2, 0), value);
 		break;
 	case ARMV8_SPSR_EL3:
-		value = value_64;
-		retval = dpm->instr_write_data_r0(dpm,
-				ARMV8_MSR_GP(SYSTEM_SPSR_EL3, 0), value);
+		if (curel < SYSTEM_CUREL_EL3) {
+			LOG_DEBUG("SPSR_EL3 not accessible in EL%u", curel);
+			retval = ERROR_FAIL;
+			break;
+		}
+		retval = dpm->instr_write_data_r0_64(dpm,
+				ARMV8_MSR_GP(SYSTEM_SPSR_EL3, 0), value_64);
 		break;
 	default:
 		retval = ERROR_FAIL;
@@ -1544,7 +1552,7 @@ static const struct {
 														NULL},
 	{ ARMV8_ESR_EL3, "ESR_EL3", 64, ARMV8_64_EL3H, REG_TYPE_UINT64, "banked", "net.sourceforge.openocd.banked",
 														NULL},
-	{ ARMV8_SPSR_EL3, "SPSR_EL3", 32, ARMV8_64_EL3H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked",
+	{ ARMV8_SPSR_EL3, "SPSR_EL3", 64, ARMV8_64_EL3H, REG_TYPE_UINT64, "banked", "net.sourceforge.openocd.banked",
 														NULL},
 	{ ARMV8_PAUTH_DMASK, "pauth_dmask", 64, ARM_MODE_ANY, REG_TYPE_UINT64, NULL, "org.gnu.gdb.aarch64.pauth", NULL},
 	{ ARMV8_PAUTH_CMASK, "pauth_cmask", 64, ARM_MODE_ANY, REG_TYPE_UINT64, NULL, "org.gnu.gdb.aarch64.pauth", NULL},

-----------------------------------------------------------------------

Summary of changes:
 src/target/armv8.c | 32 +++++++++++++++++++++++++-------
 1 file changed, 25 insertions(+), 7 deletions(-)


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