Menu
▾
▴
[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-620-g230680916
|
From: openocd-gerrit <ope...@us...> - 2024-06-23 09:29:02
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 230680916039ba413278b74f3440ffa49e55de27 (commit)
via 8c75e4760333a4e0408bdf9dd58a702e4fb67c51 (commit)
from bcd6a1022322f67f25f74af2dfe40d440d382e74 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 230680916039ba413278b74f3440ffa49e55de27
Author: Antonio Borneo <bor...@gm...>
Date: Tue May 14 10:03:09 2024 +0200
target: aarch64: access reg ESR_EL3 only in EL3
The register ESR_EL3 is accessible and it's content is relevant
only when the target is in EL3.
Plus, the register is 64 bits wide.
Without this patch, an error:
Error: Opcode 0xd53e5200, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $ESR_EL3
or through OpenOCD command
reg ESR_EL3
Detect the EL and return error if the register cannot be accessed.
Handle the register as 64 bits.
Drop the FIXME comment on Aarch32 case, as the register exists in
Aarch64 only.
Change-Id: Ie8c69dc7b50ae81a52506cf151c8e64e15752d0d
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8269
Tested-by: jenkins
diff --git a/src/target/armv8.c b/src/target/armv8.c
index e36e2f6f4..383ac3ef4 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -342,9 +342,13 @@ static int armv8_read_reg(struct armv8_common *armv8, int regnum, uint64_t *regv
value_64 = value;
break;
case ARMV8_ESR_EL3:
- retval = dpm->instr_read_data_r0(dpm,
- ARMV8_MRS(SYSTEM_ESR_EL3, 0), &value);
- value_64 = value;
+ if (curel < SYSTEM_CUREL_EL3) {
+ LOG_DEBUG("ESR_EL3 not accessible in EL%u", curel);
+ retval = ERROR_FAIL;
+ break;
+ }
+ retval = dpm->instr_read_data_r0_64(dpm,
+ ARMV8_MRS(SYSTEM_ESR_EL3, 0), &value_64);
break;
case ARMV8_SPSR_EL1:
retval = dpm->instr_read_data_r0(dpm,
@@ -469,9 +473,13 @@ static int armv8_write_reg(struct armv8_common *armv8, int regnum, uint64_t valu
ARMV8_MSR_GP(SYSTEM_ESR_EL2, 0), value);
break;
case ARMV8_ESR_EL3:
- value = value_64;
- retval = dpm->instr_write_data_r0(dpm,
- ARMV8_MSR_GP(SYSTEM_ESR_EL3, 0), value);
+ if (curel < SYSTEM_CUREL_EL3) {
+ LOG_DEBUG("ESR_EL3 not accessible in EL%u", curel);
+ retval = ERROR_FAIL;
+ break;
+ }
+ retval = dpm->instr_write_data_r0_64(dpm,
+ ARMV8_MSR_GP(SYSTEM_ESR_EL3, 0), value_64);
break;
case ARMV8_SPSR_EL1:
value = value_64;
@@ -575,7 +583,7 @@ static int armv8_read_reg32(struct armv8_common *armv8, int regnum, uint64_t *re
ARMV4_5_MRC(15, 4, 0, 5, 2, 0),
&value);
break;
- case ARMV8_ESR_EL3: /* FIXME: no equivalent in aarch32? */
+ case ARMV8_ESR_EL3: /* no equivalent in aarch32 */
retval = ERROR_FAIL;
break;
case ARMV8_SPSR_EL1: /* mapped to SPSR_svc */
@@ -711,7 +719,7 @@ static int armv8_write_reg32(struct armv8_common *armv8, int regnum, uint64_t va
ARMV4_5_MCR(15, 4, 0, 5, 2, 0),
value);
break;
- case ARMV8_ESR_EL3: /* FIXME: no equivalent in aarch32? */
+ case ARMV8_ESR_EL3: /* no equivalent in aarch32 */
retval = ERROR_FAIL;
break;
case ARMV8_SPSR_EL1: /* mapped to SPSR_svc */
@@ -1534,7 +1542,7 @@ static const struct {
{ ARMV8_ELR_EL3, "ELR_EL3", 64, ARMV8_64_EL3H, REG_TYPE_CODE_PTR, "banked", "net.sourceforge.openocd.banked",
NULL},
- { ARMV8_ESR_EL3, "ESR_EL3", 32, ARMV8_64_EL3H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked",
+ { ARMV8_ESR_EL3, "ESR_EL3", 64, ARMV8_64_EL3H, REG_TYPE_UINT64, "banked", "net.sourceforge.openocd.banked",
NULL},
{ ARMV8_SPSR_EL3, "SPSR_EL3", 32, ARMV8_64_EL3H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked",
NULL},
commit 8c75e4760333a4e0408bdf9dd58a702e4fb67c51
Author: Antonio Borneo <bor...@gm...>
Date: Mon May 13 18:19:55 2024 +0200
target: aarch64: access reg ELR_EL3 only in EL3
The register ELR_EL3 is accessible and it's content is relevant
only when the target is in EL3.
Without this patch, an error:
Error: Opcode 0xd53e4020, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $ELR_EL3
or through OpenOCD command
reg ELR_EL3
Detect the EL and return error if the register cannot be accessed.
Change-Id: I545abb196e5c34e462c7e5d5d3ec952e588642da
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8268
Tested-by: jenkins
diff --git a/src/target/armv8.c b/src/target/armv8.c
index 8d97902f5..e36e2f6f4 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -278,6 +278,7 @@ static int armv8_get_pauth_mask(struct armv8_common *armv8, uint64_t *mask)
static int armv8_read_reg(struct armv8_common *armv8, int regnum, uint64_t *regval)
{
struct arm_dpm *dpm = &armv8->dpm;
+ unsigned int curel = armv8_curel_from_core_mode(dpm->arm->core_mode);
int retval;
uint32_t value;
uint64_t value_64;
@@ -322,6 +323,11 @@ static int armv8_read_reg(struct armv8_common *armv8, int regnum, uint64_t *regv
ARMV8_MRS(SYSTEM_ELR_EL2, 0), &value_64);
break;
case ARMV8_ELR_EL3:
+ if (curel < SYSTEM_CUREL_EL3) {
+ LOG_DEBUG("ELR_EL3 not accessible in EL%u", curel);
+ retval = ERROR_FAIL;
+ break;
+ }
retval = dpm->instr_read_data_r0_64(dpm,
ARMV8_MRS(SYSTEM_ELR_EL3, 0), &value_64);
break;
@@ -396,6 +402,7 @@ static int armv8_read_reg_simdfp_aarch64(struct armv8_common *armv8, int regnum,
static int armv8_write_reg(struct armv8_common *armv8, int regnum, uint64_t value_64)
{
struct arm_dpm *dpm = &armv8->dpm;
+ unsigned int curel = armv8_curel_from_core_mode(dpm->arm->core_mode);
int retval;
uint32_t value;
@@ -443,6 +450,11 @@ static int armv8_write_reg(struct armv8_common *armv8, int regnum, uint64_t valu
ARMV8_MSR_GP(SYSTEM_ELR_EL2, 0), value_64);
break;
case ARMV8_ELR_EL3:
+ if (curel < SYSTEM_CUREL_EL3) {
+ LOG_DEBUG("ELR_EL3 not accessible in EL%u", curel);
+ retval = ERROR_FAIL;
+ break;
+ }
retval = dpm->instr_write_data_r0_64(dpm,
ARMV8_MSR_GP(SYSTEM_ELR_EL3, 0), value_64);
break;
-----------------------------------------------------------------------
Summary of changes:
src/target/armv8.c | 38 +++++++++++++++++++++++++++++---------
1 file changed, 29 insertions(+), 9 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
