From: openocd-gerrit <ope...@us...> - 2023-12-30 13:13:57
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This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via a90b1642ec1c5dc12c7d9d2af806efee582f7b19 (commit) from 5394e5b762ec01bef6bd5b00faa63b3361599e24 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit a90b1642ec1c5dc12c7d9d2af806efee582f7b19 Author: Marc Schink <de...@za...> Date: Sat May 13 12:24:04 2023 +0200 flash/nor/stm32f1x: Add support for Geehy APM32F0 series Tested with APM32F030C8T. Change-Id: I63cd8b66424135dae481a96ba560e6f0b1f9544e Suggested-by: Christian U <in...@cu...> Signed-off-by: Marc Schink <de...@za...> Reviewed-on: https://review.openocd.org/c/openocd/+/8014 Tested-by: jenkins Reviewed-by: Tomas Vanek <va...@fb...> Reviewed-by: Antonio Borneo <bor...@gm...> diff --git a/doc/openocd.texi b/doc/openocd.texi index 7467e6ad9..395d03ca2 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -7707,12 +7707,10 @@ applied to all of them. @end deffn @deffn {Flash Driver} {stm32f1x} -All members of the STM32F0, STM32F1 and STM32F3 microcontroller families -from STMicroelectronics and all members of the GD32F1x0, GD32F3x0 and GD32E23x microcontroller -families from GigaDevice include internal flash and use ARM Cortex-M0/M3/M4/M23 cores. -The driver also works with GD32VF103 powered by RISC-V core. -The driver automatically recognizes a number of these chips using -the chip identification register, and autoconfigures itself. +This driver supports the STM32F0, STM32F1 and STM32F3 microcontroller series from STMicroelectronics. +The driver is also compatible with the GD32F1, GD32VF103 (RISC-V core), GD32F3 and GD32E23 microcontroller series from GigaDevice. +The driver also supports the APM32F0 series from Geehy Semiconductor. +The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself. @example flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME diff --git a/src/flash/nor/stm32f1x.c b/src/flash/nor/stm32f1x.c index b3bb84335..5a3c2da66 100644 --- a/src/flash/nor/stm32f1x.c +++ b/src/flash/nor/stm32f1x.c @@ -745,6 +745,7 @@ static int stm32x_get_property_addr(struct target *target, struct stm32x_propert switch (cortex_m_get_impl_part(target)) { case CORTEX_M0_PARTNO: /* STM32F0x devices */ + case CORTEX_M0P_PARTNO: /* APM32F0x devices */ addr->device_id = 0x40015800; addr->flash_size = 0x1FFFF7CC; return ERROR_OK; ----------------------------------------------------------------------- Summary of changes: doc/openocd.texi | 10 ++++------ src/flash/nor/stm32f1x.c | 1 + 2 files changed, 5 insertions(+), 6 deletions(-) hooks/post-receive -- Main OpenOCD repository |