[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-376-g5ea20d7ed

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- Log -----------------------------------------------------------------
commit 5ea20d7ed99e252947a85f93db870109cc094efc
Author: Nishanth Menon <nm...@ti...>
Date:   Wed Oct 18 13:45:39 2023 -0500

    tcl/target/ti_k3: Convert memory access ap port num as a variable
    
    Convert the memory access ap port num as a variable to allow support
    for the AM2x family of K3 SoCs.
    
    Change-Id: Ibd96c94055721f60d95179dab21d014c15b0f562
    Signed-off-by: Nishanth Menon <nm...@ti...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7943
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index e05b81a17..bb2a991ce 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -66,6 +66,9 @@ set _gp_mcu_cores 0
 # General Purpose MCU power-ap unlock offsets
 set _gp_mcu_ap_unlock_offsets {0xf0 0x60}
 
+# Generic mem-ap port number
+set _mem_ap_num 2
+
 # Set configuration overrides for each SOC
 switch $_soc {
 	am654 {
@@ -423,5 +426,5 @@ if { 0 == [string compare [adapter name] dmem ] } {
 	}
 } else {
 	# AXI AP access port for SoC address map
-	target create $_CHIPNAME.axi_ap mem_ap -dap $_CHIPNAME.dap -ap-num 2
+	target create $_CHIPNAME.axi_ap mem_ap -dap $_CHIPNAME.dap -ap-num $_mem_ap_num
 }

commit 4b879bb01737f11a11f05c3b4feb09e6ddc85a5d
Author: Nishanth Menon <nm...@ti...>
Date:   Tue Oct 17 13:56:00 2023 -0500

    tcl/target/ti_k3: Convert Cortex-R5 ap port num as a variable
    
    Convert the Cortex-R5 ap port num as a variable to allow support for
    the AM2x family of K3 SoCs.
    
    Change-Id: I7dc8b459dca8b5f21395230b5cb782b14538bd48
    Signed-off-by: Nishanth Menon <nm...@ti...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7942
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index 78ee8b2ca..e05b81a17 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -56,6 +56,7 @@ set ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000}
 set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000}
 set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000}
 set R5_NAMES {mcu_r5.0 mcu_r5.1 main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
+set _r5_ap_num 1
 
 # Finally an General Purpose(GP) MCU
 set CM4_CTIBASE		{0x20001000}
@@ -359,12 +360,12 @@ if { $_v8_smp_debug == 0 } {
 
 for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
 	set _r5_name [lindex $R5_NAMES $_core]
-	cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num 1 \
+	cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num $_r5_ap_num \
 		-baseaddr [lindex $R5_CTIBASE $_core]
 
 	# inactive core examination will fail - wait till startup of additional core
 	target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \
-		-dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine \
+		-dbgbase [lindex $R5_DBGBASE $_core] -ap-num $_r5_ap_num -defer-examine \
 		-rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_r5_name]
 
 	$_TARGETNAME.$_r5_name configure -event gdb-attach {

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/ti_k3.cfg | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)


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