[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-265-g93002a86c

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- Log -----------------------------------------------------------------
commit 93002a86cde9cf95a894bdc099b67d6379e22cd3
Author: Erhan Kurubas <erh...@es...>
Date:   Sun Jun 18 11:18:31 2023 +0200

    tcl/target: update esp32s2.cfg to reference shared functions in the esp_common.cfg
    
    This commit enhances code reusability, simplifies maintenance, and ensures
    consistency across all chip configurations by consolidating commonly used
    commands and variables into the common config file.
    
    Signed-off-by: Erhan Kurubas <erh...@es...>
    Change-Id: I36c86fe4ebc99928ce48a5bff8cb9580a0fa3ac0
    Reviewed-on: https://review.openocd.org/c/openocd/+/7746
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/target/esp32s2.cfg b/tcl/target/esp32s2.cfg
index e478a6d39..4c1362a34 100644
--- a/tcl/target/esp32s2.cfg
+++ b/tcl/target/esp32s2.cfg
@@ -1,32 +1,17 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 #
-# The ESP32-S2 only supports JTAG.
-transport select jtag
 
-set CPU_MAX_ADDRESS 0xFFFFFFFF
-source [find bitsbytes.tcl]
-source [find memory.tcl]
-source [find mmr_helpers.tcl]
-# Source the ESP common configuration file
+# Source the ESP common configuration file.
 source [find target/esp_common.cfg]
 
-if { [info exists CHIPNAME] } {
-	set _CHIPNAME $CHIPNAME
-} else {
-	set _CHIPNAME esp32s2
-}
-
-if { [info exists CPUTAPID] } {
-	set _CPUTAPID $CPUTAPID
-} else {
-	set _CPUTAPID 0x120034e5
-}
-
-set _TARGETNAME $_CHIPNAME
-set _CPUNAME cpu
-set _TAPNAME $_CHIPNAME.$_CPUNAME
-
-jtag newtap $_CHIPNAME $_CPUNAME -irlen 5 -expected-id $_CPUTAPID
+# Target specific global variables
+set _CHIPNAME 					"esp32s2"
+set _CPUTAPID 					0x120034e5
+set _ESP_ARCH					"xtensa"
+set _ONLYCPU					1
+set _ESP_SMP_TARGET				0
+set _ESP_SMP_BREAK 				1
+set _ESP_EFUSE_MAC_ADDR_REG  	0x3f41A004
 
 proc esp32s2_memprot_is_enabled { } {
 	# IRAM0, DPORT_PMS_PRO_IRAM0_0_REG
@@ -48,33 +33,10 @@ proc esp32s2_memprot_is_enabled { } {
 	return 0
 }
 
-target create $_TARGETNAME esp32s2 -endian little -chain-position $_TAPNAME
-
-$_TARGETNAME configure -event gdb-attach {
-	# necessary to auto-probe flash bank when GDB is connected and generate proper memory map
-	halt 1000
-	if { [esp32s2_memprot_is_enabled] } {
-		# 'reset halt' to disable memory protection and allow flasher to work correctly
-		echo "Memory protection is enabled. Reset target to disable it..."
-		reset halt
-	}
-}
-
-xtensa maskisr on
-
-$_TARGETNAME configure -event examine-end {
-	# Need to enable to set 'semihosting_basedir'
-	arm semihosting enable
-	arm semihosting_resexit enable
-	if { [info exists _SEMIHOST_BASEDIR] } {
-		if { $_SEMIHOST_BASEDIR != "" } {
-			arm semihosting_basedir $_SEMIHOST_BASEDIR
-		}
-	}
+proc esp32s2_soc_reset { } {
+	soft_reset_halt
 }
 
-$_TARGETNAME configure -event reset-assert-post { soft_reset_halt }
-
-gdb_breakpoint_override hard
+create_esp_target $_ESP_ARCH
 
 source [find target/xtensa-core-esp32s2.cfg]

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/esp32s2.cfg | 62 ++++++++++----------------------------------------
 1 file changed, 12 insertions(+), 50 deletions(-)


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