[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-rc1-55-gb8735bbf7

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- Log -----------------------------------------------------------------
commit b8735bbf7ed7eedb0590edbf2a22929b401887ba
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Oct 16 23:56:23 2022 +0200

    doc: fix riscv commands
    
    - Fix the declaration of riscv command 'set_mem_access'.
    - Remove non existing riscv command 'set_scratch_ram'.
    - Add riscv commands 'info', 'reset_delays'; copy the description
      from the 'help' text.
    - Don't add riscv commands 'set_prefer_sba' and 'test_sba_config_reg'
      as they are marked as deprecated.
    - Ensure that 'test_sba_config_reg' prints a deprecation warning
      when used.
    
    Change-Id: I39dc3aec4e7f13b69ac19685f1b593790acdde83
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Signed-off-by: Jan Matyas <ma...@co...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7268
    Reviewed-by: Tim Newsome <ti...@si...>
    Tested-by: jenkins

diff --git a/doc/openocd.texi b/doc/openocd.texi
index ba495ccd1..6321bf7a6 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -10649,6 +10649,16 @@ $_TARGETNAME expose_custom 32=myregister
 @end example
 @end deffn
 
+@deffn {Command} {riscv info}
+Displays some information OpenOCD detected about the target.
+@end deffn
+
+@deffn {Command} {riscv reset_delays} [wait]
+OpenOCD learns how many Run-Test/Idle cycles are required between scans to avoid
+encountering the target being busy. This command resets those learned values
+after `wait` scans. It's only useful for testing OpenOCD itself.
+@end deffn
+
 @deffn {Command} {riscv set_command_timeout_sec} [seconds]
 Set the wall-clock timeout (in seconds) for individual commands. The default
 should work fine for all but the slowest targets (eg. simulators).
@@ -10659,12 +10669,7 @@ Set the maximum time to wait for a hart to come out of reset after reset is
 deasserted.
 @end deffn
 
-@deffn {Command} {riscv set_scratch_ram} none|[address]
-Set the address of 16 bytes of scratch RAM the debugger can use, or 'none'.
-This is used to access 64-bit floating point registers on 32-bit targets.
-@end deffn
-
-@deffn Command {riscv set_mem_access} method1 [method2] [method3]
+@deffn {Command} {riscv set_mem_access} method1 [method2] [method3]
 Specify which RISC-V memory access method(s) shall be used, and in which order
 of priority. At least one method must be specified.
 
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index ae0a7375d..4f24fb41e 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -2744,6 +2744,9 @@ COMMAND_HANDLER(riscv_dmi_write)
 
 COMMAND_HANDLER(riscv_test_sba_config_reg)
 {
+	LOG_WARNING("Command \"riscv test_sba_config_reg\" is deprecated. "
+		"It will be removed in a future OpenOCD version.");
+
 	if (CMD_ARGC != 4) {
 		LOG_ERROR("Command takes exactly 4 arguments");
 		return ERROR_COMMAND_SYNTAX_ERROR;

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi         | 17 +++++++++++------
 src/target/riscv/riscv.c |  3 +++
 2 files changed, 14 insertions(+), 6 deletions(-)


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