[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-rc1-25-gbced97cce

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- Log -----------------------------------------------------------------
commit bced97cce95a31987f18674bb022e6d263b4f29c
Author: Tomas Vanek <va...@fb...>
Date:   Sun Oct 2 09:30:50 2022 +0200

    target/armv7m: prevent storing invalid register
    
    armv7m_start_algorithm() stored all non-debug execution
    registers from register cache without checking validity.
    
    Check if the register cache is valid.
    Try to read from CPU if not valid.
    Issue a warning if register read fails.
    
    Change-Id: I365f86d65243230cf521b13909575e5986a87a50
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7240
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Reviewed-by: Jonathan Bell <jon...@ra...>

diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index 2db2ce2dd..6f6a170b7 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -528,11 +528,14 @@ int armv7m_start_algorithm(struct target *target,
 
 	/* Store all non-debug execution registers to armv7m_algorithm_info context */
 	for (unsigned i = 0; i < armv7m->arm.core_cache->num_regs; i++) {
+		struct reg *reg = &armv7m->arm.core_cache->reg_list[i];
+		if (!reg->valid)
+			armv7m_get_core_reg(reg);
 
-		armv7m_algorithm_info->context[i] = buf_get_u32(
-				armv7m->arm.core_cache->reg_list[i].value,
-				0,
-				32);
+		if (!reg->valid)
+			LOG_TARGET_WARNING(target, "Storing invalid register %s", reg->name);
+
+		armv7m_algorithm_info->context[i] = buf_get_u32(reg->value, 0, 32);
 	}
 
 	for (int i = 0; i < num_mem_params; i++) {

-----------------------------------------------------------------------

Summary of changes:
 src/target/armv7m.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)


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