Menu
▾
▴
[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.11.0-813-gce5ca9f7b
|
From: OpenOCD-Gerrit <ope...@us...> - 2022-08-20 15:39:09
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via ce5ca9f7ba782ea9fba8ecd5fc1cb9407fd27949 (commit)
from be2e5c6c35f77fecb4df2a19cec05cceac500ca9 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit ce5ca9f7ba782ea9fba8ecd5fc1cb9407fd27949
Author: Ian Thompson <ia...@ca...>
Date: Fri Jun 24 22:27:32 2022 -0700
target: add generic Xtensa LX support
Generic Xtensa LX support extends the original Espressif/Xtensa
patch-set to support arbitrary Xtensa configurations, as defined in
a core-specific .cfg file. Not yet fully-featured. Additional
functionality to be added:
- Xtensa NX support
- DAP/SWD support
- File-IO support
- Generic Xtensa multi-core support
Valgrind-clean, no new Clang analyzer warnings
Signed-off-by: Ian Thompson <ia...@ca...>
Change-Id: I08e7bf8fa57c25b5d0cb75a1aa7a2ac13a380c52
Reviewed-on: https://review.openocd.org/c/openocd/+/7055
Tested-by: jenkins
Reviewed-by: Erhan Kurubas <erh...@es...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 9a5ab9a18..0df25406f 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -4906,6 +4906,7 @@ And two debug interfaces cores:
@item @code{testee} -- a dummy target for cases without a real CPU, e.g. CPLD.
@item @code{xscale} -- this is actually an architecture,
not a CPU type. It is based on the ARMv5 architecture.
+@item @code{xtensa} -- this is a generic Cadence/Tensilica Xtensa core.
@end itemize
@end deffn
@@ -10935,33 +10936,150 @@ OpenOCD supports debugging STM8 through the STMicroelectronics debug
protocol SWIM, @pxref{swimtransport,,SWIM}.
@section Xtensa Architecture
-Xtensa processors are based on a modular, highly flexible 32-bit RISC architecture
-that can easily scale from a tiny, cache-less controller or task engine to a high-performance
-SIMD/VLIW DSP provided by Cadence.
-@url{https://www.cadence.com/en_US/home/tools/ip/tensilica-ip/tensilica-xtensa-controllers-and-extensible-processors.html}.
-OpenOCD supports generic Xtensa processors implementation which can be customized by
-simply providing vendor-specific core configuration which controls every configurable
+Xtensa is a highly-customizable, user-extensible microprocessor and DSP
+architecture for complex embedded systems provided by Cadence Design
+Systems, Inc. See the
+@uref{https://www.cadence.com/en_US/home/tools/ip/tensilica-ip.html, Tensilica IP}
+website for additional information and documentation.
+
+OpenOCD supports generic Xtensa processor implementations which can be customized by
+providing a core-specific configuration file which describes every enabled
Xtensa architecture option, e.g. number of address registers, exceptions, reduced
-size instructions support, memory banks configuration etc. Also OpenOCD supports SMP
-configurations for Xtensa processors with any number of cores and allows to configure
-their debug signals interconnection (so-called "break/stall networks") which control how
-debug signals are distributed among cores. Xtensa "break networks" are compatible with
-ARM's Cross Trigger Interface (CTI). For debugging code on Xtensa chips OpenOCD
-uses JTAG protocol. Currently OpenOCD implements several Epsressif Xtensa-based chips of
+size instructions support, memory banks configuration etc. OpenOCD also supports SMP
+configurations for Xtensa processors with any number of cores and allows configuring
+their debug interconnect (termed "break/stall networks"), which control how debug
+signals are distributed among cores. Xtensa "break networks" are compatible with
+ARM's Cross Trigger Interface (CTI). OpenOCD implements both generic Xtensa targets
+as well as several Espressif Xtensa-based chips from the
@uref{https://www.espressif.com/en/products/socs, ESP32 family}.
-@subsection General Xtensa Commands
+OCD sessions for Xtensa processor and DSP targets are accessed via the Xtensa
+Debug Module (XDM), which provides external connectivity either through a
+traditional JTAG interface or an ARM DAP interface. If used, the DAP interface
+can control Xtensa targets through JTAG or SWD probes.
+
+@subsection Xtensa Core Configuration
+
+Due to the high level of configurability in Xtensa cores, the Xtensa target
+configuration comprises two categories:
+
+@enumerate
+@item Base Xtensa support common to all core configurations, and
+@item Core-specific support as configured for individual cores.
+@end enumerate
+
+All common Xtensa support is built into the OpenOCD Xtensa target layer and
+is enabled through a combination of TCL scripts: the target-specific
+@file{target/xtensa.cfg} and a board-specific @file{board/xtensa-*.cfg},
+similar to other target architectures.
+
+Importantly, core-specific configuration information must be provided by
+the user, and takes the form of an @file{xtensa-core-XXX.cfg} TCL script that
+defines the core's configurable features through a series of Xtensa
+configuration commands (detailed below).
+
+This core-specific @file{xtensa-core-XXX.cfg} file is typically either:
+
+@itemize @bullet
+@item Located within the Xtensa core configuration build as
+@file{src/config/xtensa-core-openocd.cfg}, or
+@item Generated by running the command @code{xt-gdb --dump-oocd-config}
+from the Xtensa processor tool-chain's command-line tools.
+@end itemize
+
+NOTE: @file{xtensa-core-XXX.cfg} must match the target Xtensa hardware
+connected to OpenOCD.
+
+Some example Xtensa configurations are bundled with OpenOCD for reference:
+@itemize @bullet
+@item Cadence Palladium VDebug emulation target. The user can combine their
+@file{xtensa-core-XXX.cfg} with the provided
+@file{board/xtensa-palladium-vdebug.cfg} to debug an emulated Xtensa RTL design.
+@item NXP MIMXRT685-EVK evaluation kit. The relevant configuration files are
+@file{board/xtensa-rt685-jlink.cfg} and @file{board/xtensa-core-nxp_rt600.cfg}.
+Additional information is provided by
+@uref{https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt600-evaluation-kit:MIMXRT685-EVK,
+NXP}.
+@end itemize
+
+@subsection Xtensa Configuration Commands
+
+@deffn {Command} {xtensa xtdef} (@option{LX}|@option{NX})
+Configure the Xtensa target architecture. Currently, Xtensa support is limited
+to LX6, LX7, and NX cores.
+@end deffn
+
+@deffn {Command} {xtensa xtopt} option value
+Configure Xtensa target options that are relevant to the debug subsystem.
+@var{option} is one of: @option{arnum}, @option{windowed},
+@option{cpenable}, @option{exceptions}, @option{intnum}, @option{hipriints},
+@option{excmlevel}, @option{intlevels}, @option{debuglevel},
+@option{ibreaknum}, or @option{dbreaknum}. @var{value} is an integer with
+the exact range determined by each particular option.
+
+NOTE: Some options are specific to Xtensa LX or Xtensa NX architecture, while
+others may be common to both but have different valid ranges.
+@end deffn
+
+@deffn {Command} {xtensa xtmem} (@option{iram}|@option{dram}|@option{sram}|@option{irom}|@option{drom}|@option{srom}) baseaddr bytes
+Configure Xtensa target memory. Memory type determines access rights,
+where RAMs are read/write while ROMs are read-only. @var{baseaddr} and
+@var{bytes} are both integers, typically hexadecimal and decimal, respectively.
+@end deffn
+
+@deffn {Command} {xtensa xtmem} (@option{icache}|@option{dcache}) linebytes cachebytes ways [writeback]
+Configure Xtensa processor cache. All parameters are required except for
+the optional @option{writeback} parameter; all are integers.
+@end deffn
+
+@deffn {Command} {xtensa xtmpu} numfgseg minsegsz lockable execonly
+Configure an Xtensa Memory Protection Unit (MPU). MPUs can restrict access
+and/or control cacheability of specific address ranges, but are lighter-weight
+than a full traditional MMU. All parameters are required; all are integers.
+@end deffn
+
+@deffn {Command} {xtensa xtmmu} numirefillentries numdrefillentries
+(Xtensa-LX only) Configure an Xtensa Memory Management Unit (MMU). Both
+parameters are required; both are integers.
+@end deffn
+
+@deffn {Command} {xtensa xtregs} numregs
+Configure the total number of registers for the Xtensa core. Configuration
+logic expects to subsequently process this number of @code{xtensa xtreg}
+definitions. @var{numregs} is an integer.
+@end deffn
+
+@deffn {Command} {xtensa xtregfmt} (@option{sparse}|@option{contiguous}) [general]
+Configure the type of register map used by GDB to access the Xtensa core.
+Generic Xtensa tools (e.g. xt-gdb) require @option{sparse} mapping (default) while
+Espressif tools expect @option{contiguous} mapping. Contiguous mapping takes an
+additional, optional integer parameter @option{numgregs}, which specifies the number
+of general registers used in handling g/G packets.
+@end deffn
+
+@deffn {Command} {xtensa xtreg} name offset
+Configure an Xtensa core register. All core registers are 32 bits wide,
+while TIE and user registers may have variable widths. @var{name} is a
+character string identifier while @var{offset} is a hexadecimal integer.
+@end deffn
+
+@subsection Xtensa Operation Commands
+
+@deffn {Command} {xtensa maskisr} (@option{on}|@option{off})
+(Xtensa-LX only) Mask or unmask Xtensa interrupts during instruction step.
+When masked, an interrupt that occurs during a step operation is handled and
+its ISR is executed, with the user's debug session returning after potentially
+executing many instructions. When unmasked, a triggered interrupt will result
+in execution progressing the requested number of instructions into the relevant
+vector/ISR code.
+@end deffn
@deffn {Command} {xtensa set_permissive} (0|1)
By default accessing memory beyond defined regions is forbidden. This commnd controls memory access address check.
When set to (1), skips access controls and address range check before read/write memory.
@end deffn
-@deffn {Command} {xtensa maskisr} (on|off)
-Selects whether interrupts will be disabled during stepping over single instruction. The default configuration is (off).
-@end deffn
-
@deffn {Command} {xtensa smpbreak} [none|breakinout|runstall] | [BreakIn] [BreakOut] [RunStallIn] [DebugModeOut]
Configures debug signals connection ("break network") for currently selected core.
@itemize @bullet
@@ -10985,6 +11103,13 @@ This feature is not well implemented and tested yet.
@end itemize
@end deffn
+@deffn {Command} {xtensa exe} <ascii-encoded hexadecimal instruction bytes>
+Execute arbitrary instruction(s) provided as an ascii string. The string represents an integer
+number of instruction bytes, thus its length must be even.
+@end deffn
+
+@subsection Xtensa Performance Monitor Configuration
+
@deffn {Command} {xtensa perfmon_enable} <counter_id> <select> [mask] [kernelcnt] [tracelevel]
Enable and start performance counter.
@itemize @bullet
@@ -11004,6 +11129,8 @@ whether to count.
Dump performance counter value. If no argument specified, dumps all counters.
@end deffn
+@subsection Xtensa Trace Configuration
+
@deffn {Command} {xtensa tracestart} [pc <pcval>/[<maskbitcount>]] [after <n> [ins|words]]
Set up and start a HW trace. Optionally set PC address range to trigger tracing stop when reached during program execution.
This command also allows to specify the amount of data to capture after stop trigger activation.
diff --git a/src/target/espressif/Makefile.am b/src/target/espressif/Makefile.am
index df002b33b..1b4f8062e 100644
--- a/src/target/espressif/Makefile.am
+++ b/src/target/espressif/Makefile.am
@@ -7,8 +7,5 @@ noinst_LTLIBRARIES += %D%/libespressif.la
%D%/esp_xtensa_smp.c \
%D%/esp_xtensa_smp.h \
%D%/esp32.c \
- %D%/esp32.h \
%D%/esp32s2.c \
- %D%/esp32s2.h \
- %D%/esp32s3.c \
- %D%/esp32s3.h
+ %D%/esp32s3.c
diff --git a/src/target/espressif/esp32.c b/src/target/espressif/esp32.c
index de8f1aacf..a083627fb 100644
--- a/src/target/espressif/esp32.c
+++ b/src/target/espressif/esp32.c
@@ -14,7 +14,6 @@
#include <target/target_type.h>
#include <target/smp.h>
#include "assert.h"
-#include "esp32.h"
#include "esp_xtensa_smp.h"
/*
@@ -70,204 +69,6 @@ implementation.
#define ESP32_RTC_CNTL_SW_CPU_STALL_REG (ESP32_RTCCNTL_BASE + 0xac)
#define ESP32_RTC_CNTL_SW_CPU_STALL_DEF 0x0
-
-/* this should map local reg IDs to GDB reg mapping as defined in xtensa-config.c 'rmap' in
- *xtensa-overlay */
-static const unsigned int esp32_gdb_regs_mapping[ESP32_NUM_REGS] = {
- XT_REG_IDX_PC,
- XT_REG_IDX_AR0, XT_REG_IDX_AR1, XT_REG_IDX_AR2, XT_REG_IDX_AR3,
- XT_REG_IDX_AR4, XT_REG_IDX_AR5, XT_REG_IDX_AR6, XT_REG_IDX_AR7,
- XT_REG_IDX_AR8, XT_REG_IDX_AR9, XT_REG_IDX_AR10, XT_REG_IDX_AR11,
- XT_REG_IDX_AR12, XT_REG_IDX_AR13, XT_REG_IDX_AR14, XT_REG_IDX_AR15,
- XT_REG_IDX_AR16, XT_REG_IDX_AR17, XT_REG_IDX_AR18, XT_REG_IDX_AR19,
- XT_REG_IDX_AR20, XT_REG_IDX_AR21, XT_REG_IDX_AR22, XT_REG_IDX_AR23,
- XT_REG_IDX_AR24, XT_REG_IDX_AR25, XT_REG_IDX_AR26, XT_REG_IDX_AR27,
- XT_REG_IDX_AR28, XT_REG_IDX_AR29, XT_REG_IDX_AR30, XT_REG_IDX_AR31,
- XT_REG_IDX_AR32, XT_REG_IDX_AR33, XT_REG_IDX_AR34, XT_REG_IDX_AR35,
- XT_REG_IDX_AR36, XT_REG_IDX_AR37, XT_REG_IDX_AR38, XT_REG_IDX_AR39,
- XT_REG_IDX_AR40, XT_REG_IDX_AR41, XT_REG_IDX_AR42, XT_REG_IDX_AR43,
- XT_REG_IDX_AR44, XT_REG_IDX_AR45, XT_REG_IDX_AR46, XT_REG_IDX_AR47,
- XT_REG_IDX_AR48, XT_REG_IDX_AR49, XT_REG_IDX_AR50, XT_REG_IDX_AR51,
- XT_REG_IDX_AR52, XT_REG_IDX_AR53, XT_REG_IDX_AR54, XT_REG_IDX_AR55,
- XT_REG_IDX_AR56, XT_REG_IDX_AR57, XT_REG_IDX_AR58, XT_REG_IDX_AR59,
- XT_REG_IDX_AR60, XT_REG_IDX_AR61, XT_REG_IDX_AR62, XT_REG_IDX_AR63,
- XT_REG_IDX_LBEG, XT_REG_IDX_LEND, XT_REG_IDX_LCOUNT, XT_REG_IDX_SAR,
- XT_REG_IDX_WINDOWBASE, XT_REG_IDX_WINDOWSTART, XT_REG_IDX_CONFIGID0, XT_REG_IDX_CONFIGID1,
- XT_REG_IDX_PS, XT_REG_IDX_THREADPTR, XT_REG_IDX_BR, XT_REG_IDX_SCOMPARE1,
- XT_REG_IDX_ACCLO, XT_REG_IDX_ACCHI,
- XT_REG_IDX_M0, XT_REG_IDX_M1, XT_REG_IDX_M2, XT_REG_IDX_M3,
- ESP32_REG_IDX_EXPSTATE,
- ESP32_REG_IDX_F64R_LO,
- ESP32_REG_IDX_F64R_HI,
- ESP32_REG_IDX_F64S,
- XT_REG_IDX_F0, XT_REG_IDX_F1, XT_REG_IDX_F2, XT_REG_IDX_F3,
- XT_REG_IDX_F4, XT_REG_IDX_F5, XT_REG_IDX_F6, XT_REG_IDX_F7,
- XT_REG_IDX_F8, XT_REG_IDX_F9, XT_REG_IDX_F10, XT_REG_IDX_F11,
- XT_REG_IDX_F12, XT_REG_IDX_F13, XT_REG_IDX_F14, XT_REG_IDX_F15,
- XT_REG_IDX_FCR, XT_REG_IDX_FSR, XT_REG_IDX_MMID, XT_REG_IDX_IBREAKENABLE,
- XT_REG_IDX_MEMCTL, XT_REG_IDX_ATOMCTL, XT_REG_IDX_OCD_DDR,
- XT_REG_IDX_IBREAKA0, XT_REG_IDX_IBREAKA1, XT_REG_IDX_DBREAKA0, XT_REG_IDX_DBREAKA1,
- XT_REG_IDX_DBREAKC0, XT_REG_IDX_DBREAKC1,
- XT_REG_IDX_EPC1, XT_REG_IDX_EPC2, XT_REG_IDX_EPC3, XT_REG_IDX_EPC4,
- XT_REG_IDX_EPC5, XT_REG_IDX_EPC6, XT_REG_IDX_EPC7, XT_REG_IDX_DEPC,
- XT_REG_IDX_EPS2, XT_REG_IDX_EPS3, XT_REG_IDX_EPS4, XT_REG_IDX_EPS5,
- XT_REG_IDX_EPS6, XT_REG_IDX_EPS7,
- XT_REG_IDX_EXCSAVE1, XT_REG_IDX_EXCSAVE2, XT_REG_IDX_EXCSAVE3, XT_REG_IDX_EXCSAVE4,
- XT_REG_IDX_EXCSAVE5, XT_REG_IDX_EXCSAVE6, XT_REG_IDX_EXCSAVE7, XT_REG_IDX_CPENABLE,
- XT_REG_IDX_INTERRUPT, XT_REG_IDX_INTSET, XT_REG_IDX_INTCLEAR, XT_REG_IDX_INTENABLE,
- XT_REG_IDX_VECBASE, XT_REG_IDX_EXCCAUSE, XT_REG_IDX_DEBUGCAUSE, XT_REG_IDX_CCOUNT,
- XT_REG_IDX_PRID, XT_REG_IDX_ICOUNT, XT_REG_IDX_ICOUNTLEVEL, XT_REG_IDX_EXCVADDR,
- XT_REG_IDX_CCOMPARE0, XT_REG_IDX_CCOMPARE1, XT_REG_IDX_CCOMPARE2,
- XT_REG_IDX_MISC0, XT_REG_IDX_MISC1, XT_REG_IDX_MISC2, XT_REG_IDX_MISC3,
- XT_REG_IDX_A0, XT_REG_IDX_A1, XT_REG_IDX_A2, XT_REG_IDX_A3,
- XT_REG_IDX_A4, XT_REG_IDX_A5, XT_REG_IDX_A6, XT_REG_IDX_A7,
- XT_REG_IDX_A8, XT_REG_IDX_A9, XT_REG_IDX_A10, XT_REG_IDX_A11,
- XT_REG_IDX_A12, XT_REG_IDX_A13, XT_REG_IDX_A14, XT_REG_IDX_A15,
- XT_REG_IDX_PWRCTL, XT_REG_IDX_PWRSTAT, XT_REG_IDX_ERISTAT,
- XT_REG_IDX_CS_ITCTRL, XT_REG_IDX_CS_CLAIMSET, XT_REG_IDX_CS_CLAIMCLR,
- XT_REG_IDX_CS_LOCKACCESS, XT_REG_IDX_CS_LOCKSTATUS, XT_REG_IDX_CS_AUTHSTATUS,
- XT_REG_IDX_FAULT_INFO,
- XT_REG_IDX_TRAX_ID, XT_REG_IDX_TRAX_CTRL, XT_REG_IDX_TRAX_STAT,
- XT_REG_IDX_TRAX_DATA, XT_REG_IDX_TRAX_ADDR, XT_REG_IDX_TRAX_PCTRIGGER,
- XT_REG_IDX_TRAX_PCMATCH, XT_REG_IDX_TRAX_DELAY, XT_REG_IDX_TRAX_MEMSTART,
- XT_REG_IDX_TRAX_MEMEND,
- XT_REG_IDX_PMG, XT_REG_IDX_PMPC, XT_REG_IDX_PM0, XT_REG_IDX_PM1,
- XT_REG_IDX_PMCTRL0, XT_REG_IDX_PMCTRL1, XT_REG_IDX_PMSTAT0, XT_REG_IDX_PMSTAT1,
- XT_REG_IDX_OCD_ID, XT_REG_IDX_OCD_DCRCLR, XT_REG_IDX_OCD_DCRSET, XT_REG_IDX_OCD_DSR,
-};
-
-static const struct xtensa_user_reg_desc esp32_user_regs[ESP32_NUM_REGS - XT_NUM_REGS] = {
- { "expstate", 0xE6, 0, 32, &xtensa_user_reg_u32_type },
- { "f64r_lo", 0xEA, 0, 32, &xtensa_user_reg_u32_type },
- { "f64r_hi", 0xEB, 0, 32, &xtensa_user_reg_u32_type },
- { "f64s", 0xEC, 0, 32, &xtensa_user_reg_u32_type },
-};
-
-static const struct xtensa_config esp32_xtensa_cfg = {
- .density = true,
- .aregs_num = XT_AREGS_NUM_MAX,
- .windowed = true,
- .coproc = true,
- .fp_coproc = true,
- .loop = true,
- .miscregs_num = 4,
- .threadptr = true,
- .boolean = true,
- .reloc_vec = true,
- .proc_id = true,
- .cond_store = true,
- .mac16 = true,
- .user_regs_num = ARRAY_SIZE(esp32_user_regs),
- .user_regs = esp32_user_regs,
- .fetch_user_regs = xtensa_fetch_user_regs_u32,
- .queue_write_dirty_user_regs = xtensa_queue_write_dirty_user_regs_u32,
- .gdb_general_regs_num = ESP32_NUM_REGS_G_COMMAND,
- .gdb_regs_mapping = esp32_gdb_regs_mapping,
- .irom = {
- .count = 2,
- .regions = {
- {
- .base = ESP32_IROM_LOW,
- .size = ESP32_IROM_HIGH - ESP32_IROM_LOW,
- .access = XT_MEM_ACCESS_READ,
- },
- {
- .base = ESP32_IROM_MASK_LOW,
- .size = ESP32_IROM_MASK_HIGH - ESP32_IROM_MASK_LOW,
- .access = XT_MEM_ACCESS_READ,
- },
- }
- },
- .iram = {
- .count = 2,
- .regions = {
- {
- .base = ESP32_IRAM_LOW,
- .size = ESP32_IRAM_HIGH - ESP32_IRAM_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- {
- .base = ESP32_RTC_IRAM_LOW,
- .size = ESP32_RTC_IRAM_HIGH - ESP32_RTC_IRAM_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- }
- },
- .drom = {
- .count = 1,
- .regions = {
- {
- .base = ESP32_DROM_LOW,
- .size = ESP32_DROM_HIGH - ESP32_DROM_LOW,
- .access = XT_MEM_ACCESS_READ,
- },
- }
- },
- .dram = {
- .count = 6,
- .regions = {
- {
- .base = ESP32_DRAM_LOW,
- .size = ESP32_DRAM_HIGH - ESP32_DRAM_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- {
- .base = ESP32_RTC_DRAM_LOW,
- .size = ESP32_RTC_DRAM_HIGH - ESP32_RTC_DRAM_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- {
- .base = ESP32_RTC_DATA_LOW,
- .size = ESP32_RTC_DATA_HIGH - ESP32_RTC_DATA_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- {
- .base = ESP32_EXTRAM_DATA_LOW,
- .size = ESP32_EXTRAM_DATA_HIGH - ESP32_EXTRAM_DATA_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- {
- .base = ESP32_DR_REG_LOW,
- .size = ESP32_DR_REG_HIGH - ESP32_DR_REG_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- {
- .base = ESP32_SYS_RAM_LOW,
- .size = ESP32_SYS_RAM_HIGH - ESP32_SYS_RAM_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- }
- },
- .exc = {
- .enabled = true,
- },
- .irq = {
- .enabled = true,
- .irq_num = 32,
- },
- .high_irq = {
- .enabled = true,
- .excm_level = 3,
- .nmi_num = 1,
- },
- .tim_irq = {
- .enabled = true,
- .comp_num = 3,
- },
- .debug = {
- .enabled = true,
- .irq_level = 6,
- .ibreaks_num = 2,
- .dbreaks_num = 2,
- .icount_sz = 32,
- },
- .trace = {
- .enabled = true,
- .mem_sz = ESP32_TRACEMEM_BLOCK_SZ,
- .reversed_mem_access = true,
- },
-};
-
/* 0 - don't care, 1 - TMS low, 2 - TMS high */
enum esp32_flash_bootstrap {
FBS_DONTCARE = 0,
@@ -401,7 +202,8 @@ static int esp32_soc_reset(struct target *target)
alive_sleep(10);
xtensa_poll(target);
if (timeval_ms() >= timeout) {
- LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state=%d", target->state);
+ LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state=%d",
+ target->state);
get_timeout = true;
break;
}
@@ -481,7 +283,6 @@ static int esp32_virt2phys(struct target *target,
return ERROR_FAIL;
}
-
/* The TDI pin is also used as a flash Vcc bootstrap pin. If we reset the CPU externally, the last state of the TDI pin
* can allow the power to an 1.8V flash chip to be raised to 3.3V, or the other way around. Users can use the
* esp32 flashbootstrap command to set a level, and this routine will make sure the tdi line will return to
@@ -544,7 +345,7 @@ static int esp32_target_create(struct target *target, Jim_Interp *interp)
return ERROR_FAIL;
}
- int ret = esp_xtensa_smp_init_arch_info(target, &esp32->esp_xtensa_smp, &esp32_xtensa_cfg,
+ int ret = esp_xtensa_smp_init_arch_info(target, &esp32->esp_xtensa_smp,
&esp32_dm_cfg, &esp32_chip_ops);
if (ret != ERROR_OK) {
LOG_ERROR("Failed to init arch info!");
diff --git a/src/target/espressif/esp32.h b/src/target/espressif/esp32.h
deleted file mode 100644
index f07c08d41..000000000
--- a/src/target/espressif/esp32.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-/***************************************************************************
- * ESP32 target for OpenOCD *
- * Copyright (C) 2017 Espressif Systems Ltd. *
- ***************************************************************************/
-
-#ifndef OPENOCD_TARGET_ESP32_H
-#define OPENOCD_TARGET_ESP32_H
-
-#include <target/xtensa/xtensa_regs.h>
-
-#define ESP32_DROM_LOW 0x3F400000
-#define ESP32_DROM_HIGH 0x3F800000
-#define ESP32_IROM_LOW 0x400D0000
-#define ESP32_IROM_HIGH 0x40400000
-
-/* Number of registers returned directly by the G command
- * Corresponds to the amount of regs listed in regformats/reg-xtensa.dat in the gdb source */
-#define ESP32_NUM_REGS_G_COMMAND 105
-
-enum esp32_reg_id {
- /* chip specific registers that extend ISA go after ISA-defined ones */
- ESP32_REG_IDX_EXPSTATE = XT_USR_REG_START,
- ESP32_REG_IDX_F64R_LO,
- ESP32_REG_IDX_F64R_HI,
- ESP32_REG_IDX_F64S,
- ESP32_NUM_REGS,
-};
-
-#endif /* OPENOCD_TARGET_ESP32_H */
diff --git a/src/target/espressif/esp32s2.c b/src/target/espressif/esp32s2.c
index bbf7ff5af..0bcd20f2d 100644
--- a/src/target/espressif/esp32s2.c
+++ b/src/target/espressif/esp32s2.c
@@ -14,7 +14,6 @@
#include <target/target.h>
#include <target/target_type.h>
#include "esp_xtensa.h"
-#include "esp32s2.h"
/* Overall memory map
* TODO: read memory configuration from target registers */
@@ -89,190 +88,6 @@
#define ESP32_S2_DR_REG_UART_BASE 0x3f400000
#define ESP32_S2_REG_UART_BASE(i) (ESP32_S2_DR_REG_UART_BASE + (i) * 0x10000)
#define ESP32_S2_UART_DATE_REG(i) (ESP32_S2_REG_UART_BASE(i) + 0x74)
-
-/* this should map local reg IDs to GDB reg mapping as defined in xtensa-config.c 'rmap' in
- * xtensa-overlay */
-static const unsigned int esp32s2_gdb_regs_mapping[ESP32_S2_NUM_REGS] = {
- XT_REG_IDX_PC,
- XT_REG_IDX_AR0, XT_REG_IDX_AR1, XT_REG_IDX_AR2, XT_REG_IDX_AR3,
- XT_REG_IDX_AR4, XT_REG_IDX_AR5, XT_REG_IDX_AR6, XT_REG_IDX_AR7,
- XT_REG_IDX_AR8, XT_REG_IDX_AR9, XT_REG_IDX_AR10, XT_REG_IDX_AR11,
- XT_REG_IDX_AR12, XT_REG_IDX_AR13, XT_REG_IDX_AR14, XT_REG_IDX_AR15,
- XT_REG_IDX_AR16, XT_REG_IDX_AR17, XT_REG_IDX_AR18, XT_REG_IDX_AR19,
- XT_REG_IDX_AR20, XT_REG_IDX_AR21, XT_REG_IDX_AR22, XT_REG_IDX_AR23,
- XT_REG_IDX_AR24, XT_REG_IDX_AR25, XT_REG_IDX_AR26, XT_REG_IDX_AR27,
- XT_REG_IDX_AR28, XT_REG_IDX_AR29, XT_REG_IDX_AR30, XT_REG_IDX_AR31,
- XT_REG_IDX_AR32, XT_REG_IDX_AR33, XT_REG_IDX_AR34, XT_REG_IDX_AR35,
- XT_REG_IDX_AR36, XT_REG_IDX_AR37, XT_REG_IDX_AR38, XT_REG_IDX_AR39,
- XT_REG_IDX_AR40, XT_REG_IDX_AR41, XT_REG_IDX_AR42, XT_REG_IDX_AR43,
- XT_REG_IDX_AR44, XT_REG_IDX_AR45, XT_REG_IDX_AR46, XT_REG_IDX_AR47,
- XT_REG_IDX_AR48, XT_REG_IDX_AR49, XT_REG_IDX_AR50, XT_REG_IDX_AR51,
- XT_REG_IDX_AR52, XT_REG_IDX_AR53, XT_REG_IDX_AR54, XT_REG_IDX_AR55,
- XT_REG_IDX_AR56, XT_REG_IDX_AR57, XT_REG_IDX_AR58, XT_REG_IDX_AR59,
- XT_REG_IDX_AR60, XT_REG_IDX_AR61, XT_REG_IDX_AR62, XT_REG_IDX_AR63,
- XT_REG_IDX_SAR,
- XT_REG_IDX_WINDOWBASE, XT_REG_IDX_WINDOWSTART, XT_REG_IDX_CONFIGID0, XT_REG_IDX_CONFIGID1,
- XT_REG_IDX_PS, XT_REG_IDX_THREADPTR,
- ESP32_S2_REG_IDX_GPIOOUT,
- XT_REG_IDX_MMID, XT_REG_IDX_IBREAKENABLE, XT_REG_IDX_OCD_DDR,
- XT_REG_IDX_IBREAKA0, XT_REG_IDX_IBREAKA1, XT_REG_IDX_DBREAKA0, XT_REG_IDX_DBREAKA1,
- XT_REG_IDX_DBREAKC0, XT_REG_IDX_DBREAKC1,
- XT_REG_IDX_EPC1, XT_REG_IDX_EPC2, XT_REG_IDX_EPC3, XT_REG_IDX_EPC4,
- XT_REG_IDX_EPC5, XT_REG_IDX_EPC6, XT_REG_IDX_EPC7, XT_REG_IDX_DEPC,
- XT_REG_IDX_EPS2, XT_REG_IDX_EPS3, XT_REG_IDX_EPS4, XT_REG_IDX_EPS5,
- XT_REG_IDX_EPS6, XT_REG_IDX_EPS7,
- XT_REG_IDX_EXCSAVE1, XT_REG_IDX_EXCSAVE2, XT_REG_IDX_EXCSAVE3, XT_REG_IDX_EXCSAVE4,
- XT_REG_IDX_EXCSAVE5, XT_REG_IDX_EXCSAVE6, XT_REG_IDX_EXCSAVE7, XT_REG_IDX_CPENABLE,
- XT_REG_IDX_INTERRUPT, XT_REG_IDX_INTSET, XT_REG_IDX_INTCLEAR, XT_REG_IDX_INTENABLE,
- XT_REG_IDX_VECBASE, XT_REG_IDX_EXCCAUSE, XT_REG_IDX_DEBUGCAUSE, XT_REG_IDX_CCOUNT,
- XT_REG_IDX_PRID, XT_REG_IDX_ICOUNT, XT_REG_IDX_ICOUNTLEVEL, XT_REG_IDX_EXCVADDR,
- XT_REG_IDX_CCOMPARE0, XT_REG_IDX_CCOMPARE1, XT_REG_IDX_CCOMPARE2,
- XT_REG_IDX_MISC0, XT_REG_IDX_MISC1, XT_REG_IDX_MISC2, XT_REG_IDX_MISC3,
- XT_REG_IDX_A0, XT_REG_IDX_A1, XT_REG_IDX_A2, XT_REG_IDX_A3,
- XT_REG_IDX_A4, XT_REG_IDX_A5, XT_REG_IDX_A6, XT_REG_IDX_A7,
- XT_REG_IDX_A8, XT_REG_IDX_A9, XT_REG_IDX_A10, XT_REG_IDX_A11,
- XT_REG_IDX_A12, XT_REG_IDX_A13, XT_REG_IDX_A14, XT_REG_IDX_A15,
- XT_REG_IDX_PWRCTL, XT_REG_IDX_PWRSTAT, XT_REG_IDX_ERISTAT,
- XT_REG_IDX_CS_ITCTRL, XT_REG_IDX_CS_CLAIMSET, XT_REG_IDX_CS_CLAIMCLR,
- XT_REG_IDX_CS_LOCKACCESS, XT_REG_IDX_CS_LOCKSTATUS, XT_REG_IDX_CS_AUTHSTATUS,
- XT_REG_IDX_FAULT_INFO,
- XT_REG_IDX_TRAX_ID, XT_REG_IDX_TRAX_CTRL, XT_REG_IDX_TRAX_STAT,
- XT_REG_IDX_TRAX_DATA, XT_REG_IDX_TRAX_ADDR, XT_REG_IDX_TRAX_PCTRIGGER,
- XT_REG_IDX_TRAX_PCMATCH, XT_REG_IDX_TRAX_DELAY, XT_REG_IDX_TRAX_MEMSTART,
- XT_REG_IDX_TRAX_MEMEND,
- XT_REG_IDX_PMG, XT_REG_IDX_PMPC, XT_REG_IDX_PM0, XT_REG_IDX_PM1,
- XT_REG_IDX_PMCTRL0, XT_REG_IDX_PMCTRL1, XT_REG_IDX_PMSTAT0, XT_REG_IDX_PMSTAT1,
- XT_REG_IDX_OCD_ID, XT_REG_IDX_OCD_DCRCLR, XT_REG_IDX_OCD_DCRSET, XT_REG_IDX_OCD_DSR,
-};
-
-static const struct xtensa_user_reg_desc esp32s2_user_regs[ESP32_S2_NUM_REGS - XT_NUM_REGS] = {
- { "gpio_out", 0x00, 0, 32, &xtensa_user_reg_u32_type },
-};
-
-static const struct xtensa_config esp32s2_xtensa_cfg = {
- .density = true,
- .aregs_num = XT_AREGS_NUM_MAX,
- .windowed = true,
- .coproc = true,
- .miscregs_num = 4,
- .reloc_vec = true,
- .proc_id = true,
- .threadptr = true,
- .user_regs_num = ARRAY_SIZE(esp32s2_user_regs),
- .user_regs = esp32s2_user_regs,
- .fetch_user_regs = xtensa_fetch_user_regs_u32,
- .queue_write_dirty_user_regs = xtensa_queue_write_dirty_user_regs_u32,
- .gdb_general_regs_num = ESP32_S2_NUM_REGS_G_COMMAND,
- .gdb_regs_mapping = esp32s2_gdb_regs_mapping,
- .irom = {
- .count = 2,
- .regions = {
- {
- .base = ESP32_S2_IROM_LOW,
- .size = ESP32_S2_IROM_HIGH - ESP32_S2_IROM_LOW,
- .access = XT_MEM_ACCESS_READ,
- },
- {
- .base = ESP32_S2_IROM_MASK_LOW,
- .size = ESP32_S2_IROM_MASK_HIGH - ESP32_S2_IROM_MASK_LOW,
- .access = XT_MEM_ACCESS_READ,
- },
- }
- },
- .iram = {
- .count = 2,
- .regions = {
- {
- .base = ESP32_S2_IRAM_LOW,
- .size = ESP32_S2_IRAM_HIGH - ESP32_S2_IRAM_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- {
- .base = ESP32_S2_RTC_IRAM_LOW,
- .size = ESP32_S2_RTC_IRAM_HIGH - ESP32_S2_RTC_IRAM_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- }
- },
- .drom = {
- .count = 2,
- .regions = {
- {
- .base = ESP32_S2_DROM0_LOW,
- .size = ESP32_S2_DROM0_HIGH - ESP32_S2_DROM0_LOW,
- .access = XT_MEM_ACCESS_READ,
- },
- {
- .base = ESP32_S2_DROM1_LOW,
- .size = ESP32_S2_DROM1_HIGH - ESP32_S2_DROM1_LOW,
- .access = XT_MEM_ACCESS_READ,
- },
- }
- },
- .dram = {
- .count = 6,
- .regions = {
- {
- .base = ESP32_S2_DRAM_LOW,
- .size = ESP32_S2_DRAM_HIGH - ESP32_S2_DRAM_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- {
- .base = ESP32_S2_RTC_DRAM_LOW,
- .size = ESP32_S2_RTC_DRAM_HIGH - ESP32_S2_RTC_DRAM_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- {
- .base = ESP32_S2_RTC_DATA_LOW,
- .size = ESP32_S2_RTC_DATA_HIGH - ESP32_S2_RTC_DATA_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- {
- .base = ESP32_S2_EXTRAM_DATA_LOW,
- .size = ESP32_S2_EXTRAM_DATA_HIGH - ESP32_S2_EXTRAM_DATA_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- {
- .base = ESP32_S2_DR_REG_LOW,
- .size = ESP32_S2_DR_REG_HIGH - ESP32_S2_DR_REG_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- {
- .base = ESP32_S2_SYS_RAM_LOW,
- .size = ESP32_S2_SYS_RAM_HIGH - ESP32_S2_SYS_RAM_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- }
- },
- .exc = {
- .enabled = true,
- },
- .irq = {
- .enabled = true,
- .irq_num = 32,
- },
- .high_irq = {
- .enabled = true,
- .excm_level = 3,
- .nmi_num = 1,
- },
- .tim_irq = {
- .enabled = true,
- .comp_num = 3,
- },
- .debug = {
- .enabled = true,
- .irq_level = 6,
- .ibreaks_num = 2,
- .dbreaks_num = 2,
- .icount_sz = 32,
- },
- .trace = {
- .enabled = true,
- .mem_sz = ESP32_S2_TRACEMEM_BLOCK_SZ,
- },
-};
-
struct esp32s2_common {
struct esp_xtensa_common esp_xtensa;
};
@@ -313,7 +128,7 @@ int esp32s2_soft_reset_halt(struct target *target)
int res = esp32s2_soc_reset(target);
if (res != ERROR_OK)
return res;
- return xtensa_assert_reset(target);
+ return xtensa_soft_reset_halt(target);
}
static int esp32s2_set_peri_reg_mask(struct target *target,
@@ -476,7 +291,8 @@ static int esp32s2_soc_reset(struct target *target)
alive_sleep(10);
xtensa_poll(target);
if (timeval_ms() >= timeout) {
- LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state=%d", target->state);
+ LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state=%d",
+ target->state);
return ERROR_TARGET_TIMEOUT;
}
}
@@ -638,7 +454,7 @@ static int esp32s2_target_create(struct target *target, Jim_Interp *interp)
return ERROR_FAIL;
}
- int ret = esp_xtensa_init_arch_info(target, &esp32->esp_xtensa, &esp32s2_xtensa_cfg, &esp32s2_dm_cfg);
+ int ret = esp_xtensa_init_arch_info(target, &esp32->esp_xtensa, &esp32s2_dm_cfg);
if (ret != ERROR_OK) {
LOG_ERROR("Failed to init arch info!");
free(esp32);
@@ -653,10 +469,6 @@ static int esp32s2_target_create(struct target *target, Jim_Interp *interp)
static const struct command_registration esp32s2_command_handlers[] = {
{
- .name = "xtensa",
- .mode = COMMAND_ANY,
- .help = "Xtensa commands group",
- .usage = "",
.chain = xtensa_command_handlers,
},
COMMAND_REGISTRATION_DONE
diff --git a/src/target/espressif/esp32s2.h b/src/target/espressif/esp32s2.h
deleted file mode 100644
index 26fc7a198..000000000
--- a/src/target/espressif/esp32s2.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-/***************************************************************************
- * ESP32-S2 target for OpenOCD *
- * Copyright (C) 2019 Espressif Systems Ltd. *
- ***************************************************************************/
-
-#ifndef OPENOCD_TARGET_ESP32S2_H
-#define OPENOCD_TARGET_ESP32S2_H
-
-#include <target/xtensa/xtensa_regs.h>
-
-#define ESP32_S2_DROM_LOW 0x3f000000
-#define ESP32_S2_DROM_HIGH 0x3ff80000
-#define ESP32_S2_IROM_LOW 0x40080000
-#define ESP32_S2_IROM_HIGH 0x40800000
-
-/* Number of registers returned directly by the G command
- * Corresponds to the amount of regs listed in regformats/reg-xtensa.dat in the gdb source */
-#define ESP32_S2_NUM_REGS_G_COMMAND 72
-
-enum esp32s2_reg_id {
- /* chip specific registers that extend ISA go after ISA-defined ones */
- ESP32_S2_REG_IDX_GPIOOUT = XT_USR_REG_START,
- ESP32_S2_NUM_REGS,
-};
-
-#endif /* OPENOCD_TARGET_ESP32S2_H */
diff --git a/src/target/espressif/esp32s3.c b/src/target/espressif/esp32s3.c
index b5487407f..b87005901 100644
--- a/src/target/espressif/esp32s3.c
+++ b/src/target/espressif/esp32s3.c
@@ -14,7 +14,6 @@
#include <target/target_type.h>
#include <target/smp.h>
#include "assert.h"
-#include "esp32s3.h"
#include "esp_xtensa_smp.h"
/*
@@ -75,246 +74,10 @@ implementation.
#define ESP32_S3_RTC_CNTL_SW_CPU_STALL_REG (ESP32_S3_RTCCNTL_BASE + 0xBC)
#define ESP32_S3_RTC_CNTL_SW_CPU_STALL_DEF 0x0
-/* this should map local reg IDs to GDB reg mapping as defined in xtensa-config.c 'rmap' in
- *xtensa-overlay */
-static const unsigned int esp32s3_gdb_regs_mapping[ESP32_S3_NUM_REGS] = {
- XT_REG_IDX_PC,
- XT_REG_IDX_AR0, XT_REG_IDX_AR1, XT_REG_IDX_AR2, XT_REG_IDX_AR3,
- XT_REG_IDX_AR4, XT_REG_IDX_AR5, XT_REG_IDX_AR6, XT_REG_IDX_AR7,
- XT_REG_IDX_AR8, XT_REG_IDX_AR9, XT_REG_IDX_AR10, XT_REG_IDX_AR11,
- XT_REG_IDX_AR12, XT_REG_IDX_AR13, XT_REG_IDX_AR14, XT_REG_IDX_AR15,
- XT_REG_IDX_AR16, XT_REG_IDX_AR17, XT_REG_IDX_AR18, XT_REG_IDX_AR19,
- XT_REG_IDX_AR20, XT_REG_IDX_AR21, XT_REG_IDX_AR22, XT_REG_IDX_AR23,
- XT_REG_IDX_AR24, XT_REG_IDX_AR25, XT_REG_IDX_AR26, XT_REG_IDX_AR27,
- XT_REG_IDX_AR28, XT_REG_IDX_AR29, XT_REG_IDX_AR30, XT_REG_IDX_AR31,
- XT_REG_IDX_AR32, XT_REG_IDX_AR33, XT_REG_IDX_AR34, XT_REG_IDX_AR35,
- XT_REG_IDX_AR36, XT_REG_IDX_AR37, XT_REG_IDX_AR38, XT_REG_IDX_AR39,
- XT_REG_IDX_AR40, XT_REG_IDX_AR41, XT_REG_IDX_AR42, XT_REG_IDX_AR43,
- XT_REG_IDX_AR44, XT_REG_IDX_AR45, XT_REG_IDX_AR46, XT_REG_IDX_AR47,
- XT_REG_IDX_AR48, XT_REG_IDX_AR49, XT_REG_IDX_AR50, XT_REG_IDX_AR51,
- XT_REG_IDX_AR52, XT_REG_IDX_AR53, XT_REG_IDX_AR54, XT_REG_IDX_AR55,
- XT_REG_IDX_AR56, XT_REG_IDX_AR57, XT_REG_IDX_AR58, XT_REG_IDX_AR59,
- XT_REG_IDX_AR60, XT_REG_IDX_AR61, XT_REG_IDX_AR62, XT_REG_IDX_AR63,
- XT_REG_IDX_LBEG, XT_REG_IDX_LEND, XT_REG_IDX_LCOUNT, XT_REG_IDX_SAR,
- XT_REG_IDX_WINDOWBASE, XT_REG_IDX_WINDOWSTART, XT_REG_IDX_CONFIGID0, XT_REG_IDX_CONFIGID1,
- XT_REG_IDX_PS, XT_REG_IDX_THREADPTR, XT_REG_IDX_BR, XT_REG_IDX_SCOMPARE1,
- XT_REG_IDX_ACCLO, XT_REG_IDX_ACCHI,
- XT_REG_IDX_M0, XT_REG_IDX_M1, XT_REG_IDX_M2, XT_REG_IDX_M3,
- ESP32_S3_REG_IDX_GPIOOUT,
- XT_REG_IDX_F0, XT_REG_IDX_F1, XT_REG_IDX_F2, XT_REG_IDX_F3,
- XT_REG_IDX_F4, XT_REG_IDX_F5, XT_REG_IDX_F6, XT_REG_IDX_F7,
- XT_REG_IDX_F8, XT_REG_IDX_F9, XT_REG_IDX_F10, XT_REG_IDX_F11,
- XT_REG_IDX_F12, XT_REG_IDX_F13, XT_REG_IDX_F14, XT_REG_IDX_F15,
- XT_REG_IDX_FCR, XT_REG_IDX_FSR,
- ESP32_S3_REG_IDX_ACCX_0, ESP32_S3_REG_IDX_ACCX_1,
- ESP32_S3_REG_IDX_QACC_H_0, ESP32_S3_REG_IDX_QACC_H_1, ESP32_S3_REG_IDX_QACC_H_2,
- ESP32_S3_REG_IDX_QACC_H_3, ESP32_S3_REG_IDX_QACC_H_4,
- ESP32_S3_REG_IDX_QACC_L_0, ESP32_S3_REG_IDX_QACC_L_1, ESP32_S3_REG_IDX_QACC_L_2,
- ESP32_S3_REG_IDX_QACC_L_3, ESP32_S3_REG_IDX_QACC_L_4,
- ESP32_S3_REG_IDX_SAR_BYTE, ESP32_S3_REG_IDX_FFT_BIT_WIDTH,
- ESP32_S3_REG_IDX_UA_STATE_0, ESP32_S3_REG_IDX_UA_STATE_1, ESP32_S3_REG_IDX_UA_STATE_2,
- ESP32_S3_REG_IDX_UA_STATE_3,
- ESP32_S3_REG_IDX_Q0, ESP32_S3_REG_IDX_Q1, ESP32_S3_REG_IDX_Q2, ESP32_S3_REG_IDX_Q3,
- ESP32_S3_REG_IDX_Q4, ESP32_S3_REG_IDX_Q5, ESP32_S3_REG_IDX_Q6, ESP32_S3_REG_IDX_Q7,
-
- XT_REG_IDX_MMID, XT_REG_IDX_IBREAKENABLE,
- XT_REG_IDX_MEMCTL, XT_REG_IDX_ATOMCTL, XT_REG_IDX_OCD_DDR,
- XT_REG_IDX_IBREAKA0, XT_REG_IDX_IBREAKA1, XT_REG_IDX_DBREAKA0, XT_REG_IDX_DBREAKA1,
- XT_REG_IDX_DBREAKC0, XT_REG_IDX_DBREAKC1,
- XT_REG_IDX_EPC1, XT_REG_IDX_EPC2, XT_REG_IDX_EPC3, XT_REG_IDX_EPC4,
- XT_REG_IDX_EPC5, XT_REG_IDX_EPC6, XT_REG_IDX_EPC7, XT_REG_IDX_DEPC,
- XT_REG_IDX_EPS2, XT_REG_IDX_EPS3, XT_REG_IDX_EPS4, XT_REG_IDX_EPS5,
- XT_REG_IDX_EPS6, XT_REG_IDX_EPS7,
- XT_REG_IDX_EXCSAVE1, XT_REG_IDX_EXCSAVE2, XT_REG_IDX_EXCSAVE3, XT_REG_IDX_EXCSAVE4,
- XT_REG_IDX_EXCSAVE5, XT_REG_IDX_EXCSAVE6, XT_REG_IDX_EXCSAVE7, XT_REG_IDX_CPENABLE,
- XT_REG_IDX_INTERRUPT, XT_REG_IDX_INTSET, XT_REG_IDX_INTCLEAR, XT_REG_IDX_INTENABLE,
- XT_REG_IDX_VECBASE, XT_REG_IDX_EXCCAUSE, XT_REG_IDX_DEBUGCAUSE, XT_REG_IDX_CCOUNT,
- XT_REG_IDX_PRID, XT_REG_IDX_ICOUNT, XT_REG_IDX_ICOUNTLEVEL, XT_REG_IDX_EXCVADDR,
- XT_REG_IDX_CCOMPARE0, XT_REG_IDX_CCOMPARE1, XT_REG_IDX_CCOMPARE2,
- XT_REG_IDX_MISC0, XT_REG_IDX_MISC1, XT_REG_IDX_MISC2, XT_REG_IDX_MISC3,
-
- XT_REG_IDX_PWRCTL, XT_REG_IDX_PWRSTAT, XT_REG_IDX_ERISTAT,
- XT_REG_IDX_CS_ITCTRL, XT_REG_IDX_CS_CLAIMSET, XT_REG_IDX_CS_CLAIMCLR,
- XT_REG_IDX_CS_LOCKACCESS, XT_REG_IDX_CS_LOCKSTATUS, XT_REG_IDX_CS_AUTHSTATUS,
- XT_REG_IDX_FAULT_INFO,
- XT_REG_IDX_TRAX_ID, XT_REG_IDX_TRAX_CTRL, XT_REG_IDX_TRAX_STAT,
- XT_REG_IDX_TRAX_DATA, XT_REG_IDX_TRAX_ADDR, XT_REG_IDX_TRAX_PCTRIGGER,
- XT_REG_IDX_TRAX_PCMATCH, XT_REG_IDX_TRAX_DELAY, XT_REG_IDX_TRAX_MEMSTART,
- XT_REG_IDX_TRAX_MEMEND,
- XT_REG_IDX_PMG, XT_REG_IDX_PMPC, XT_REG_IDX_PM0, XT_REG_IDX_PM1,
- XT_REG_IDX_PMCTRL0, XT_REG_IDX_PMCTRL1, XT_REG_IDX_PMSTAT0, XT_REG_IDX_PMSTAT1,
- XT_REG_IDX_OCD_ID, XT_REG_IDX_OCD_DCRCLR, XT_REG_IDX_OCD_DCRSET, XT_REG_IDX_OCD_DSR,
- XT_REG_IDX_A0, XT_REG_IDX_A1, XT_REG_IDX_A2, XT_REG_IDX_A3,
- XT_REG_IDX_A4, XT_REG_IDX_A5, XT_REG_IDX_A6, XT_REG_IDX_A7,
- XT_REG_IDX_A8, XT_REG_IDX_A9, XT_REG_IDX_A10, XT_REG_IDX_A11,
- XT_REG_IDX_A12, XT_REG_IDX_A13, XT_REG_IDX_A14, XT_REG_IDX_A15,
-};
-
-/* actually this table contains user + TIE registers
- * TODO: for TIE registers we need to specify custom access functions instead of `xtensa_user_reg_xxx_type`*/
-static const struct xtensa_user_reg_desc esp32s3_user_regs[ESP32_S3_NUM_REGS - XT_NUM_REGS] = {
- { "gpio_out", 0x00, 0, 32, &xtensa_user_reg_u32_type },
- { "accx_0", 0x01, 0, 32, &xtensa_user_reg_u32_type },
- { "accx_1", 0x02, 0, 32, &xtensa_user_reg_u32_type },
- { "qacc_h_0", 0x03, 0, 32, &xtensa_user_reg_u32_type },
- { "qacc_h_1", 0x04, 0, 32, &xtensa_user_reg_u32_type },
- { "qacc_h_2", 0x05, 0, 32, &xtensa_user_reg_u32_type },
- { "qacc_h_3", 0x06, 0, 32, &xtensa_user_reg_u32_type },
- { "qacc_h_4", 0x07, 0, 32, &xtensa_user_reg_u32_type },
- { "qacc_l_0", 0x08, 0, 32, &xtensa_user_reg_u32_type },
- { "qacc_l_1", 0x09, 0, 32, &xtensa_user_reg_u32_type },
- { "qacc_l_2", 0x0A, 0, 32, &xtensa_user_reg_u32_type },
- { "qacc_l_3", 0x0B, 0, 32, &xtensa_user_reg_u32_type },
- { "qacc_l_4", 0x0C, 0, 32, &xtensa_user_reg_u32_type },
- { "sar_byte", 0x0D, 0, 32, &xtensa_user_reg_u32_type },
- { "fft_bit_width", 0x0E, 0, 32, &xtensa_user_reg_u32_type },
- { "ua_state_0", 0x0F, 0, 32, &xtensa_user_reg_u32_type },
- { "ua_state_1", 0x10, 0, 32, &xtensa_user_reg_u32_type },
- { "ua_state_2", 0x11, 0, 32, &xtensa_user_reg_u32_type },
- { "ua_state_3", 0x12, 0, 32, &xtensa_user_reg_u32_type },
- { "q0", 0x13, 0, 128, &xtensa_user_reg_u128_type },
- { "q1", 0x14, 0, 128, &xtensa_user_reg_u128_type },
- { "q2", 0x15, 0, 128, &xtensa_user_reg_u128_type },
- { "q3", 0x16, 0, 128, &xtensa_user_reg_u128_type },
- { "q4", 0x17, 0, 128, &xtensa_user_reg_u128_type },
- { "q5", 0x18, 0, 128, &xtensa_user_reg_u128_type },
- { "q6", 0x19, 0, 128, &xtensa_user_reg_u128_type },
- { "q7", 0x20, 0, 128, &xtensa_user_reg_u128_type },
-};
-
struct esp32s3_common {
struct esp_xtensa_smp_common esp_xtensa_smp;
};
-static int esp32s3_fetch_user_regs(struct target *target);
-static int esp32s3_queue_write_dirty_user_regs(struct target *target);
-
-static const struct xtensa_config esp32s3_xtensa_cfg = {
- .density = true,
- .aregs_num = XT_AREGS_NUM_MAX,
- .windowed = true,
- .coproc = true,
- .fp_coproc = true,
- .loop = true,
- .miscregs_num = 4,
- .threadptr = true,
- .boolean = true,
- .reloc_vec = true,
- .proc_id = true,
- .cond_store = true,
- .mac16 = true,
- .user_regs_num = ARRAY_SIZE(esp32s3_user_regs),
- .user_regs = esp32s3_user_regs,
- .fetch_user_regs = esp32s3_fetch_user_regs,
- .queue_write_dirty_user_regs = esp32s3_queue_write_dirty_user_regs,
- .gdb_general_regs_num = ESP32_S3_NUM_REGS_G_COMMAND,
- .gdb_regs_mapping = esp32s3_gdb_regs_mapping,
- .irom = {
- .count = 2,
- .regions = {
- {
- .base = ESP32_S3_IROM_LOW,
- .size = ESP32_S3_IROM_HIGH - ESP32_S3_IROM_LOW,
- .access = XT_MEM_ACCESS_READ,
- },
- {
- .base = ESP32_S3_IROM_MASK_LOW,
- .size = ESP32_S3_IROM_MASK_HIGH - ESP32_S3_IROM_MASK_LOW,
- .access = XT_MEM_ACCESS_READ,
- }
- }
- },
- .iram = {
- .count = 2,
- .regions = {
- {
- .base = ESP32_S3_IRAM_LOW,
- .size = ESP32_S3_IRAM_HIGH - ESP32_S3_IRAM_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- {
- .base = ESP32_S3_RTC_IRAM_LOW,
- .size = ESP32_S3_RTC_IRAM_HIGH - ESP32_S3_RTC_IRAM_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- }
- },
- .drom = {
- .count = 1,
- .regions = {
- {
- .base = ESP32_S3_DROM_LOW,
- .size = ESP32_S3_DROM_HIGH - ESP32_S3_DROM_LOW,
- .access = XT_MEM_ACCESS_READ,
- },
- }
- },
- .dram = {
- .count = 4,
- .regions = {
- {
- .base = ESP32_S3_DRAM_LOW,
- .size = ESP32_S3_DRAM_HIGH - ESP32_S3_DRAM_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- {
- .base = ESP32_S3_RTC_DRAM_LOW,
- .size = ESP32_S3_RTC_DRAM_HIGH - ESP32_S3_RTC_DRAM_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- {
- .base = ESP32_S3_RTC_DATA_LOW,
- .size = ESP32_S3_RTC_DATA_HIGH - ESP32_S3_RTC_DATA_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- {
- .base = ESP32_S3_SYS_RAM_LOW,
- .size = ESP32_S3_SYS_RAM_HIGH - ESP32_S3_SYS_RAM_LOW,
- .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
- },
- }
- },
- .exc = {
- .enabled = true,
- },
- .irq = {
- .enabled = true,
- .irq_num = 32,
- },
- .high_irq = {
- .enabled = true,
- .excm_level = 3,
- .nmi_num = 1,
- },
- .tim_irq = {
- .enabled = true,
- .comp_num = 3,
- },
- .debug = {
- .enabled = true,
- .irq_level = 6,
- .ibreaks_num = 2,
- .dbreaks_num = 2,
- .icount_sz = 32,
- },
- .trace = {
- .enabled = true,
- .mem_sz = ESP32_S3_TRACEMEM_BLOCK_SZ,
- },
-};
-
-static int esp32s3_fetch_user_regs(struct target *target)
-{
- LOG_DEBUG("%s: user regs fetching is not implemented!", target_name(target));
- return ERROR_OK;
-}
-
-static int esp32s3_queue_write_dirty_user_regs(struct target *target)
-{
- LOG_DEBUG("%s: user regs writing is not implemented!", target_name(target));
- return ERROR_OK;
-}
-
/* Reset ESP32-S3's peripherals.
* 1. OpenOCD makes sure the target is halted; if not, tries to halt it.
* If that fails, tries to reset it (via OCD) and then halt.
@@ -537,7 +300,6 @@ static int esp32s3_virt2phys(struct target *target,
return ERROR_FAIL;
}
-
static int esp32s3_target_init(struct command_context *cmd_ctx, struct target *target)
{
return esp_xtensa_target_init(cmd_ctx, target);
@@ -577,7 +339,6 @@ static int esp32s3_target_create(struct target *target, Jim_Interp *interp)
int ret = esp_xtensa_smp_init_arch_info(target,
&esp32s3->esp_xtensa_smp,
- &esp32s3_xtensa_cfg,
&esp32s3_dm_cfg,
&esp32s3_chip_ops);
if (ret != ERROR_OK) {
diff --git a/src/target/espressif/esp32s3.h b/src/target/espressif/esp32s3.h
deleted file mode 100644
index a7d57ec02..000000000
--- a/src/target/espressif/esp32s3.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-/***************************************************************************
- * ESP32-S3 target for OpenOCD *
- * Copyright (C) 2020 Espressif Systems Ltd. *
- ***************************************************************************/
-
-#ifndef OPENOCD_TARGET_ESP32S3_H
-#define OPENOCD_TARGET_ESP32S3_H
-
-#include <target/xtensa/xtensa_regs.h>
-
-#define ESP32_S3_DROM_LOW 0x3C000000
-#define ESP32_S3_DROM_HIGH 0x3D000000
-#define ESP32_S3_IROM_LOW 0x42000000
-#define ESP32_S3_IROM_HIGH 0x44000000
-
-/*Number of registers returned directly by the G command
- *Corresponds to the amount of regs listed in regformats/reg-xtensa.dat in the gdb source */
-#define ESP32_S3_NUM_REGS_G_COMMAND 128
-
-enum esp32s3_reg_id {
- /* chip specific registers that extend ISA go after ISA-defined ones */
- ESP32_S3_REG_IDX_GPIOOUT = XT_NUM_REGS,
- ESP32_S3_REG_IDX_ACCX_0,
- ESP32_S3_REG_IDX_ACCX_1,
- ESP32_S3_REG_IDX_QACC_H_0,
- ESP32_S3_REG_IDX_QACC_H_1,
- ESP32_S3_REG_IDX_QACC_H_2,
- ESP32_S3_REG_IDX_QACC_H_3,
- ESP32_S3_REG_IDX_QACC_H_4,
- ESP32_S3_REG_IDX_QACC_L_0,
- ESP32_S3_REG_IDX_QACC_L_1,
- ESP32_S3_REG_IDX_QACC_L_2,
- ESP32_S3_REG_IDX_QACC_L_3,
- ESP32_S3_REG_IDX_QACC_L_4,
- ESP32_S3_REG_IDX_SAR_BYTE,
- ESP32_S3_REG_IDX_FFT_BIT_WIDTH,
- ESP32_S3_REG_IDX_UA_STATE_0,
- ESP32_S3_REG_IDX_UA_STATE_1,
- ESP32_S3_REG_IDX_UA_STATE_2,
- ESP32_S3_REG_IDX_UA_STATE_3,
- ESP32_S3_REG_IDX_Q0,
- ESP32_S3_REG_IDX_Q1,
- ESP32_S3_REG_IDX_Q2,
- ESP32_S3_REG_IDX_Q3,
- ESP32_S3_REG_IDX_Q4,
- ESP32_S3_REG_IDX_Q5,
- ESP32_S3_REG_IDX_Q6,
- ESP32_S3_REG_IDX_Q7,
- ESP32_S3_NUM_REGS,
-};
-
-#endif /* OPENOCD_TARGET_ESP32S3_H */
diff --git a/src/target/espressif/esp_xtensa.c b/src/target/espressif/esp_xtensa.c
index ce1601289..fcd42eac3 100644
--- a/src/target/espressif/esp_xtensa.c
+++ b/src/target/espressif/esp_xtensa.c
@@ -17,10 +17,9 @@
int esp_xtensa_init_arch_info(struct target *target,
struct esp_xtensa_common *esp_xtensa,
- const struct xtensa_config *xtensa_cfg,
struct xtensa_debug_module_config *dm_cfg)
{
- return xtensa_init_arch_info(target, &esp_xtensa->xtensa, xtensa_cfg, dm_cfg);
+ return xtensa_init_arch_info(target, &esp_xtensa->xtensa, dm_cfg);
}
int esp_xtensa_target_init(struct command_context *cmd_ctx, struct target *target)
diff --git a/src/target/espressif/esp_xtensa.h b/src/target/espressif/esp_xtensa.h
index 4bbbd756c..61e87c086 100644
--- a/src/target/espressif/esp_xtensa.h
+++ b/src/target/espressif/esp_xtensa.h
@@ -23,7 +23,6 @@ static inline struct esp_xtensa_common *target_to_esp_xtensa(struct target *targ
int esp_xtensa_init_arch_info(struct target *target,
struct esp_xtensa_common *esp_xtensa,
- const struct xtensa_config *xtensa_cfg,
struct xtensa_debug_module_config *dm_cfg);
int esp_xtensa_target_init(struct command_context *cmd_ctx, struct target *target);
void esp_xtensa_target_deinit(struct target *target);
diff --git a/src/target/espressif/esp_xtensa_smp.c b/src/target/espressif/esp_xtensa_smp.c
index 606066247..b109f3c5e 100644
--- a/src/target/espressif/esp_xtensa_smp.c
+++ b/src/target/espressif/esp_xtensa_smp.c
@@ -450,11 +450,10 @@ int esp_xtensa_smp_watchpoint_remove(struct target *target, struct watchpoint *w
int esp_xtensa_smp_init_arch_info(struct target *target,
struct esp_xtensa_smp_common *esp_xtensa_smp,
- const struct xtensa_config *xtensa_cfg,
struct xtensa_debug_module_config *dm_cfg,
const struct esp_xtensa_smp_chip_ops *chip_ops)
{
- int ret = esp_xtensa_init_arch_info(target, &esp_xtensa_smp->esp_xtensa, xtensa_cfg, dm_cfg);
+ int ret = esp_xtensa_init_arch_info(target, &esp_xtensa_smp->esp_xtensa, dm_cfg);
if (ret != ERROR_OK)
return ret;
esp_xtensa_smp->chip_ops = chip_ops;
@@ -467,6 +466,139 @@ int esp_xtensa_smp_target_init(struct command_context *cmd_ctx, struct target *t
return esp_xtensa_target_init(cmd_ctx, target);
}
+COMMAND_HANDLER(esp_xtensa_smp_cmd_xtdef)
+{
+ struct target *target = get_current_target(CMD_CTX);
+ if (target->smp && CMD_ARGC > 0) {
+ struct target_list *head;
+ struct target *curr;
+ foreach_smp_target(head, target->smp_targets) {
+ curr = head->target;
+ int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtdef_do,
+ target_to_xtensa(curr));
+ if (ret != ERROR_OK)
+ return ret;
+ }
+ return ERROR_OK;
+ }
+ return CALL_COMMAND_HANDLER(xtensa_cmd_xtdef_do,
+ target_to_xtensa(target));
+}
+
+COMMAND_HANDLER(esp_xtensa_smp_cmd_xtopt)
+{
+ struct target *target = get_current_target(CMD_CTX);
+ if (target->smp && CMD_ARGC > 0) {
+ struct target_list *head;
+ struct target *curr;
+ foreach_smp_target(head, target->smp_targets) {
+ curr = head->target;
+ int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtopt_do,
+ target_to_xtensa(curr));
+ if (ret != ERROR_OK)
+ return ret;
+ }
+ return ERROR_OK;
+ }
+ return CALL_COMMAND_HANDLER(xtensa_cmd_xtopt_do,
+ target_to_xtensa(target));
+}
+
+COMMAND_HANDLER(esp_xtensa_smp_cmd_xtmem)
+{
+ struct target *target = get_current_target(CMD_CTX);
+ if (target->smp && CMD_ARGC > 0) {
+ struct target_list *head;
+ struct target *curr;
+ foreach_smp_target(head, target->smp_targets) {
+ curr = head->target;
+ int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtmem_do,
+ target_to_xtensa(curr));
+ if (ret != ERROR_OK)
+ return ret;
+ }
+ return ERROR_OK;
+ }
+ return CALL_COMMAND_HANDLER(xtensa_cmd_xtmem_do,
+ target_to_xtensa(target));
+}
+
+COMMAND_HANDLER(esp_xtensa_smp_cmd_xtmpu)
+{
+ struct target *target = get_current_target(CMD_CTX);
+ if (target->smp && CMD_ARGC > 0) {
+ struct target_list *head;
+ struct target *curr;
+ foreach_smp_target(head, target->smp_targets) {
+ curr = head->target;
+ int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtmpu_do,
+ target_to_xtensa(curr));
+ if (ret != ERROR_OK)
+ return ret;
+ }
+ return ERROR_OK;
+ }
+ return CALL_COMMAND_HANDLER(xtensa_cmd_xtmpu_do,
+ target_to_xtensa(target));
+}
+
+COMMAND_HANDLER(esp_xtensa_smp_cmd_xtmmu)
+{
+ struct target *target = get_current_target(CMD_CTX);
+ if (target->smp && CMD_ARGC > 0) {
+ struct target_list *head;
+ struct target *curr;
+ foreach_smp_target(head, target->smp_targets) {
+ curr = head->target;
+ int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtmmu_do,
+ target_to_xtensa(curr));
+ if (ret != ERROR_OK)
+ return ret;
+ }
+ return ERROR_OK;
+ }
+ return CALL_COMMAND_HANDLER(xtensa_cmd_xtmmu_do,
+ target_to_xtensa(target));
+}
+
+COMMAND_HANDLER(esp_xtensa_smp_cmd_xtreg)
+{
+ struct target *target = get_current_target(CMD_CTX);
+ if (target->smp && CMD_ARGC > 0) {
+ struct target_list *head;
+ struct target *curr;
+ foreach_smp_target(head, target->smp_targets) {
+ curr = head->target;
+ int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtreg_do,
+ target_to_xtensa(curr));
+ if (ret != ERROR_OK)
+ return ret;
+ }
+ return ERROR_OK;
+ }
+ return CALL_COMMAND_HANDLER(xtensa_cmd_xtreg_do,
+ target_to_xtensa(target));
+}
+
+COMMAND_HANDLER(esp_xtensa_smp_cmd_xtregfmt)
+{
+ struct target *target = get_current_target(CMD_CTX);
+ if (target->smp && CMD_ARGC > 0) {
+ struct target_list *head;
+ struct target *curr;
+ foreach_smp_target(head, target->smp_targets) {
+ curr = head->target;
+ int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtregfmt_do,
+ target_to_xtensa(curr));
+ if (ret != ERROR_OK)
+ return ret;
+ }
+ return ERROR_OK;
+ }
+ return CALL_COMMAND_HANDLER(xtensa_cmd_xtregfmt_do,
+ target_to_xtensa(target));
+}
+
COMMAND_HANDLER(esp_xtensa_smp_cmd_permissive_mode)
{
struct target *target = get_current_target(CMD_CTX);
@@ -632,6 +764,62 @@ COMMAND_HANDLER(esp_xtensa_smp_cmd_tracedump)
}
const struct command_registration esp_xtensa_smp_xtensa_command_handlers[] = {
+ {
+ .name = "xtdef",
+ .handler = esp_xtensa_smp_cmd_xtdef,
+ .mode = COMMAND_CONFIG,
+ .help = "Configure Xtensa core type",
+ .usage = "<type>",
+ },
+ {
+ .name = "xtopt",
+ .handler = esp_xtensa_smp_cmd_xtopt,
+ .mode = COMMAND_CONFIG,
+ .help = "Configure Xtensa core option",
+ .usage = "<name> <value>",
+ },
+ {
+ .name = "xtmem",
+ .handler = esp_xtensa_smp_cmd_xtmem,
+ .mode = COMMAND_CONFIG,
+ .help = "Configure Xtensa memory/cache option",
+ .usage = "<type> [parameters]",
+ },
+ {
+ .name = "xtmmu",
+ .handler = esp_xtensa_smp_cmd_xtmmu,
+ .mode = COMMAND_CONFIG,
+ .help = "Configure Xtensa MMU option",
+ .usage = "<NIREFILLENTRIES> <NDREFILLENTRIES> <IVARWAY56> <DVARWAY56>",
+ },
+ {
+ .name = "xtmpu",
+ .handler = esp_xtensa_smp_cmd_xtmpu,
+ .mode = COMMAND_CONFIG,
+ .help = "Configure Xtensa MPU option",
+ .usage = "<num FG seg> <min seg size> <lockable> <executeonly>",
+ },
+ {
+ .name = "xtreg",
+ .handler = esp_xtensa_smp_cmd_xtreg,
+ .mode = COMMAND_CONFIG,
+ .help = "Configure Xtensa register",
+ .usage = "<regname> <regnum>",
+ },
+ {
+ .name = "xtregs",
+ .handler = esp_xtensa_smp_cmd_xtreg,
+ .mode = COMMAND_CONFIG,
+ .help = "Configure number of Xtensa registers",
+ .usage = "<numregs>",
+ },
+ {
+ .name = "xtregfmt",
+ .handler = esp_xtensa_smp_cmd_xtregfmt,
+ .mode = COMMAND_CONFIG,
+ .help = "Configure format of Xtensa register map",
+ .usage = "<numgregs>",
+ },
{
.name = "set_permissive",
.handler = esp_xtensa_smp_cmd_permissive_mode,
diff --git a/src/target/espressif/esp_xtensa_smp.h b/src/target/espressif/esp_xtensa_smp.h
index 159125d37..bafd42066 100644
--- a/src/target/espressif/esp_xtensa_smp.h
+++ b/src/target/espressif/esp_xtensa_smp.h
@@ -43,7 +43,6 @@ int esp_xtensa_smp_handle_target_event(struct target *target, enum target_event
int esp_xtensa_smp_target_init(struct command_context *cmd_ctx, struct target *target);
int esp_xtensa_smp_init_arch_info(struct target *target,
struct esp_xtensa_smp_common *esp_xtensa_smp,
- const struct xtensa_config *xtensa_cfg,
struct xtensa_debug_module_config *dm_cfg,
const struct esp_xtensa_smp_chip_ops *chip_ops);
diff --git a/src/target/target.c b/src/target/target.c
index 10a25efde..9b07dbf61 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -77,6 +77,7 @@ extern struct target_type fa526_target;
extern struct target_type feroceon_target;
extern struct target_type dragonite_target;
extern struct target_type xscale_target;
+extern struct target_type xtensa_chip_target;
extern struct target_type cortexm_target;
extern struct target_type cortexa_target;
extern struct target_type aarch64_target;
@@ -118,6 +119,7 @@ static struct target_type *target_types[] = {
&feroceon_target,
&dragonite_target,
&xscale_target,
+ &xtensa_chip_target,
&cortexm_target,
&cortexa_target,
&cortexr4_target,
diff --git a/src/target/xtensa/Makefile.am b/src/target/xtensa/Makefile.am
index a11e58530..94c7c4a85 100644
--- a/src/target/xtensa/Makefile.am
+++ b/src/target/xtensa/Makefile.am
@@ -4,6 +4,8 @@ noinst_LTLIBRARIES += %D%/libxtensa.la
%C%_libxtensa_la_SOURCES = \
%D%/xtensa.c \
%D%/xtensa.h \
+ %D%/xtensa_chip.c \
+ %D%/xtensa_chip.h \
%D%/xtensa_debug_module.c \
%D%/xtensa_debug_module.h \
%D%/xtensa_regs.h
diff --git a/src/target/xtensa/xtensa.c b/src/target/xtensa/xtensa.c
index 6f9d77e6c..fe0f43882 100644
--- a/src/target/xtensa/xtensa.c
+++ b/src/target/xtensa/xtensa.c
@@ -2,6 +2,7 @@
/***************************************************************************
* Generic Xtensa target API for OpenOCD *
+ * Copyright (C) 2020-2022 Cadence Design Systems, Inc. *
* Copyright (C) 2016-2019 Espressif Systems Ltd. *
* Derived from esp108.c *
* Author: Angus Gratton gu...@pr... *
@@ -16,325 +17,270 @@
#include <helper/align.h>
#include <target/register.h>
+#include "xtensa_chip.h"
#include "xtensa.h"
-
-#define _XT_INS_FORMAT_RSR(OPCODE, SR, T) ((OPCODE) \
- | (((SR) & 0xFF) << 8) \
+/* Swap 4-bit Xtensa opcodes and fields */
+#define XT_NIBSWAP8(V) \
+ ((((V) & 0x0F) << 4) \
+ | (((V) & 0xF0) >> 4))
+
+#define XT_NIBSWAP16(V) \
+ ((((V) & 0x000F) << 12) \
+ | (((V) & 0x00F0) << 4) \
+ | (((V) & 0x0F00) >> 4) \
+ | (((V) & 0xF000) >> 12))
+
+#define XT_NIBSWAP24(V) \
+ ((((V) & 0x00000F) << 20) \
+ | (((V) & 0x0000F0) << 12) \
+ | (((V) & 0x000F00) << 4) \
+ | (((V) & 0x00F000) >> 4) \
+ | (((V) & 0x0F0000) >> 12) \
+ | (((V) & 0xF00000) >> 20))
+
+/* _XT_INS_FORMAT_*()
+ * Instruction formatting converted from little-endian inputs
+ * and shifted to the MSB-side of DIR for BE systems.
+ */
+#define _XT_INS_FORMAT_RSR(X, OPCODE, SR, T) \
+ (XT_ISBE(X) ? (XT_NIBSWAP24(OPCODE) \
+ | (((T) & 0x0F) << 16) \
+ | (((SR) & 0xFF) << 8)) << 8 \
+ : (OPCODE) \
+ | (((SR) & 0xFF) << 8) \
| (((T) & 0x0F) << 4))
-#define _XT_INS_FORMAT_RRR(OPCODE, ST, R) ((OPCODE) \
- | (((ST) & 0xFF) << 4) \
+#define _XT_INS_FORMAT_RRR(X, OPCODE, ST, R) \
+ (XT_ISBE(X) ? (XT_NIBSWAP24(OPCODE) \
+ | ((XT_NIBSWAP8((ST) & 0xFF)) << 12) \
+ | (((R) & 0x0F) << 8)) << 8 \
+ : (OPCODE) \
+ | (((ST) & 0xFF) << 4) \
| (((R) & 0x0F) << 12))
-#define _XT_INS_FORMAT_RRRN(OPCODE, S, T, IMM4) ((OPCODE) \
- | (((T) & 0x0F) << 4) \
- | (((S) & 0x0F) << 8) \
+#define _XT_INS_FORMAT_RRRN(X, OPCODE, S, T, IMM4) \
+ (XT_ISBE(X) ? (XT_NIBSWAP16(OPCODE) \
+ | (((T) & 0x0F) << 8) \
+ | (((S) & 0x0F) << 4) \
+ | ((IMM4) & 0x0F)) << 16 \
+ : (OPCODE) \
+ | (((T) & 0x0F) << 4) \
+ | (((S) & 0x0F) << 8) \
| (((IMM4) & 0x0F) << 12))
-#define _XT_INS_FORMAT_RRI8(OPCODE, R, S, T, IMM8) ((OPCODE) \
- | (((IMM8) & 0xFF) << 16) \
- | (((R) & 0x0F) << 12) \
- | (((S) & 0x0F) << 8) \
+#define _XT_INS_FORMAT_RRI8(X, OPCODE, R, S, T, IMM8) \
+ (XT_ISBE(X) ? (XT_NIBSWAP24(OPCODE) \
+ | (((T) & 0x0F) << 16) \
+ | (((S) & 0x0F) << 12) \
+ | (((R) & 0x0F) << 8) \
+ | ((IMM8) & 0xFF)) << 8 \
+ : (OPCODE) \
+ | (((IMM8) & 0xFF) << 16) \
+ | (((R) & 0x0F) << 12) \
+ | (((S) & 0x0F) << 8) \
| (((T) & 0x0F) << 4))
-#define _XT_INS_FORMAT_RRI4(OPCODE, IMM4, R, S, T) ((OPCODE) \
- | (((IMM4) & 0x0F) << 20) \
- | (((R) & 0x0F) << 12) \
- | (((S) & 0x0F) << 8) \
+#define _XT_INS_FORMAT_RRI4(X, OPCODE, IMM4, R, S, T) \
+ (XT_ISBE(X) ? (XT_NIBSWAP24(OPCODE) \
+ | (((T) & 0x0F) << 16) \
+ | (((S) & 0x0F) << 12) \
+ | (((R) & 0x0F) << 8)) << 8 \
+ | ((IMM4) & 0x0F) \
+ : (OPCODE) \
+ | (((IMM4) & 0x0F) << 20) \
+ | (((R) & 0x0F) << 12) \
+ | (((S) & 0x0F) << 8) \
| (((T) & 0x0F) << 4))
/* Xtensa processor instruction opcodes
- * "Return From Debug Operation" to Normal */
-#define XT_INS_RFDO 0xf1e000
+*/
+/* "Return From Debug Operation" to Normal */
+#define XT_INS_RFDO(X) (XT_ISBE(X) ? 0x000e1f << 8 : 0xf1e000)
/* "Return From Debug and Dispatch" - allow sw debugging stuff to take over */
-#define XT_INS_RFDD 0xf1e010
+#define XT_INS_RFDD(X) (XT_ISBE(X) ? 0x010e1f << 8 : 0xf1e010)
/* Load to DDR register, increase addr register */
-#define XT_INS_LDDR32P(S) (0x0070E0 | ((S) << 8))
+#define XT_INS_LDDR32P(X, S) (XT_ISBE(X) ? (0x0E0700 | ((S) << 12)) << 8 : (0x0070E0 | ((S) << 8)))
/* Store from DDR register, increase addr register */
-#define XT_INS_SDDR32P(S) (0x0070F0 | ((S) << 8))
-
-/* Load 32-bit Indirect from A(S) + 4 * IMM8 to A(T) */
-#define XT_INS_L32I(S, T, IMM8) _XT_INS_FORMAT_RRI8(0x002002, 0, S, T, IMM8)
-/* Load 16-bit Unsigned from A(S) + 2 * IMM8 to A(T) */
-#define XT_INS_L16UI(S, T, IMM8) _XT_INS_FORMAT_RRI8(0x001002, 0, S, T, IMM8)
-/* Load 8-bit Unsigned from A(S) + IMM8 to A(T) */
-#define XT_INS_L8UI(S, T, IMM8) _XT_INS_FORMAT_RRI8(0x000002, 0, S, T, IMM8)
-
-/* Store 32-bit Indirect to A(S) + 4 * IMM8 from A(T) */
-#define XT_INS_S32I(S, T, IMM8) _XT_INS_FORMAT_RRI8(0x006002, 0, S, T, IMM8)
-/* Store 16-bit to A(S) + 2 * IMM8 from A(T) */
-#define XT_INS_S16I(S, T, IMM8) _XT_INS_FORMAT_RRI8(0x005002, 0, S, T, IMM8)
-/* Store 8-bit to A(S) + IMM8 from A(T) */
-#define XT_INS_S8I(S, T, IMM8) _XT_INS_FORMAT_RRI8(0x004002, 0, S, T, IMM8)
+#define XT_INS_SDDR32P(X, S) (XT_ISBE(X) ? (0x0F0700 | ((S) << 12)) << 8 : (0x0070F0 | ((S) << 8)))
+
+/* Load 32-bit Indirect from A(S)+4*IMM8 to A(T) */
+#define XT_INS_L32I(X, S, T, IMM8) _XT_INS_FORMAT_RRI8(X, 0x002002, 0, S, T, IMM8)
+/* Load 16-bit Unsigned from A(S)+2*IMM8 to A(T) */
+#define XT_INS_L16UI(X, S, T, IMM8) _XT_INS_FORMAT_RRI8(X, 0x001002, 0, S, T, IMM8)
+/* Load 8-bit Unsigned f...
[truncated message content] |
