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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.11.0-702-g78c87f5e8
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From: OpenOCD-Gerrit <ope...@us...> - 2022-06-04 08:19:40
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- Log -----------------------------------------------------------------
commit 78c87f5e81f8b3ee2a72aa546f87985596cb2b9f
Author: Erhan Kurubas <erh...@es...>
Date: Thu Apr 21 07:53:54 2022 +0200
target: add Espressif ESP32-S2 basic support
ESP32-S2 is a single core Xtensa chip.
Not full featured yet. Some of the missing functionality:
-Semihosting
-Flash breakpoints
-Flash loader
-Apptrace
-FreeRTOS
Signed-off-by: Erhan Kurubas <erh...@es...>
Change-Id: I2fb32978e801af5aa21616c581691406ad7cd6bb
Reviewed-on: https://review.openocd.org/c/openocd/+/6940
Reviewed-by: Tomas Vanek <va...@fb...>
Reviewed-by: Ian Thompson <ia...@ca...>
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/doc/openocd.texi b/doc/openocd.texi
index cc1d10441..85be06ea6 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -4895,6 +4895,7 @@ compact Thumb2 instruction set. Supports also ARMv6-M and ARMv8-M cores
@item @code{dsp5680xx} -- implements Freescale's 5680x DSP.
@item @code{esirisc} -- this is an EnSilica eSi-RISC core.
The current implementation supports eSi-32xx cores.
+@item @code{esp32s2} -- this is an Espressif SoC with single Xtensa core.
@item @code{fa526} -- resembles arm920 (w/o Thumb).
@item @code{feroceon} -- resembles arm926.
@item @code{hla_target} -- a Cortex-M alternative to work with HL adapters like ST-Link.
@@ -10956,6 +10957,94 @@ STMicroelectronics, based on a proprietary 8-bit core architecture.
OpenOCD supports debugging STM8 through the STMicroelectronics debug
protocol SWIM, @pxref{swimtransport,,SWIM}.
+@section Xtensa Architecture
+Xtensa processors are based on a modular, highly flexible 32-bit RISC architecture
+that can easily scale from a tiny, cache-less controller or task engine to a high-performance
+SIMD/VLIW DSP provided by Cadence.
+@url{https://www.cadence.com/en_US/home/tools/ip/tensilica-ip/tensilica-xtensa-controllers-and-extensible-processors.html}.
+
+OpenOCD supports generic Xtensa processors implementation which can be customized by
+simply providing vendor-specific core configuration which controls every configurable
+Xtensa architecture option, e.g. number of address registers, exceptions, reduced
+size instructions support, memory banks configuration etc. Also OpenOCD supports SMP
+configurations for Xtensa processors with any number of cores and allows to configure
+their debug signals interconnection (so-called "break/stall networks") which control how
+debug signals are distributed among cores. Xtensa "break networks" are compatible with
+ARM's Cross Trigger Interface (CTI). For debugging code on Xtensa chips OpenOCD
+uses JTAG protocol. Currently OpenOCD implements several Epsressif Xtensa-based chips of
+@uref{https://www.espressif.com/en/products/socs, ESP32 family}.
+
+@subsection General Xtensa Commands
+
+@deffn {Command} {xtensa set_permissive} (0|1)
+By default accessing memory beyond defined regions is forbidden. This commnd controls memory access address check.
+When set to (1), skips access controls and address range check before read/write memory.
+@end deffn
+
+@deffn {Command} {xtensa maskisr} (on|off)
+Selects whether interrupts will be disabled during stepping over single instruction. The default configuration is (off).
+@end deffn
+
+@deffn {Command} {xtensa smpbreak} [none|breakinout|runstall] | [BreakIn] [BreakOut] [RunStallIn] [DebugModeOut]
+Configures debug signals connection ("break network") for currently selected core.
+@itemize @bullet
+@item @code{none} - Core's "break/stall network" is disconnected. Core is not affected by any debug
+signal from other cores.
+@item @code{breakinout} - Core's "break network" is fully connected (break inputs and outputs are enabled).
+Core will receive debug break signals from other cores and send such signals to them. For example when another core
+is stopped due to breakpoint hit this core will be stopped too and vice versa.
+@item @code{runstall} - Core's "stall network" is fully connected (stall inputs and outputs are enabled).
+This feature is not well implemented and tested yet.
+@item @code{BreakIn} - Core's "break-in" signal is enabled.
+Core will receive debug break signals from other cores. For example when another core is
+stopped due to breakpoint hit this core will be stopped too.
+@item @code{BreakOut} - Core's "break-out" signal is enabled.
+Core will send debug break signal to other cores. For example when this core is
+stopped due to breakpoint hit other cores with enabled break-in signals will be stopped too.
+@item @code{RunStallIn} - Core's "runstall-in" signal is enabled.
+This feature is not well implemented and tested yet.
+@item @code{DebugModeOut} - Core's "debugmode-out" signal is enabled.
+This feature is not well implemented and tested yet.
+@end itemize
+@end deffn
+
+@deffn {Command} {xtensa perfmon_enable} <counter_id> <select> [mask] [kernelcnt] [tracelevel]
+Enable and start performance counter.
+@itemize @bullet
+@item @code{counter_id} - Counter ID (0-1).
+@item @code{select} - Selects performance metric to be counted by the counter,
+e.g. 0 - CPU cycles, 2 - retired instructions.
+@item @code{mask} - Selects input subsets to be counted (counter will
+increment only once even if more than one condition corresponding to a mask bit occurs).
+@item @code{kernelcnt} - 0 - count events with "CINTLEVEL <= tracelevel",
+1 - count events with "CINTLEVEL > tracelevel".
+@item @code{tracelevel} - Compares this value to "CINTLEVEL" when deciding
+whether to count.
+@end itemize
+@end deffn
+
+@deffn {Command} {xtensa perfmon_dump} (counter_id)
+Dump performance counter value. If no argument specified, dumps all counters.
+@end deffn
+
+@deffn {Command} {xtensa tracestart} [pc <pcval>/[<maskbitcount>]] [after <n> [ins|words]]
+Set up and start a HW trace. Optionally set PC address range to trigger tracing stop when reached during program execution.
+This command also allows to specify the amount of data to capture after stop trigger activation.
+@itemize @bullet
+@item @code{pcval} - PC value which will trigger trace data collection stop.
+@item @code{maskbitcount} - PC value mask.
+@item @code{n} - Maximum number of instructions/words to capture after trace stop trigger.
+@end itemize
+@end deffn
+
+@deffn {Command} {xtensa tracestop}
+Stop current trace as started by the tracestart command.
+@end deffn
+
+@deffn {Command} {xtensa tracedump} <outfile>
+Dump trace memory to a file.
+@end deffn
+
@anchor{softwaredebugmessagesandtracing}
@section Software Debug Messages and Tracing
@cindex Linux-ARM DCC support
diff --git a/src/target/Makefile.am b/src/target/Makefile.am
index 49e882fe6..799c3dd07 100644
--- a/src/target/Makefile.am
+++ b/src/target/Makefile.am
@@ -1,5 +1,7 @@
%C%_libtarget_la_LIBADD = %D%/openrisc/libopenrisc.la \
- %D%/riscv/libriscv.la
+ %D%/riscv/libriscv.la \
+ %D%/xtensa/libxtensa.la \
+ %D%/espressif/libespressif.la
%C%_libtarget_la_CPPFLAGS = $(AM_CPPFLAGS)
@@ -260,3 +262,5 @@ ARC_SRC = \
include %D%/openrisc/Makefile.am
include %D%/riscv/Makefile.am
+include %D%/xtensa/Makefile.am
+include %D%/espressif/Makefile.am
\ No newline at end of file
diff --git a/src/target/espressif/Makefile.am b/src/target/espressif/Makefile.am
new file mode 100644
index 000000000..c681e09aa
--- /dev/null
+++ b/src/target/espressif/Makefile.am
@@ -0,0 +1,6 @@
+noinst_LTLIBRARIES += %D%/libespressif.la
+%C%_libespressif_la_SOURCES = \
+ %D%/esp_xtensa.c \
+ %D%/esp_xtensa.h \
+ %D%/esp32s2.c \
+ %D%/esp32s2.h
diff --git a/src/target/espressif/esp32s2.c b/src/target/espressif/esp32s2.c
new file mode 100644
index 000000000..212533ff8
--- /dev/null
+++ b/src/target/espressif/esp32s2.c
@@ -0,0 +1,715 @@
+/***************************************************************************
+ * ESP32-S2 target for OpenOCD *
+ * Copyright (C) 2019 Espressif Systems Ltd. *
+ * Author: Alexey Gerenkov <al...@es...> *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "assert.h"
+#include <target/target.h>
+#include <target/target_type.h>
+#include "esp_xtensa.h"
+#include "esp32s2.h"
+
+/* Overall memory map
+ * TODO: read memory configuration from target registers */
+#define ESP32_S2_IROM_MASK_LOW 0x40000000
+#define ESP32_S2_IROM_MASK_HIGH 0x40020000
+#define ESP32_S2_IRAM_LOW 0x40020000
+#define ESP32_S2_IRAM_HIGH 0x40070000
+#define ESP32_S2_DRAM_LOW 0x3ffb0000
+#define ESP32_S2_DRAM_HIGH 0x40000000
+#define ESP32_S2_RTC_IRAM_LOW 0x40070000
+#define ESP32_S2_RTC_IRAM_HIGH 0x40072000
+#define ESP32_S2_RTC_DRAM_LOW 0x3ff9e000
+#define ESP32_S2_RTC_DRAM_HIGH 0x3ffa0000
+#define ESP32_S2_RTC_DATA_LOW 0x50000000
+#define ESP32_S2_RTC_DATA_HIGH 0x50002000
+#define ESP32_S2_EXTRAM_DATA_LOW 0x3f500000
+#define ESP32_S2_EXTRAM_DATA_HIGH 0x3ff80000
+#define ESP32_S2_DR_REG_LOW 0x3f400000
+#define ESP32_S2_DR_REG_HIGH 0x3f4d3FFC
+#define ESP32_S2_SYS_RAM_LOW 0x60000000UL
+#define ESP32_S2_SYS_RAM_HIGH (ESP32_S2_SYS_RAM_LOW + 0x20000000UL)
+/* ESP32-S2 DROM mapping is not contiguous. */
+/* IDF declares this as 0x3F000000..0x3FF80000, but there are peripheral registers mapped to
+ * 0x3f400000..0x3f4d3FFC. */
+#define ESP32_S2_DROM0_LOW ESP32_S2_DROM_LOW
+#define ESP32_S2_DROM0_HIGH ESP32_S2_DR_REG_LOW
+#define ESP32_S2_DROM1_LOW ESP32_S2_DR_REG_HIGH
+#define ESP32_S2_DROM1_HIGH ESP32_S2_DROM_HIGH
+
+/* ESP32 WDT */
+#define ESP32_S2_WDT_WKEY_VALUE 0x50d83aa1
+#define ESP32_S2_TIMG0_BASE 0x3f41F000
+#define ESP32_S2_TIMG1_BASE 0x3f420000
+#define ESP32_S2_TIMGWDT_CFG0_OFF 0x48
+#define ESP32_S2_TIMGWDT_PROTECT_OFF 0x64
+#define ESP32_S2_TIMG0WDT_CFG0 (ESP32_S2_TIMG0_BASE + ESP32_S2_TIMGWDT_CFG0_OFF)
+#define ESP32_S2_TIMG1WDT_CFG0 (ESP32_S2_TIMG1_BASE + ESP32_S2_TIMGWDT_CFG0_OFF)
+#define ESP32_S2_TIMG0WDT_PROTECT (ESP32_S2_TIMG0_BASE + ESP32_S2_TIMGWDT_PROTECT_OFF)
+#define ESP32_S2_TIMG1WDT_PROTECT (ESP32_S2_TIMG1_BASE + ESP32_S2_TIMGWDT_PROTECT_OFF)
+#define ESP32_S2_RTCCNTL_BASE 0x3f408000
+#define ESP32_S2_RTCWDT_CFG_OFF 0x94
+#define ESP32_S2_RTCWDT_PROTECT_OFF 0xAC
+#define ESP32_S2_SWD_CONF_OFF 0xB0
+#define ESP32_S2_SWD_WPROTECT_OFF 0xB4
+#define ESP32_S2_RTC_CNTL_DIG_PWC_REG_OFF 0x8C
+#define ESP32_S2_RTC_CNTL_DIG_PWC_REG (ESP32_S2_RTCCNTL_BASE + ESP32_S2_RTC_CNTL_DIG_PWC_REG_OFF)
+#define ESP32_S2_RTCWDT_CFG (ESP32_S2_RTCCNTL_BASE + ESP32_S2_RTCWDT_CFG_OFF)
+#define ESP32_S2_RTCWDT_PROTECT (ESP32_S2_RTCCNTL_BASE + ESP32_S2_RTCWDT_PROTECT_OFF)
+#define ESP32_S2_SWD_CONF_REG (ESP32_S2_RTCCNTL_BASE + ESP32_S2_SWD_CONF_OFF)
+#define ESP32_S2_SWD_WPROTECT_REG (ESP32_S2_RTCCNTL_BASE + ESP32_S2_SWD_WPROTECT_OFF)
+#define ESP32_S2_SWD_AUTO_FEED_EN_M BIT(31)
+#define ESP32_S2_SWD_WKEY_VALUE 0x8F1D312AU
+#define ESP32_S2_OPTIONS0 (ESP32_S2_RTCCNTL_BASE + 0x0000)
+#define ESP32_S2_SW_SYS_RST_M 0x80000000
+#define ESP32_S2_SW_SYS_RST_V 0x1
+#define ESP32_S2_SW_SYS_RST_S 31
+#define ESP32_S2_SW_STALL_PROCPU_C0_M ((ESP32_S2_SW_STALL_PROCPU_C0_V) << (ESP32_S2_SW_STALL_PROCPU_C0_S))
+#define ESP32_S2_SW_STALL_PROCPU_C0_V 0x3
+#define ESP32_S2_SW_STALL_PROCPU_C0_S 2
+#define ESP32_S2_SW_CPU_STALL (ESP32_S2_RTCCNTL_BASE + 0x00B8)
+#define ESP32_S2_SW_STALL_PROCPU_C1_M ((ESP32_S2_SW_STALL_PROCPU_C1_V) << (ESP32_S2_SW_STALL_PROCPU_C1_S))
+#define ESP32_S2_SW_STALL_PROCPU_C1_V 0x3FU
+#define ESP32_S2_SW_STALL_PROCPU_C1_S 26
+#define ESP32_S2_CLK_CONF (ESP32_S2_RTCCNTL_BASE + 0x0074)
+#define ESP32_S2_CLK_CONF_DEF 0x1583218
+#define ESP32_S2_STORE4 (ESP32_S2_RTCCNTL_BASE + 0x00BC)
+#define ESP32_S2_STORE5 (ESP32_S2_RTCCNTL_BASE + 0x00C0)
+#define ESP32_S2_DPORT_PMS_OCCUPY_3 0x3F4C10E0
+
+#define ESP32_S2_TRACEMEM_BLOCK_SZ 0x4000
+
+#define ESP32_S2_DR_REG_UART_BASE 0x3f400000
+#define ESP32_S2_REG_UART_BASE(i) (ESP32_S2_DR_REG_UART_BASE + (i) * 0x10000)
+#define ESP32_S2_UART_DATE_REG(i) (ESP32_S2_REG_UART_BASE(i) + 0x74)
+
+/* this should map local reg IDs to GDB reg mapping as defined in xtensa-config.c 'rmap' in
+ * xtensa-overlay */
+static const unsigned int esp32s2_gdb_regs_mapping[ESP32_S2_NUM_REGS] = {
+ XT_REG_IDX_PC,
+ XT_REG_IDX_AR0, XT_REG_IDX_AR1, XT_REG_IDX_AR2, XT_REG_IDX_AR3,
+ XT_REG_IDX_AR4, XT_REG_IDX_AR5, XT_REG_IDX_AR6, XT_REG_IDX_AR7,
+ XT_REG_IDX_AR8, XT_REG_IDX_AR9, XT_REG_IDX_AR10, XT_REG_IDX_AR11,
+ XT_REG_IDX_AR12, XT_REG_IDX_AR13, XT_REG_IDX_AR14, XT_REG_IDX_AR15,
+ XT_REG_IDX_AR16, XT_REG_IDX_AR17, XT_REG_IDX_AR18, XT_REG_IDX_AR19,
+ XT_REG_IDX_AR20, XT_REG_IDX_AR21, XT_REG_IDX_AR22, XT_REG_IDX_AR23,
+ XT_REG_IDX_AR24, XT_REG_IDX_AR25, XT_REG_IDX_AR26, XT_REG_IDX_AR27,
+ XT_REG_IDX_AR28, XT_REG_IDX_AR29, XT_REG_IDX_AR30, XT_REG_IDX_AR31,
+ XT_REG_IDX_AR32, XT_REG_IDX_AR33, XT_REG_IDX_AR34, XT_REG_IDX_AR35,
+ XT_REG_IDX_AR36, XT_REG_IDX_AR37, XT_REG_IDX_AR38, XT_REG_IDX_AR39,
+ XT_REG_IDX_AR40, XT_REG_IDX_AR41, XT_REG_IDX_AR42, XT_REG_IDX_AR43,
+ XT_REG_IDX_AR44, XT_REG_IDX_AR45, XT_REG_IDX_AR46, XT_REG_IDX_AR47,
+ XT_REG_IDX_AR48, XT_REG_IDX_AR49, XT_REG_IDX_AR50, XT_REG_IDX_AR51,
+ XT_REG_IDX_AR52, XT_REG_IDX_AR53, XT_REG_IDX_AR54, XT_REG_IDX_AR55,
+ XT_REG_IDX_AR56, XT_REG_IDX_AR57, XT_REG_IDX_AR58, XT_REG_IDX_AR59,
+ XT_REG_IDX_AR60, XT_REG_IDX_AR61, XT_REG_IDX_AR62, XT_REG_IDX_AR63,
+ XT_REG_IDX_SAR,
+ XT_REG_IDX_WINDOWBASE, XT_REG_IDX_WINDOWSTART, XT_REG_IDX_CONFIGID0, XT_REG_IDX_CONFIGID1,
+ XT_REG_IDX_PS, XT_REG_IDX_THREADPTR,
+ ESP32_S2_REG_IDX_GPIOOUT,
+ XT_REG_IDX_MMID, XT_REG_IDX_IBREAKENABLE, XT_REG_IDX_OCD_DDR,
+ XT_REG_IDX_IBREAKA0, XT_REG_IDX_IBREAKA1, XT_REG_IDX_DBREAKA0, XT_REG_IDX_DBREAKA1,
+ XT_REG_IDX_DBREAKC0, XT_REG_IDX_DBREAKC1,
+ XT_REG_IDX_EPC1, XT_REG_IDX_EPC2, XT_REG_IDX_EPC3, XT_REG_IDX_EPC4,
+ XT_REG_IDX_EPC5, XT_REG_IDX_EPC6, XT_REG_IDX_EPC7, XT_REG_IDX_DEPC,
+ XT_REG_IDX_EPS2, XT_REG_IDX_EPS3, XT_REG_IDX_EPS4, XT_REG_IDX_EPS5,
+ XT_REG_IDX_EPS6, XT_REG_IDX_EPS7,
+ XT_REG_IDX_EXCSAVE1, XT_REG_IDX_EXCSAVE2, XT_REG_IDX_EXCSAVE3, XT_REG_IDX_EXCSAVE4,
+ XT_REG_IDX_EXCSAVE5, XT_REG_IDX_EXCSAVE6, XT_REG_IDX_EXCSAVE7, XT_REG_IDX_CPENABLE,
+ XT_REG_IDX_INTERRUPT, XT_REG_IDX_INTSET, XT_REG_IDX_INTCLEAR, XT_REG_IDX_INTENABLE,
+ XT_REG_IDX_VECBASE, XT_REG_IDX_EXCCAUSE, XT_REG_IDX_DEBUGCAUSE, XT_REG_IDX_CCOUNT,
+ XT_REG_IDX_PRID, XT_REG_IDX_ICOUNT, XT_REG_IDX_ICOUNTLEVEL, XT_REG_IDX_EXCVADDR,
+ XT_REG_IDX_CCOMPARE0, XT_REG_IDX_CCOMPARE1, XT_REG_IDX_CCOMPARE2,
+ XT_REG_IDX_MISC0, XT_REG_IDX_MISC1, XT_REG_IDX_MISC2, XT_REG_IDX_MISC3,
+ XT_REG_IDX_A0, XT_REG_IDX_A1, XT_REG_IDX_A2, XT_REG_IDX_A3,
+ XT_REG_IDX_A4, XT_REG_IDX_A5, XT_REG_IDX_A6, XT_REG_IDX_A7,
+ XT_REG_IDX_A8, XT_REG_IDX_A9, XT_REG_IDX_A10, XT_REG_IDX_A11,
+ XT_REG_IDX_A12, XT_REG_IDX_A13, XT_REG_IDX_A14, XT_REG_IDX_A15,
+ XT_REG_IDX_PWRCTL, XT_REG_IDX_PWRSTAT, XT_REG_IDX_ERISTAT,
+ XT_REG_IDX_CS_ITCTRL, XT_REG_IDX_CS_CLAIMSET, XT_REG_IDX_CS_CLAIMCLR,
+ XT_REG_IDX_CS_LOCKACCESS, XT_REG_IDX_CS_LOCKSTATUS, XT_REG_IDX_CS_AUTHSTATUS,
+ XT_REG_IDX_FAULT_INFO,
+ XT_REG_IDX_TRAX_ID, XT_REG_IDX_TRAX_CTRL, XT_REG_IDX_TRAX_STAT,
+ XT_REG_IDX_TRAX_DATA, XT_REG_IDX_TRAX_ADDR, XT_REG_IDX_TRAX_PCTRIGGER,
+ XT_REG_IDX_TRAX_PCMATCH, XT_REG_IDX_TRAX_DELAY, XT_REG_IDX_TRAX_MEMSTART,
+ XT_REG_IDX_TRAX_MEMEND,
+ XT_REG_IDX_PMG, XT_REG_IDX_PMPC, XT_REG_IDX_PM0, XT_REG_IDX_PM1,
+ XT_REG_IDX_PMCTRL0, XT_REG_IDX_PMCTRL1, XT_REG_IDX_PMSTAT0, XT_REG_IDX_PMSTAT1,
+ XT_REG_IDX_OCD_ID, XT_REG_IDX_OCD_DCRCLR, XT_REG_IDX_OCD_DCRSET, XT_REG_IDX_OCD_DSR,
+};
+
+static const struct xtensa_user_reg_desc esp32s2_user_regs[ESP32_S2_NUM_REGS - XT_NUM_REGS] = {
+ { "gpio_out", 0x00, 0, 32, &xtensa_user_reg_u32_type },
+};
+
+static const struct xtensa_config esp32s2_xtensa_cfg = {
+ .density = true,
+ .aregs_num = XT_AREGS_NUM_MAX,
+ .windowed = true,
+ .coproc = true,
+ .miscregs_num = 4,
+ .reloc_vec = true,
+ .proc_id = true,
+ .threadptr = true,
+ .user_regs_num = ARRAY_SIZE(esp32s2_user_regs),
+ .user_regs = esp32s2_user_regs,
+ .fetch_user_regs = xtensa_fetch_user_regs_u32,
+ .queue_write_dirty_user_regs = xtensa_queue_write_dirty_user_regs_u32,
+ .gdb_general_regs_num = ESP32_S2_NUM_REGS_G_COMMAND,
+ .gdb_regs_mapping = esp32s2_gdb_regs_mapping,
+ .irom = {
+ .count = 2,
+ .regions = {
+ {
+ .base = ESP32_S2_IROM_LOW,
+ .size = ESP32_S2_IROM_HIGH - ESP32_S2_IROM_LOW,
+ .access = XT_MEM_ACCESS_READ,
+ },
+ {
+ .base = ESP32_S2_IROM_MASK_LOW,
+ .size = ESP32_S2_IROM_MASK_HIGH - ESP32_S2_IROM_MASK_LOW,
+ .access = XT_MEM_ACCESS_READ,
+ },
+ }
+ },
+ .iram = {
+ .count = 2,
+ .regions = {
+ {
+ .base = ESP32_S2_IRAM_LOW,
+ .size = ESP32_S2_IRAM_HIGH - ESP32_S2_IRAM_LOW,
+ .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
+ },
+ {
+ .base = ESP32_S2_RTC_IRAM_LOW,
+ .size = ESP32_S2_RTC_IRAM_HIGH - ESP32_S2_RTC_IRAM_LOW,
+ .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
+ },
+ }
+ },
+ .drom = {
+ .count = 2,
+ .regions = {
+ {
+ .base = ESP32_S2_DROM0_LOW,
+ .size = ESP32_S2_DROM0_HIGH - ESP32_S2_DROM0_LOW,
+ .access = XT_MEM_ACCESS_READ,
+ },
+ {
+ .base = ESP32_S2_DROM1_LOW,
+ .size = ESP32_S2_DROM1_HIGH - ESP32_S2_DROM1_LOW,
+ .access = XT_MEM_ACCESS_READ,
+ },
+ }
+ },
+ .dram = {
+ .count = 6,
+ .regions = {
+ {
+ .base = ESP32_S2_DRAM_LOW,
+ .size = ESP32_S2_DRAM_HIGH - ESP32_S2_DRAM_LOW,
+ .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
+ },
+ {
+ .base = ESP32_S2_RTC_DRAM_LOW,
+ .size = ESP32_S2_RTC_DRAM_HIGH - ESP32_S2_RTC_DRAM_LOW,
+ .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
+ },
+ {
+ .base = ESP32_S2_RTC_DATA_LOW,
+ .size = ESP32_S2_RTC_DATA_HIGH - ESP32_S2_RTC_DATA_LOW,
+ .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
+ },
+ {
+ .base = ESP32_S2_EXTRAM_DATA_LOW,
+ .size = ESP32_S2_EXTRAM_DATA_HIGH - ESP32_S2_EXTRAM_DATA_LOW,
+ .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
+ },
+ {
+ .base = ESP32_S2_DR_REG_LOW,
+ .size = ESP32_S2_DR_REG_HIGH - ESP32_S2_DR_REG_LOW,
+ .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
+ },
+ {
+ .base = ESP32_S2_SYS_RAM_LOW,
+ .size = ESP32_S2_SYS_RAM_HIGH - ESP32_S2_SYS_RAM_LOW,
+ .access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
+ },
+ }
+ },
+ .exc = {
+ .enabled = true,
+ },
+ .irq = {
+ .enabled = true,
+ .irq_num = 32,
+ },
+ .high_irq = {
+ .enabled = true,
+ .excm_level = 3,
+ .nmi_num = 1,
+ },
+ .tim_irq = {
+ .enabled = true,
+ .comp_num = 3,
+ },
+ .debug = {
+ .enabled = true,
+ .irq_level = 6,
+ .ibreaks_num = 2,
+ .dbreaks_num = 2,
+ .icount_sz = 32,
+ },
+ .trace = {
+ .enabled = true,
+ .mem_sz = ESP32_S2_TRACEMEM_BLOCK_SZ,
+ },
+};
+
+struct esp32s2_common {
+ struct esp_xtensa_common esp_xtensa;
+};
+
+static int esp32s2_soc_reset(struct target *target);
+static int esp32s2_disable_wdts(struct target *target);
+
+static int esp32s2_assert_reset(struct target *target)
+{
+ return ERROR_OK;
+}
+
+static int esp32s2_deassert_reset(struct target *target)
+{
+ struct xtensa *xtensa = target_to_xtensa(target);
+
+ LOG_TARGET_DEBUG(target, "begin");
+
+ int res = xtensa_deassert_reset(target);
+ if (res != ERROR_OK)
+ return res;
+
+ /* restore configured value
+ esp32s2_soc_reset() modified it, but can not restore just after SW reset for some reason (???) */
+ res = xtensa_smpbreak_write(xtensa, xtensa->smp_break);
+ if (res != ERROR_OK) {
+ LOG_ERROR("Failed to restore smpbreak (%d)!", res);
+ return res;
+ }
+ return ERROR_OK;
+}
+
+int esp32s2_soft_reset_halt(struct target *target)
+{
+ LOG_TARGET_DEBUG(target, "begin");
+
+ /* Reset the SoC first */
+ int res = esp32s2_soc_reset(target);
+ if (res != ERROR_OK)
+ return res;
+ return xtensa_assert_reset(target);
+}
+
+static int esp32s2_set_peri_reg_mask(struct target *target,
+ target_addr_t addr,
+ uint32_t mask,
+ uint32_t val)
+{
+ uint32_t reg_val;
+ int res = target_read_u32(target, addr, ®_val);
+ if (res != ERROR_OK)
+ return res;
+ reg_val = (reg_val & (~mask)) | val;
+ res = target_write_u32(target, addr, reg_val);
+ if (res != ERROR_OK)
+ return res;
+
+ return ERROR_OK;
+}
+
+static int esp32s2_stall_set(struct target *target, bool stall)
+{
+ LOG_TARGET_DEBUG(target, "begin");
+
+ int res = esp32s2_set_peri_reg_mask(target,
+ ESP32_S2_SW_CPU_STALL,
+ ESP32_S2_SW_STALL_PROCPU_C1_M,
+ stall ? 0x21U << ESP32_S2_SW_STALL_PROCPU_C1_S : 0);
+ if (res != ERROR_OK) {
+ LOG_ERROR("Failed to write ESP32_S2_SW_CPU_STALL (%d)!", res);
+ return res;
+ }
+ res = esp32s2_set_peri_reg_mask(target,
+ ESP32_S2_OPTIONS0,
+ ESP32_S2_SW_STALL_PROCPU_C0_M,
+ stall ? 0x2 << ESP32_S2_SW_STALL_PROCPU_C0_S : 0);
+ if (res != ERROR_OK) {
+ LOG_ERROR("Failed to write ESP32_S2_OPTIONS0 (%d)!", res);
+ return res;
+ }
+ return ERROR_OK;
+}
+
+static inline int esp32s2_stall(struct target *target)
+{
+ return esp32s2_stall_set(target, true);
+}
+
+static inline int esp32s2_unstall(struct target *target)
+{
+ return esp32s2_stall_set(target, false);
+}
+
+/* Reset ESP32-S2's peripherals.
+Postconditions: all peripherals except RTC_CNTL are reset, CPU's PC is undefined, PRO CPU is halted, APP CPU is in reset
+How this works:
+0. make sure target is halted; if not, try to halt it; if that fails, try to reset it (via OCD) and then halt
+1. Resets clock related registers
+2. Stalls CPU
+3. trigger SoC reset using RTC_CNTL_SW_SYS_RST bit
+4. CPU is reset and stalled at the first reset vector instruction
+5. wait for the OCD to be reset
+6. halt the target
+7. Unstalls CPU
+8. Disables WDTs and trace memory mapping
+*/
+static int esp32s2_soc_reset(struct target *target)
+{
+ int res;
+ struct xtensa *xtensa = target_to_xtensa(target);
+
+ LOG_DEBUG("start");
+
+ /* In order to write to peripheral registers, target must be halted first */
+ if (target->state != TARGET_HALTED) {
+ LOG_TARGET_DEBUG(target, "Target not halted before SoC reset, trying to halt it first");
+ xtensa_halt(target);
+ res = target_wait_state(target, TARGET_HALTED, 1000);
+ if (res != ERROR_OK) {
+ LOG_TARGET_DEBUG(target, "Couldn't halt target before SoC reset, trying to do reset-halt");
+ res = xtensa_assert_reset(target);
+ if (res != ERROR_OK) {
+ LOG_TARGET_ERROR(
+ target,
+ "Couldn't halt target before SoC reset! (xtensa_assert_reset returned %d)",
+ res);
+ return res;
+ }
+ alive_sleep(10);
+ xtensa_poll(target);
+ int reset_halt_save = target->reset_halt;
+ target->reset_halt = 1;
+ res = xtensa_deassert_reset(target);
+ target->reset_halt = reset_halt_save;
+ if (res != ERROR_OK) {
+ LOG_TARGET_ERROR(
+ target,
+ "Couldn't halt target before SoC reset! (xtensa_deassert_reset returned %d)",
+ res);
+ return res;
+ }
+ alive_sleep(10);
+ xtensa_poll(target);
+ xtensa_halt(target);
+ res = target_wait_state(target, TARGET_HALTED, 1000);
+ if (res != ERROR_OK) {
+ LOG_TARGET_ERROR(target, "Couldn't halt target before SoC reset");
+ return res;
+ }
+ }
+ }
+
+ assert(target->state == TARGET_HALTED);
+
+ /* Set some clock-related RTC registers to the default values */
+ res = target_write_u32(target, ESP32_S2_STORE4, 0);
+ if (res != ERROR_OK) {
+ LOG_ERROR("Failed to write ESP32_S2_STORE4 (%d)!", res);
+ return res;
+ }
+ res = target_write_u32(target, ESP32_S2_STORE5, 0);
+ if (res != ERROR_OK) {
+ LOG_ERROR("Failed to write ESP32_S2_STORE5 (%d)!", res);
+ return res;
+ }
+ res = target_write_u32(target, ESP32_S2_RTC_CNTL_DIG_PWC_REG, 0);
+ if (res != ERROR_OK) {
+ LOG_ERROR("Failed to write ESP32_S2_RTC_CNTL_DIG_PWC_REG (%d)!", res);
+ return res;
+ }
+ res = target_write_u32(target, ESP32_S2_CLK_CONF, ESP32_S2_CLK_CONF_DEF);
+ if (res != ERROR_OK) {
+ LOG_ERROR("Failed to write ESP32_S2_CLK_CONF (%d)!", res);
+ return res;
+ }
+ /* Stall CPU */
+ res = esp32s2_stall(target);
+ if (res != ERROR_OK)
+ return res;
+ /* enable stall */
+ res = xtensa_smpbreak_write(xtensa, OCDDCR_RUNSTALLINEN);
+ if (res != ERROR_OK) {
+ LOG_ERROR("Failed to set smpbreak (%d)!", res);
+ return res;
+ }
+ /* Reset CPU */
+ xtensa->suppress_dsr_errors = true;
+ res = esp32s2_set_peri_reg_mask(target,
+ ESP32_S2_OPTIONS0,
+ ESP32_S2_SW_SYS_RST_M,
+ 1U << ESP32_S2_SW_SYS_RST_S);
+ xtensa->suppress_dsr_errors = false;
+ if (res != ERROR_OK) {
+ LOG_ERROR("Failed to write ESP32_S2_OPTIONS0 (%d)!", res);
+ return res;
+ }
+ /* Wait for SoC to reset */
+ alive_sleep(100);
+ int timeout = 100;
+ while (target->state != TARGET_RESET && target->state != TARGET_RUNNING && --timeout > 0) {
+ alive_sleep(10);
+ xtensa_poll(target);
+ }
+ if (timeout == 0) {
+ LOG_ERROR("Timed out waiting for CPU to be reset, target->state=%d", target->state);
+ return ERROR_TARGET_TIMEOUT;
+ }
+ xtensa_halt(target);
+ res = target_wait_state(target, TARGET_HALTED, 1000);
+ if (res != ERROR_OK) {
+ LOG_TARGET_ERROR(target, "Couldn't halt target before SoC reset");
+ return res;
+ }
+ /* Unstall CPU */
+ res = esp32s2_unstall(target);
+ if (res != ERROR_OK)
+ return res;
+ /* Disable WDTs */
+ res = esp32s2_disable_wdts(target);
+ if (res != ERROR_OK)
+ return res;
+ /* Disable trace memory mapping */
+ res = target_write_u32(target, ESP32_S2_DPORT_PMS_OCCUPY_3, 0);
+ if (res != ERROR_OK) {
+ LOG_ERROR("Failed to write ESP32_S2_DPORT_PMS_OCCUPY_3 (%d)!", res);
+ return res;
+ }
+ return ERROR_OK;
+}
+
+static int esp32s2_disable_wdts(struct target *target)
+{
+ /* TIMG1 WDT */
+ int res = target_write_u32(target, ESP32_S2_TIMG0WDT_PROTECT, ESP32_S2_WDT_WKEY_VALUE);
+ if (res != ERROR_OK) {
+ LOG_ERROR("Failed to write ESP32_S2_TIMG0WDT_PROTECT (%d)!", res);
+ return res;
+ }
+ res = target_write_u32(target, ESP32_S2_TIMG0WDT_CFG0, 0);
+ if (res != ERROR_OK) {
+ LOG_ERROR("Failed to write ESP32_S2_TIMG0WDT_CFG0 (%d)!", res);
+ return res;
+ }
+ /* TIMG2 WDT */
+ res = target_write_u32(target, ESP32_S2_TIMG1WDT_PROTECT, ESP32_S2_WDT_WKEY_VALUE);
+ if (res != ERROR_OK) {
+ LOG_ERROR("Failed to write ESP32_S2_TIMG1WDT_PROTECT (%d)!", res);
+ return res;
+ }
+ res = target_write_u32(target, ESP32_S2_TIMG1WDT_CFG0, 0);
+ if (res != ERROR_OK) {
+ LOG_ERROR("Failed to write ESP32_S2_TIMG1WDT_CFG0 (%d)!", res);
+ return res;
+ }
+ /* RTC WDT */
+ res = target_write_u32(target, ESP32_S2_RTCWDT_PROTECT, ESP32_S2_WDT_WKEY_VALUE);
+ if (res != ERROR_OK) {
+ LOG_ERROR("Failed to write ESP32_S2_RTCWDT_PROTECT (%d)!", res);
+ return res;
+ }
+ res = target_write_u32(target, ESP32_S2_RTCWDT_CFG, 0);
+ if (res != ERROR_OK) {
+ LOG_ERROR("Failed to write ESP32_S2_RTCWDT_CFG (%d)!", res);
+ return res;
+ }
+ /* Enable SWD auto-feed */
+ res = target_write_u32(target, ESP32_S2_SWD_WPROTECT_REG, ESP32_S2_SWD_WKEY_VALUE);
+ if (res != ERROR_OK) {
+ LOG_ERROR("Failed to write ESP32_S2_SWD_WPROTECT_REG (%d)!", res);
+ return res;
+ }
+ uint32_t swd_conf_reg = 0;
+ res = target_read_u32(target, ESP32_S2_SWD_CONF_REG, &swd_conf_reg);
+ if (res != ERROR_OK) {
+ LOG_ERROR("Failed to read ESP32_S2_SWD_CONF_REG (%d)!", res);
+ return res;
+ }
+ swd_conf_reg |= ESP32_S2_SWD_AUTO_FEED_EN_M;
+ res = target_write_u32(target, ESP32_S2_SWD_CONF_REG, swd_conf_reg);
+ if (res != ERROR_OK) {
+ LOG_ERROR("Failed to write ESP32_S2_SWD_CONF_REG (%d)!", res);
+ return res;
+ }
+ return ERROR_OK;
+}
+
+static int esp32s2_arch_state(struct target *target)
+{
+ return ERROR_OK;
+}
+
+static int esp32s2_on_halt(struct target *target)
+{
+ return esp32s2_disable_wdts(target);
+}
+
+static int esp32s2_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
+{
+ int ret = xtensa_step(target, current, address, handle_breakpoints);
+ if (ret == ERROR_OK) {
+ esp32s2_on_halt(target);
+ target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+ }
+ return ret;
+}
+
+static int esp32s2_poll(struct target *target)
+{
+ enum target_state old_state = target->state;
+ int ret = esp_xtensa_poll(target);
+
+ if (old_state != TARGET_HALTED && target->state == TARGET_HALTED) {
+ /* Call any event callbacks that are applicable */
+ if (old_state == TARGET_DEBUG_RUNNING) {
+ target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
+ } else {
+ esp32s2_on_halt(target);
+ target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+ }
+ }
+
+ return ret;
+}
+
+static int esp32s2_virt2phys(struct target *target,
+ target_addr_t virtual, target_addr_t *physical)
+{
+ *physical = virtual;
+ return ERROR_OK;
+}
+
+static int esp32s2_target_init(struct command_context *cmd_ctx, struct target *target)
+{
+ return esp_xtensa_target_init(cmd_ctx, target);
+}
+
+static const struct xtensa_debug_ops esp32s2_dbg_ops = {
+ .queue_enable = xtensa_dm_queue_enable,
+ .queue_reg_read = xtensa_dm_queue_reg_read,
+ .queue_reg_write = xtensa_dm_queue_reg_write
+};
+
+static const struct xtensa_power_ops esp32s2_pwr_ops = {
+ .queue_reg_read = xtensa_dm_queue_pwr_reg_read,
+ .queue_reg_write = xtensa_dm_queue_pwr_reg_write
+};
+
+static int esp32s2_target_create(struct target *target, Jim_Interp *interp)
+{
+ struct xtensa_debug_module_config esp32s2_dm_cfg = {
+ .dbg_ops = &esp32s2_dbg_ops,
+ .pwr_ops = &esp32s2_pwr_ops,
+ .tap = target->tap,
+ .queue_tdi_idle = NULL,
+ .queue_tdi_idle_arg = NULL
+ };
+
+ /* creates xtensa object */
+ struct esp32s2_common *esp32 = calloc(1, sizeof(*esp32));
+ if (!esp32) {
+ LOG_ERROR("Failed to alloc memory for arch info!");
+ return ERROR_FAIL;
+ }
+
+ int ret = esp_xtensa_init_arch_info(target, &esp32->esp_xtensa, &esp32s2_xtensa_cfg, &esp32s2_dm_cfg);
+ if (ret != ERROR_OK) {
+ LOG_ERROR("Failed to init arch info!");
+ free(esp32);
+ return ret;
+ }
+
+ /* Assume running target. If different, the first poll will fix this */
+ target->state = TARGET_RUNNING;
+ target->debug_reason = DBG_REASON_NOTHALTED;
+ return ERROR_OK;
+}
+
+static const struct command_registration esp32s2_command_handlers[] = {
+ {
+ .name = "xtensa",
+ .mode = COMMAND_ANY,
+ .help = "Xtensa commands group",
+ .usage = "",
+ .chain = xtensa_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+/* Holds methods for Xtensa targets. */
+struct target_type esp32s2_target = {
+ .name = "esp32s2",
+
+ .poll = esp32s2_poll,
+ .arch_state = esp32s2_arch_state,
+
+ .halt = xtensa_halt,
+ .resume = xtensa_resume,
+ .step = esp32s2_step,
+
+ .assert_reset = esp32s2_assert_reset,
+ .deassert_reset = esp32s2_deassert_reset,
+ .soft_reset_halt = esp32s2_soft_reset_halt,
+
+ .virt2phys = esp32s2_virt2phys,
+ .mmu = xtensa_mmu_is_enabled,
+ .read_memory = xtensa_read_memory,
+ .write_memory = xtensa_write_memory,
+
+ .read_buffer = xtensa_read_buffer,
+ .write_buffer = xtensa_write_buffer,
+
+ .checksum_memory = xtensa_checksum_memory,
+
+ .get_gdb_arch = xtensa_get_gdb_arch,
+ .get_gdb_reg_list = xtensa_get_gdb_reg_list,
+
+ .add_breakpoint = esp_xtensa_breakpoint_add,
+ .remove_breakpoint = esp_xtensa_breakpoint_remove,
+
+ .add_watchpoint = xtensa_watchpoint_add,
+ .remove_watchpoint = xtensa_watchpoint_remove,
+
+ .target_create = esp32s2_target_create,
+ .init_target = esp32s2_target_init,
+ .examine = xtensa_examine,
+ .deinit_target = esp_xtensa_target_deinit,
+
+ .commands = esp32s2_command_handlers,
+};
diff --git a/src/target/espressif/esp32s2.h b/src/target/espressif/esp32s2.h
new file mode 100644
index 000000000..2c43e3ec4
--- /dev/null
+++ b/src/target/espressif/esp32s2.h
@@ -0,0 +1,40 @@
+/***************************************************************************
+ * ESP32-S2 target for OpenOCD *
+ * Copyright (C) 2019 Espressif Systems Ltd. *
+ * Author: Alexey Gerenkov <al...@es...> *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
+ ***************************************************************************/
+
+#ifndef OPENOCD_TARGET_ESP32S2_H
+#define OPENOCD_TARGET_ESP32S2_H
+
+#include <target/xtensa/xtensa_regs.h>
+
+#define ESP32_S2_DROM_LOW 0x3f000000
+#define ESP32_S2_DROM_HIGH 0x3ff80000
+#define ESP32_S2_IROM_LOW 0x40080000
+#define ESP32_S2_IROM_HIGH 0x40800000
+
+/* Number of registers returned directly by the G command
+ * Corresponds to the amount of regs listed in regformats/reg-xtensa.dat in the gdb source */
+#define ESP32_S2_NUM_REGS_G_COMMAND 72
+
+enum esp32s2_reg_id {
+ /* chip specific registers that extend ISA go after ISA-defined ones */
+ ESP32_S2_REG_IDX_GPIOOUT = XT_USR_REG_START,
+ ESP32_S2_NUM_REGS,
+};
+
+#endif /* OPENOCD_TARGET_ESP32S2_H */
diff --git a/src/target/espressif/esp_xtensa.c b/src/target/espressif/esp_xtensa.c
new file mode 100644
index 000000000..89393f442
--- /dev/null
+++ b/src/target/espressif/esp_xtensa.c
@@ -0,0 +1,71 @@
+/***************************************************************************
+ * Espressif Xtensa target API for OpenOCD *
+ * Copyright (C) 2019 Espressif Systems Ltd. *
+ * Author: Alexey Gerenkov <al...@es...> *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include <config.h>
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <target/smp.h>
+#include "esp_xtensa.h"
+#include <target/register.h>
+
+int esp_xtensa_init_arch_info(struct target *target,
+ struct esp_xtensa_common *esp_xtensa,
+ const struct xtensa_config *xtensa_cfg,
+ struct xtensa_debug_module_config *dm_cfg)
+{
+ return xtensa_init_arch_info(target, &esp_xtensa->xtensa, xtensa_cfg, dm_cfg);
+}
+
+int esp_xtensa_target_init(struct command_context *cmd_ctx, struct target *target)
+{
+ return xtensa_target_init(cmd_ctx, target);
+}
+
+void esp_xtensa_target_deinit(struct target *target)
+{
+ LOG_DEBUG("start");
+
+ xtensa_target_deinit(target);
+ free(target_to_esp_xtensa(target)); /* same as free(xtensa) */
+}
+
+int esp_xtensa_arch_state(struct target *target)
+{
+ return ERROR_OK;
+}
+
+int esp_xtensa_poll(struct target *target)
+{
+ return xtensa_poll(target);
+}
+
+int esp_xtensa_breakpoint_add(struct target *target, struct breakpoint *breakpoint)
+{
+ return xtensa_breakpoint_add(target, breakpoint);
+ /* flash breakpoints will be handled in another patch */
+}
+
+int esp_xtensa_breakpoint_remove(struct target *target, struct breakpoint *breakpoint)
+{
+ return xtensa_breakpoint_remove(target, breakpoint);
+ /* flash breakpoints will be handled in another patch */
+}
diff --git a/src/target/espressif/esp_xtensa.h b/src/target/espressif/esp_xtensa.h
new file mode 100644
index 000000000..6badb1bd3
--- /dev/null
+++ b/src/target/espressif/esp_xtensa.h
@@ -0,0 +1,48 @@
+/***************************************************************************
+ * Generic ESP xtensa target implementation for OpenOCD *
+ * Copyright (C) 2019 Espressif Systems Ltd. *
+ * Author: Alexey Gerenkov <al...@es...> *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
+ ***************************************************************************/
+
+#ifndef OPENOCD_TARGET_ESP_XTENSA_H
+#define OPENOCD_TARGET_ESP_XTENSA_H
+
+#include <helper/command.h>
+#include <target/target.h>
+#include <target/xtensa/xtensa.h>
+
+struct esp_xtensa_common {
+ struct xtensa xtensa; /* must be the first element */
+};
+
+static inline struct esp_xtensa_common *target_to_esp_xtensa(struct target *target)
+{
+ return container_of(target->arch_info, struct esp_xtensa_common, xtensa);
+}
+
+int esp_xtensa_init_arch_info(struct target *target,
+ struct esp_xtensa_common *esp_xtensa,
+ const struct xtensa_config *xtensa_cfg,
+ struct xtensa_debug_module_config *dm_cfg);
+int esp_xtensa_target_init(struct command_context *cmd_ctx, struct target *target);
+void esp_xtensa_target_deinit(struct target *target);
+int esp_xtensa_arch_state(struct target *target);
+void esp_xtensa_queue_tdi_idle(struct target *target);
+int esp_xtensa_breakpoint_add(struct target *target, struct breakpoint *breakpoint);
+int esp_xtensa_breakpoint_remove(struct target *target, struct breakpoint *breakpoint);
+int esp_xtensa_poll(struct target *target);
+
+#endif /* OPENOCD_TARGET_ESP_XTENSA_H */
diff --git a/src/target/target.c b/src/target/target.c
index 76327b1c7..e2004e4a9 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -105,6 +105,7 @@ extern struct target_type hla_target;
extern struct target_type nds32_v2_target;
extern struct target_type nds32_v3_target;
extern struct target_type nds32_v3m_target;
+extern struct target_type esp32s2_target;
extern struct target_type or1k_target;
extern struct target_type quark_x10xx_target;
extern struct target_type quark_d20xx_target;
@@ -141,6 +142,7 @@ static struct target_type *target_types[] = {
&nds32_v2_target,
&nds32_v3_target,
&nds32_v3m_target,
+ &esp32s2_target,
&or1k_target,
&quark_x10xx_target,
&quark_d20xx_target,
diff --git a/src/target/xtensa/Makefile.am b/src/target/xtensa/Makefile.am
new file mode 100644
index 000000000..f6cee99c2
--- /dev/null
+++ b/src/target/xtensa/Makefile.am
@@ -0,0 +1,7 @@
+noinst_LTLIBRARIES += %D%/libxtensa.la
+%C%_libxtensa_la_SOURCES = \
+ %D%/xtensa.c \
+ %D%/xtensa.h \
+ %D%/xtensa_debug_module.c \
+ %D%/xtensa_debug_module.h \
+ %D%/xtensa_regs.h
diff --git a/src/target/xtensa/xtensa.c b/src/target/xtensa/xtensa.c
new file mode 100644
index 000000000..a9559600f
--- /dev/null
+++ b/src/target/xtensa/xtensa.c
@@ -0,0 +1,2731 @@
+/***************************************************************************
+ * Generic Xtensa target API for OpenOCD *
+ * Copyright (C) 2016-2019 Espressif Systems Ltd. *
+ * Derived from esp108.c *
+ * Author: Angus Gratton gu...@pr... *
+ * Author: Jeroen Domburg <je...@es...> *
+ * Author: Alexey Gerenkov <al...@es...> *
+ * Author: Andrey Gramakov <and...@es...> *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <stdlib.h>
+#include <helper/time_support.h>
+#include <helper/align.h>
+#include <target/register.h>
+
+#include "xtensa.h"
+
+
+#define _XT_INS_FORMAT_RSR(OPCODE, SR, T) ((OPCODE) \
+ | (((SR) & 0xFF) << 8) \
+ | (((T) & 0x0F) << 4))
+
+#define _XT_INS_FORMAT_RRR(OPCODE, ST, R) ((OPCODE) \
+ | (((ST) & 0xFF) << 4) \
+ | (((R) & 0x0F) << 12))
+
+#define _XT_INS_FORMAT_RRRN(OPCODE, S, T, IMM4) ((OPCODE) \
+ | (((T) & 0x0F) << 4) \
+ | (((S) & 0x0F) << 8) \
+ | (((IMM4) & 0x0F) << 12))
+
+#define _XT_INS_FORMAT_RRI8(OPCODE, R, S, T, IMM8) ((OPCODE) \
+ | (((IMM8) & 0xFF) << 16) \
+ | (((R) & 0x0F) << 12) \
+ | (((S) & 0x0F) << 8) \
+ | (((T) & 0x0F) << 4))
+
+#define _XT_INS_FORMAT_RRI4(OPCODE, IMM4, R, S, T) ((OPCODE) \
+ | (((IMM4) & 0x0F) << 20) \
+ | (((R) & 0x0F) << 12) \
+ | (((S) & 0x0F) << 8) \
+ | (((T) & 0x0F) << 4))
+
+/* Xtensa processor instruction opcodes
+ * "Return From Debug Operation" to Normal */
+#define XT_INS_RFDO 0xf1e000
+/* "Return From Debug and Dispatch" - allow sw debugging stuff to take over */
+#define XT_INS_RFDD 0xf1e010
+
+/* Load to DDR register, increase addr register */
+#define XT_INS_LDDR32P(S) (0x0070E0 | ((S) << 8))
+/* Store from DDR register, increase addr register */
+#define XT_INS_SDDR32P(S) (0x0070F0 | ((S) << 8))
+
+/* Load 32-bit Indirect from A(S) + 4 * IMM8 to A(T) */
+#define XT_INS_L32I(S, T, IMM8) _XT_INS_FORMAT_RRI8(0x002002, 0, S, T, IMM8)
+/* Load 16-bit Unsigned from A(S) + 2 * IMM8 to A(T) */
+#define XT_INS_L16UI(S, T, IMM8) _XT_INS_FORMAT_RRI8(0x001002, 0, S, T, IMM8)
+/* Load 8-bit Unsigned from A(S) + IMM8 to A(T) */
+#define XT_INS_L8UI(S, T, IMM8) _XT_INS_FORMAT_RRI8(0x000002, 0, S, T, IMM8)
+
+/* Store 32-bit Indirect to A(S) + 4 * IMM8 from A(T) */
+#define XT_INS_S32I(S, T, IMM8) _XT_INS_FORMAT_RRI8(0x006002, 0, S, T, IMM8)
+/* Store 16-bit to A(S) + 2 * IMM8 from A(T) */
+#define XT_INS_S16I(S, T, IMM8) _XT_INS_FORMAT_RRI8(0x005002, 0, S, T, IMM8)
+/* Store 8-bit to A(S) + IMM8 from A(T) */
+#define XT_INS_S8I(S, T, IMM8) _XT_INS_FORMAT_RRI8(0x004002, 0, S, T, IMM8)
+
+/* Read Special Register */
+#define XT_INS_RSR(SR, T) _XT_INS_FORMAT_RSR(0x030000, SR, T)
+/* Write Special Register */
+#define XT_INS_WSR(SR, T) _XT_INS_FORMAT_RSR(0x130000, SR, T)
+/* Swap Special Register */
+#define XT_INS_XSR(SR, T) _XT_INS_FORMAT_RSR(0x610000, SR, T)
+
+/* Rotate Window by (-8..7) */
+#define XT_INS_ROTW(N) ((0x408000) | (((N) & 15) << 4))
+
+/* Read User Register */
+#define XT_INS_RUR(UR, T) _XT_INS_FORMAT_RRR(0xE30000, UR, T)
+/* Write User Register */
+#define XT_INS_WUR(UR, T) _XT_INS_FORMAT_RSR(0xF30000, UR, T)
+
+/* Read Floating-Point Register */
+#define XT_INS_RFR(FR, T) _XT_INS_FORMAT_RRR(0xFA0000, (((FR) << 4) | 0x4), T)
+/* Write Floating-Point Register */
+#define XT_INS_WFR(FR, T) _XT_INS_FORMAT_RRR(0xFA0000, (((FR) << 4) | 0x5), T)
+
+/* 32-bit break */
+#define XT_INS_BREAK(IMM1, IMM2) _XT_INS_FORMAT_RRR(0x000000, \
+ (((IMM1) & 0x0F) << 4) | ((IMM2) & 0x0F), 0x4)
+/* 16-bit break */
+#define XT_INS_BREAKN(IMM4) _XT_INS_FORMAT_RRRN(0x00000D, IMM4, 0x2, 0xF)
+
+#define XT_INS_L32E(R, S, T) _XT_INS_FORMAT_RRI4(0x90000, 0, R, S, T)
+#define XT_INS_S32E(R, S, T) _XT_INS_FORMAT_RRI4(0x490000, 0, R, S, T)
+#define XT_INS_L32E_S32E_MASK 0xFF000F
+
+#define XT_INS_RFWO 0x3400
+#define XT_INS_RFWU 0x3500
+#define XT_INS_RFWO_RFWU_MASK 0xFFFFFF
+
+#define XT_WATCHPOINTS_NUM_MAX 2
+
+/* Special register number macro for DDR register.
+* this gets used a lot so making a shortcut to it is
+* useful.
+*/
+#define XT_SR_DDR (xtensa_regs[XT_REG_IDX_OCD_DDR].reg_num)
+
+/*Same thing for A3/A4 */
+#define XT_REG_A3 (xtensa_regs[XT_REG_IDX_AR3].reg_num)
+#define XT_REG_A4 (xtensa_regs[XT_REG_IDX_AR4].reg_num)
+
+#define XT_PC_REG_NUM_BASE (176)
+#define XT_SW_BREAKPOINTS_MAX_NUM 32
+
+const struct xtensa_reg_desc xtensa_regs[XT_NUM_REGS] = {
+ { "pc", XT_PC_REG_NUM_BASE /*+XT_DEBUGLEVEL*/, XT_REG_SPECIAL, 0 }, /* actually epc[debuglevel] */
+ { "ar0", 0x00, XT_REG_GENERAL, 0 },
+ { "ar1", 0x01, XT_REG_GENERAL, 0 },
+ { "ar2", 0x02, XT_REG_GENERAL, 0 },
+ { "ar3", 0x03, XT_REG_GENERAL, 0 },
+ { "ar4", 0x04, XT_REG_GENERAL, 0 },
+ { "ar5", 0x05, XT_REG_GENERAL, 0 },
+ { "ar6", 0x06, XT_REG_GENERAL, 0 },
+ { "ar7", 0x07, XT_REG_GENERAL, 0 },
+ { "ar8", 0x08, XT_REG_GENERAL, 0 },
+ { "ar9", 0x09, XT_REG_GENERAL, 0 },
+ { "ar10", 0x0A, XT_REG_GENERAL, 0 },
+ { "ar11", 0x0B, XT_REG_GENERAL, 0 },
+ { "ar12", 0x0C, XT_REG_GENERAL, 0 },
+ { "ar13", 0x0D, XT_REG_GENERAL, 0 },
+ { "ar14", 0x0E, XT_REG_GENERAL, 0 },
+ { "ar15", 0x0F, XT_REG_GENERAL, 0 },
+ { "ar16", 0x10, XT_REG_GENERAL, 0 },
+ { "ar17", 0x11, XT_REG_GENERAL, 0 },
+ { "ar18", 0x12, XT_REG_GENERAL, 0 },
+ { "ar19", 0x13, XT_REG_GENERAL, 0 },
+ { "ar20", 0x14, XT_REG_GENERAL, 0 },
+ { "ar21", 0x15, XT_REG_GENERAL, 0 },
+ { "ar22", 0x16, XT_REG_GENERAL, 0 },
+ { "ar23", 0x17, XT_REG_GENERAL, 0 },
+ { "ar24", 0x18, XT_REG_GENERAL, 0 },
+ { "ar25", 0x19, XT_REG_GENERAL, 0 },
+ { "ar26", 0x1A, XT_REG_GENERAL, 0 },
+ { "ar27", 0x1B, XT_REG_GENERAL, 0 },
+ { "ar28", 0x1C, XT_REG_GENERAL, 0 },
+ { "ar29", 0x1D, XT_REG_GENERAL, 0 },
+ { "ar30", 0x1E, XT_REG_GENERAL, 0 },
+ { "ar31", 0x1F, XT_REG_GENERAL, 0 },
+ { "ar32", 0x20, XT_REG_GENERAL, 0 },
+ { "ar33", 0x21, XT_REG_GENERAL, 0 },
+ { "ar34", 0x22, XT_REG_GENERAL, 0 },
+ { "ar35", 0x23, XT_REG_GENERAL, 0 },
+ { "ar36", 0x24, XT_REG_GENERAL, 0 },
+ { "ar37", 0x25, XT_REG_GENERAL, 0 },
+ { "ar38", 0x26, XT_REG_GENERAL, 0 },
+ { "ar39", 0x27, XT_REG_GENERAL, 0 },
+ { "ar40", 0x28, XT_REG_GENERAL, 0 },
+ { "ar41", 0x29, XT_REG_GENERAL, 0 },
+ { "ar42", 0x2A, XT_REG_GENERAL, 0 },
+ { "ar43", 0x2B, XT_REG_GENERAL, 0 },
+ { "ar44", 0x2C, XT_REG_GENERAL, 0 },
+ { "ar45", 0x2D, XT_REG_GENERAL, 0 },
+ { "ar46", 0x2E, XT_REG_GENERAL, 0 },
+ { "ar47", 0x2F, XT_REG_GENERAL, 0 },
+ { "ar48", 0x30, XT_REG_GENERAL, 0 },
+ { "ar49", 0x31, XT_REG_GENERAL, 0 },
+ { "ar50", 0x32, XT_REG_GENERAL, 0 },
+ { "ar51", 0x33, XT_REG_GENERAL, 0 },
+ { "ar52", 0x34, XT_REG_GENERAL, 0 },
+ { "ar53", 0x35, XT_REG_GENERAL, 0 },
+ { "ar54", 0x36, XT_REG_GENERAL, 0 },
+ { "ar55", 0x37, XT_REG_GENERAL, 0 },
+ { "ar56", 0x38, XT_REG_GENERAL, 0 },
+ { "ar57", 0x39, XT_REG_GENERAL, 0 },
+ { "ar58", 0x3A, XT_REG_GENERAL, 0 },
+ { "ar59", 0x3B, XT_REG_GENERAL, 0 },
+ { "ar60", 0x3C, XT_REG_GENERAL, 0 },
+ { "ar61", 0x3D, XT_REG_GENERAL, 0 },
+ { "ar62", 0x3E, XT_REG_GENERAL, 0 },
+ { "ar63", 0x3F, XT_REG_GENERAL, 0 },
+ { "lbeg", 0x00, XT_REG_SPECIAL, 0 },
+ { "lend", 0x01, XT_REG_SPECIAL, 0 },
+ { "lcount", 0x02, XT_REG_SPECIAL, 0 },
+ { "sar", 0x03, XT_REG_SPECIAL, 0 },
+ { "windowbase", 0x48, XT_REG_SPECIAL, 0 },
+ { "windowstart", 0x49, XT_REG_SPECIAL, 0 },
+ { "configid0", 0xB0, XT_REG_SPECIAL, 0 },
+ { "configid1", 0xD0, XT_REG_SPECIAL, 0 },
+ { "ps", 0xC6, XT_REG_SPECIAL, 0 }, /* actually EPS[debuglevel] */
+ { "threadptr", 0xE7, XT_REG_USER, 0 },
+ { "br", 0x04, XT_REG_SPECIAL, 0 },
+ { "scompare1", 0x0C, XT_REG_SPECIAL, 0 },
+ { "acclo", 0x10, XT_REG_SPECIAL, 0 },
+ { "acchi", 0x11, XT_REG_SPECIAL, 0 },
+ { "m0", 0x20, XT_REG_SPECIAL, 0 },
+ { "m1", 0x21, XT_REG_SPECIAL, 0 },
+ { "m2", 0x22, XT_REG_SPECIAL, 0 },
+ { "m3", 0x23, XT_REG_SPECIAL, 0 },
+ { "f0", 0x00, XT_REG_FR, XT_REGF_COPROC0 },
+ { "f1", 0x01, XT_REG_FR, XT_REGF_COPROC0 },
+ { "f2", 0x02, XT_REG_FR, XT_REGF_COPROC0 },
+ { "f3", 0x03, XT_REG_FR, XT_REGF_COPROC0 },
+ { "f4", 0x04, XT_REG_FR, XT_REGF_COPROC0 },
+ { "f5", 0x05, XT_REG_FR, XT_REGF_COPROC0 },
+ { "f6", 0x06, XT_REG_FR, XT_REGF_COPROC0 },
+ { "f7", 0x07, XT_REG_FR, XT_REGF_COPROC0 },
+ { "f8", 0x08, XT_REG_FR, XT_REGF_COPROC0 },
+ { "f9", 0x09, XT_REG_FR, XT_REGF_COPROC0 },
+ { "f10", 0x0A, XT_REG_FR, XT_REGF_COPROC0 },
+ { "f11", 0x0B, XT_REG_FR, XT_REGF_COPROC0 },
+ { "f12", 0x0C, XT_REG_FR, XT_REGF_COPROC0 },
+ { "f13", 0x0D, XT_REG_FR, XT_REGF_COPROC0 },
+ { "f14", 0x0E, XT_REG_FR, XT_REGF_COPROC0 },
+ { "f15", 0x0F, XT_REG_FR, XT_REGF_COPROC0 },
+ { "fcr", 0xE8, XT_REG_USER, XT_REGF_COPROC0 },
+ { "fsr", 0xE9, XT_REG_USER, XT_REGF_COPROC0 },
+ { "mmid", 0x59, XT_REG_SPECIAL, XT_REGF_NOREAD },
+ { "ibreakenable", 0x60, XT_REG_SPECIAL, 0 },
+ { "memctl", 0x61, XT_REG_SPECIAL, 0 },
+ { "atomctl", 0x63, XT_REG_SPECIAL, 0 },
+ { "ibreaka0", 0x80, XT_REG_SPECIAL, 0 },
+ { "ibreaka1", 0x81, XT_REG_SPECIAL, 0 },
+ { "dbreaka0", 0x90, XT_REG_SPECIAL, 0 },
+ { "dbreaka1", 0x91, XT_REG_SPECIAL, 0 },
+ { "dbreakc0", 0xA0, XT_REG_SPECIAL, 0 },
+ { "dbreakc1", 0xA1, XT_REG_SPECIAL, 0 },
+ { "epc1", 0xB1, XT_REG_SPECIAL, 0 },
+ { "epc2", 0xB2, XT_REG_SPECIAL, 0 },
+ { "epc3", 0xB3, XT_REG_SPECIAL, 0 },
+ { "epc4", 0xB4, XT_REG_SPECIAL, 0 },
+ { "epc5", 0xB5, XT_REG_SPECIAL, 0 },
+ { "epc6", 0xB6, XT_REG_SPECIAL, 0 },
+ { "epc7", 0xB7, XT_REG_SPECIAL, 0 },
+ { "depc", 0xC0, XT_REG_SPECIAL, 0 },
+ { "eps2", 0xC2, XT_REG_SPECIAL, 0 },
+ { "eps3", 0xC3, XT_REG_SPECIAL, 0 },
+ { "eps4", 0xC4, XT_REG_SPECIAL, 0 },
+ { "eps5", 0xC5, XT_REG_SPECIAL, 0 },
+ { "eps6", 0xC6, XT_REG_SPECIAL, 0 },
+ { "eps7", 0xC7, XT_REG_SPECIAL, 0 },
+ { "excsave1", 0xD1, XT_REG_SPECIAL, 0 },
+ { "excsave2", 0xD2, XT_REG_SPECIAL, 0 },
+ { "excsave3", 0xD3, XT_REG_SPECIAL, 0 },
+ { "excsave4", 0xD4, XT_REG_SPECIAL, 0 },
+ { "excsave5", 0xD5, XT_REG_SPECIAL, 0 },
+ { "excsave6", 0xD6, XT_REG_SPECIAL, 0 },
+ { "excsave7", 0xD7, XT_REG_SPECIAL, 0 },
+ { "cpenable", 0xE0, XT_REG_SPECIAL, 0 },
+ { "interrupt", 0xE2, XT_REG_SPECIAL, 0 },
+ { "intset", 0xE2, XT_REG_SPECIAL, XT_REGF_NOREAD },
+ { "intclear", 0xE3, XT_REG_SPECIAL, XT_REGF_NOREAD },
+ { "intenable", 0xE4, XT_REG_SPECIAL, 0 },
+ { "vecbase", 0xE7, XT_REG_SPECIAL, 0 },
+ { "exccause", 0xE8, XT_REG_SPECIAL, 0 },
+ { "debugcause", 0xE9, XT_REG_SPECIAL, 0 },
+ { "ccount", 0xEA, XT_REG_SPECIAL, 0 },
+ { "prid", 0xEB, XT_REG_SPECIAL, 0 },
+ { "icount", 0xEC, XT_REG_SPECIAL, 0 },
+ { "icountlevel", 0xED, XT_REG_SPECIAL, 0 },
+ { "excvaddr", 0xEE, XT_REG_SPECIAL, 0 },
+ { "ccompare0", 0xF0, XT_REG_SPECIAL, 0 },
+ { "ccompare1", 0xF1, XT_REG_SPECIAL, 0 },
+ { "ccompare2", 0xF2, XT_REG_SPECIAL, 0 },
+ { "misc0", 0xF4, XT_REG_SPECIAL, 0 },
+ { "misc1", 0xF5, XT_REG_SPECIAL, 0 },
+ { "misc2", 0xF6, XT_REG_SPECIAL, 0 },
+ { "misc3", 0xF7, XT_REG_SPECIAL, 0 },
+ { "litbase", 0x05, XT_REG_SPECIAL, 0 },
+ { "ptevaddr", 0x53, XT_REG_SPECIAL, 0 },
+ { "rasid", 0x5A, XT_REG_SPECIAL, 0 },
+ { "itlbcfg", 0x5B, XT_REG_SPECIAL, 0 },
+ { "dtlbcfg", 0x5C, XT_REG_SPECIAL, 0 },
+ { "mepc", 0x6A, XT_REG_SPECIAL, 0 },
+ { "meps", 0x6B, XT_REG_SPECIAL, 0 },
+ { "mesave", 0x6C, XT_REG_SPECIAL, 0 },
+ { "mesr", 0x6D, XT_REG_SPECIAL, 0 },
+ { "mecr", 0x6E, XT_REG_SPECIAL, 0 },
+ { "mevaddr", 0x6F, XT_REG_SPECIAL, 0 },
+ { "a0", XT_REG_IDX_AR0, XT_REG_RELGEN, 0 }, /* WARNING: For these registers, regnum points to the */
+ { "a1", XT_REG_IDX_AR1, XT_REG_RELGEN, 0 }, /* index of the corresponding ARxregisters, NOT to */
+ { "a2", XT_REG_IDX_AR2, XT_REG_RELGEN, 0 }, /* the processor register number! */
+ { "a3", XT_REG_IDX_AR3, XT_REG_RELGEN, 0 },
+ { "a4", XT_REG_IDX_AR4, XT_REG_RELGEN, 0 },
+ { "a5", XT_REG_IDX_AR5, XT_REG_RELGEN, 0 },
+ { "a6", XT_REG_IDX_AR6, XT_REG_RELGEN, 0 },
+ { "a7", XT_REG_IDX_AR7, XT_REG_RELGEN, 0 },
+ { "a8", XT_REG_IDX_AR8, XT_REG_RELGEN, 0 },
+ { "a9", XT_REG_IDX_AR9, XT_REG_RELGEN, 0 },
+ { "a10", XT_REG_IDX_AR10, XT_REG_RELGEN, 0 },
+ { "a11", XT_REG_IDX_AR11, XT_REG_RELGEN, 0 },
+ { "a12", XT_REG_IDX_AR12, XT_REG_RELGEN, 0 },
+ { "a13", XT_REG_IDX_AR13, XT_REG_RELGEN, 0 },
+ { "a14", XT_REG_IDX_AR14, XT_REG_RELGEN, 0 },
+ { "a15", XT_REG_IDX_AR15, XT_REG_RELGEN, 0 },
+
+ { "pwrctl", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
+ { "pwrstat", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
+ { "eristat", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
+ { "cs_itctrl", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
+ { "cs_claimset", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
+ { "cs_claimclr", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
+ { "cs_lockaccess", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
+ { "cs_lockstatus", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
+ { "cs_authstatus", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
+ { "fault_info", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
+ { "trax_id", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
+ { "trax_ctrl", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
+ { "trax_stat", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
+ { "trax_data", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
+ { "trax_addr", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
+ { "trax_pctrigger", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
+ { "trax_pcmatch", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
+ { "trax_delay", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
+ { "trax_memstart", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
+ { "trax_memend", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
+ { "pmg", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
+ { "pmoc", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
+ { "pm0", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
+ { "pm1", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
+ { "pmctrl0", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
+ { "pmctrl1", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
+ { "pmstat0", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
+ { "pmstat1", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
+ { "ocd_id", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
+ { "ocd_dcrclr", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
+ { "ocd_dcrset", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
+ { "ocd_dsr", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
+ { "ddr", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
+};
+
+
+/**
+ * Types of memory used at xtensa target
+ */
+enum xtensa_mem_region_type {
+ XTENSA_MEM_REG_IROM = 0x0,
+ XTENSA_MEM_REG_IRAM,
+ XTENSA_MEM_REG_DROM,
+ XTENSA_MEM_REG_DRAM,
+ XTENSA_MEM_REG_URAM,
+ XTENSA_MEM_REG_XLMI,
+ XTENSA_MEM_REGS_NUM
+};
+
+/**
+ * Gets a config for the specific mem type
+ */
+static inline const struct xtensa_local_mem_config *xtensa_get_mem_config(
+ struct xtensa *xtensa,
+ enum xtensa_mem_region_type type)
+{
+ switch (type) {
+ case XTENSA_MEM_REG_IROM:
+ return &xtensa->core_config->irom;
+ case XTENSA_MEM_REG_IRAM:
+ return &xtensa->core_config->iram;
+ case XTENSA_MEM_REG_DROM:
+ return &xtensa->core_config->drom;
+ case XTENSA_MEM_REG_DRAM:
+ return &xtensa->core_config->dram;
+ case XTENSA_MEM_REG_URAM:
+ return &xtensa->core_config->uram;
+ case XTENSA_MEM_REG_XLMI:
+ return &xtensa->core_config->xlmi;
+ default:
+ return NULL;
+ }
+}
+
+/**
+ * Extracts an exact xtensa_local_mem_region_config from xtensa_local_mem_config
+ * for a given address
+ * Returns NULL if nothing found
+ */
+static inline const struct xtensa_local_mem_region_config *xtensa_memory_region_find(
+ const struct xtensa_local_mem_config *mem,
+ target_addr_t address)
+{
+ for (unsigned int i = 0; i < mem->count; i++) {
+ const struct xtensa_local_mem_region_config *region = &mem->regions[i];
+ if (address >= region->base && address < (region->base + region->size))
+ return region;
+ }
+ return NULL;
+}
+
+/**
+ * Returns a corresponding xtensa_local_mem_region_config from the xtensa target
+ * for a given address
+ * Returns NULL if nothing found
+ */
+static inline const struct xtensa_local_mem_region_config *xtensa_target_memory_region_find(
+ struct xtensa *xtensa,
+ target_addr_t address)
+{
+ const struct xtensa_local_mem_region_config *result;
+ const struct xtensa_local_mem_config *mcgf;
+ for (unsigned int mtype = 0; mtype < XTENSA_MEM_REGS_NUM; mtype++) {
+ mcgf = xtensa_get_mem_config(xtensa, mtype);
+ result = xtensa_memory_region_find(mcgf, address);
+ if (result)
+ return result;
+ }
+ return NULL;
+}
+
+static int xtensa_core_reg_get(struct reg *reg)
+{
+ /*We don't need this because we read all registers on halt anyway. */
+ struct xtensa *xtensa = (struct xtensa *)reg->arch_info;
+ struct target *target = xtensa->target;
+
+ if (target->state != TARGET_HALTED)
+ return ERROR_TARGET_NOT_HALTED;
+ return ERROR_OK;
+}
+
+static int xtensa_core_reg_set(struct reg *reg, uint8_t *buf)
+{
+ struct xtensa *xtensa = (struct xtensa *)reg->arch_info;
+ struct target *target = xtensa->target;
+
+ assert(reg->size <= 64 && "up to 64-bit regs are supported only!");
+ if (target->state != TARGET_HALTED)
+ return ERROR_TARGET_NOT_HALTED;
+
+ buf_cpy(buf, reg->value, reg->size);
+ reg->dirty = true;
+ reg->valid = true;
+
+ return ERROR_OK;
+}
+
+static const struct reg_arch_...
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