[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.11.0-691-ge5f515f99

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- Log -----------------------------------------------------------------
commit e5f515f990cc345fd3089a5520f39d5a128329bd
Author: micbis <mic...@re...>
Date:   Thu May 12 15:17:49 2022 +0200

    tcl/target/renesas_rz_five: Added RZ/Five
    
    Added support for the new Renesas RISC-V
    device: RZ/Five
    
    Signed-off-by: micbis <mic...@re...>
    Change-Id: Id8ba29b83528c0bfe4f9b4ed21b0151a6e853bd7
    Reviewed-on: https://review.openocd.org/c/openocd/+/6974
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/tcl/target/renesas_rz_five.cfg b/tcl/target/renesas_rz_five.cfg
new file mode 100644
index 000000000..5ab94ab1f
--- /dev/null
+++ b/tcl/target/renesas_rz_five.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Renesas RZ/Five SoC
+#
+# General-purpose Microprocessors with RISC-V CPU Core (Andes AX45MP Single) (1.0 GHz)
+
+transport select jtag
+
+reset_config trst_and_srst srst_gates_jtag
+adapter speed 4000
+adapter srst delay 500
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME r9A07g043u
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563d
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME

commit 19e992e8827a13a9507b64b3a96895e6ed3d714a
Author: micbis <mic...@re...>
Date:   Tue May 10 10:49:31 2022 +0200

    tcl/target/renesas_rz_g2: Added RZ/G2LC and RZ/G2UL
    
    Added support for two new devices: RZ/G2LC and RZ/G2UL
    
    Change-Id: Iec6ba88c1d279f50808b060343b45c796bbfdbfc
    Signed-off-by: micbis <mic...@re...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/6972
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/target/renesas_rz_g2.cfg b/tcl/target/renesas_rz_g2.cfg
index 3615aa0e2..a3d5f48fb 100644
--- a/tcl/target/renesas_rz_g2.cfg
+++ b/tcl/target/renesas_rz_g2.cfg
@@ -6,11 +6,13 @@
 # - Each SOC can boot through the Cortex-A5x cores
 
 # Supported RZ/G2 SOCs and their cores:
-# RZ/G2H: Cortex-A57 x4, Cortex-A53 x4, Cortex-R7
-# RZ/G2M: Cortex-A57 x2, Cortex-A53 x4, Cortex-R7
-# RZ/G2N: Cortex-A57 x2,                Cortex-R7
-# RZ/G2E:                Cortex-A53 x2, Cortex-R7
-# RZ/G2L:                Cortex-A55 x2, Cortex-M33
+# RZ/G2H:   Cortex-A57 x4, Cortex-A53 x4, Cortex-R7
+# RZ/G2M:   Cortex-A57 x2, Cortex-A53 x4, Cortex-R7
+# RZ/G2N:   Cortex-A57 x2,                Cortex-R7
+# RZ/G2E:                  Cortex-A53 x2, Cortex-R7
+# RZ/G2L:                  Cortex-A55 x2, Cortex-M33
+# RZ/G2LC:                 Cortex-A55 x2, Cortex-M33
+# RZ/G2UL:                 Cortex-A55 x1, Cortex-M33
 
 # Usage:
 # There are 2 configuration options:
@@ -75,6 +77,20 @@ switch $_soc {
 		set _boot_core CA55
 		set _ap_num 0
 	}
+	G2LC {
+		set _CHIPNAME r9a07g044c
+		set _num_ca55 2
+		set _num_cm33 1
+		set _boot_core CA55
+		set _ap_num 0
+	}
+	G2UL {
+		set _CHIPNAME r9a07g043u
+		set _num_ca55 1
+		set _num_cm33 1
+		set _boot_core CA55
+		set _ap_num 0
+	}
 	default {
 		error "'$_soc' is invalid!"
 	}
@@ -169,7 +185,7 @@ if { $_boot_core == "CA57" } {
 echo "SMP targets:$smp_targets"
 eval "target smp $smp_targets"
 
-if { $_soc == "G2L"} {
+if { $_soc == "G2L" || $_soc == "G2LC" || $_soc == "G2UL" } {
 	target create $_CHIPNAME.axi_ap mem_ap -dap $_DAPNAME -ap-num 1
 }
 

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/renesas_rz_five.cfg | 22 ++++++++++++++++++++++
 tcl/target/renesas_rz_g2.cfg   | 28 ++++++++++++++++++++++------
 2 files changed, 44 insertions(+), 6 deletions(-)
 create mode 100644 tcl/target/renesas_rz_five.cfg


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