[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.11.0-687-g7d2ea186c

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- Log -----------------------------------------------------------------
commit 7d2ea186cf212c64a8e5b10725e0a2512a137fbe
Author: Tomas Vanek <va...@fb...>
Date:   Sun May 1 15:20:24 2022 +0200

    target/riscv: fix 'reset run' after 'reset halt'
    
    'reset halt' does not clear DM_DMCONTROL_HALTREQ at deassert_reset().
    If hw reset line is configured e.g. 'reset_config srst_only'
    the folowing 'reset run' halts:
    
     > gd32v.cpu curstate
     running
    
     > reset halt
     JTAG tap: gd32v.cpu tap/device found: 0x1000563d (mfg: 0x31e ...
     > gd32v.cpu curstate
     halted
    
     > reset
     JTAG tap: gd32v.cpu tap/device found: 0x1000563d (mfg: 0x31e ...
     > gd32v.cpu curstate
     halted <<<<---- wrong!!!
    
     > reset
     JTAG tap: gd32v.cpu tap/device found: 0x1000563d (mfg: 0x31e ...
     > gd32v.cpu curstate
     running
    
    Clear DM_DMCONTROL_HALTREQ when acking reset.
    
    Change-Id: Iae0454b425e81e64774b9785bb5ba1d4564d940b
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/6961
    Tested-by: jenkins
    Reviewed-by: Tim Newsome <ti...@si...>

diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c
index 2b9179d53..1b1450a7d 100644
--- a/src/target/riscv/riscv-013.c
+++ b/src/target/riscv/riscv-013.c
@@ -2397,11 +2397,11 @@ static int deassert_reset(struct target *target)
 	select_dmi(target);
 
 	/* Clear the reset, but make sure haltreq is still set */
-	uint32_t control = 0;
-	control = set_field(control, DM_DMCONTROL_HALTREQ, target->reset_halt ? 1 : 0);
+	uint32_t control = 0, control_haltreq;
 	control = set_field(control, DM_DMCONTROL_DMACTIVE, 1);
+	control_haltreq = set_field(control, DM_DMCONTROL_HALTREQ, target->reset_halt ? 1 : 0);
 	dmi_write(target, DM_DMCONTROL,
-			set_hartsel(control, r->current_hartid));
+			set_hartsel(control_haltreq, r->current_hartid));
 
 	uint32_t dmstatus;
 	int dmi_busy_delay = info->dmi_busy_delay;
@@ -2413,7 +2413,7 @@ static int deassert_reset(struct target *target)
 			if (index != target->coreid)
 				continue;
 			dmi_write(target, DM_DMCONTROL,
-					set_hartsel(control, index));
+					set_hartsel(control_haltreq, index));
 		} else {
 			index = r->current_hartid;
 		}
@@ -2449,7 +2449,7 @@ static int deassert_reset(struct target *target)
 		target->state = TARGET_HALTED;
 
 		if (get_field(dmstatus, DM_DMSTATUS_ALLHAVERESET)) {
-			/* Ack reset. */
+			/* Ack reset and clear DM_DMCONTROL_HALTREQ if previously set */
 			dmi_write(target, DM_DMCONTROL,
 					set_hartsel(control, index) |
 					DM_DMCONTROL_ACKHAVERESET);

-----------------------------------------------------------------------

Summary of changes:
 src/target/riscv/riscv-013.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)


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