[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.11.0-600-g4ea21b95f

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- Log -----------------------------------------------------------------
commit 4ea21b95f9562ae13ef200461180bc72bbad8926
Author: Nishanth Menon <nm...@ti...>
Date:   Tue Mar 1 09:09:55 2022 -0600

    tcl/target/ti_k3: Add a gdb-attach event hook for armv8 and simplify startup function
    
    Since we can detect the type of target as well, reuse the _cpu_no_smp_up
    function name and use the target name to simplify the _up function and
    maintain consistency with what we introduced for r5.
    
    Lets introduce gdb-attach event in a much cleaner fashion.
    
    NOTE: we add a halt 1000 to retain the default gdb-attach hook behavior
    
    While at it, fix a minor type of s/are/as in "Set Default target are
    core 0" and simplify the foreach usage.
    
    Signed-off-by: Nishanth Menon <nm...@ti...>
    Change-Id: I3259b7c3ae4c71b06d921edfaefe17c03bb673dc
    Reviewed-on: https://review.openocd.org/c/openocd/+/6616
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index 883197b14..f2267ca12 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -154,6 +154,16 @@ proc _cpu_no_smp_up {} {
 	$_current_target $_current_type dbginit
 }
 
+proc _armv8_smp_up {} {
+	for { set _core 0 } { $_core < $::_armv8_cores } { incr _core } {
+		$::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
+		$::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
+		$::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 smp on
+	}
+	# Set Default target as core 0
+	targets $::_TARGETNAME.$::_armv8_cpu_name.0
+}
+
 set _v8_smp_targets ""
 
 for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
@@ -165,6 +175,20 @@ for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
 		-dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine
 
 	set _v8_smp_targets "$_v8_smp_targets $_TARGETNAME.$_armv8_cpu_name.$_core"
+
+	if { $_v8_smp_debug == 0 } {
+		$_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
+			_cpu_no_smp_up
+			# gdb-attach default rule
+			halt 1000
+		}
+	} else {
+		$_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
+			_armv8_smp_up
+			# gdb-attach default rule
+			halt 1000
+		}
+	}
 }
 
 # Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs
@@ -174,22 +198,15 @@ set _armv8_smp_cmd "$_armv8_cpu_name"_smp
 
 if { $_v8_smp_debug == 0 } {
 	proc $_armv8_up_cmd { args } {
-		foreach { _core } [set args] {
-			$::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
-			$::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
+		foreach _core $args {
+			targets $_core
+			_cpu_no_smp_up
 		}
 	}
 } else {
 	proc $_armv8_smp_cmd { args } {
-		for { set _core 0 } { $_core < $::_armv8_cores } { incr _core } {
-			$::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
-			$::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
-			$::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 smp on
-		}
-		# Set Default target are core 0
-		targets $::_TARGETNAME.$::_armv8_cpu_name.0
+		_armv8_smp_up
 	}
-
 	# Declare SMP
 	target smp $:::_v8_smp_targets
 }

commit 3ba2b515b528094b43d5be5056b9e52f1dc33969
Author: Nishanth Menon <nm...@ti...>
Date:   Mon Oct 4 09:20:34 2021 -0500

    tcl/target/ti_k3: Add a gdb-attach event hook for r5 and simplify startup function
    
    Since we can detect the type of target as well, make the attach
    function name generic for the follow on cleanup patch on armv8 to use
    as well.
    
    Lets introduce gdb-attach event in a much cleaner fashion. We can
    introduce a simpler r5_up function since we now have more descriptive
    core names making the individual descriptive procs redundant.
    
    NOTE: we add a halt 1000 to retain the default gdb-attach hook behavior
    
    Signed-off-by: Nishanth Menon <nm...@ti...>
    Change-Id: I31506bb2b86e63638082640eb72aa7c4c9575e93
    Reviewed-on: https://review.openocd.org/c/openocd/+/6617
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index 6c2c2e1da..883197b14 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -64,9 +64,6 @@ switch $_soc {
 
 		# AM654 has 1 cluster of 2 R5s cores.
 		set _r5_cores 2
-		set _mcu_r5_cores 2
-		set _main0_r5_cores 0
-		set _main1_r5_cores 0
 		set R5_NAMES {mcu_r5.0 mcu_r5.1}
 
 		# Sysctrl power-ap unlock offsets
@@ -84,9 +81,6 @@ switch $_soc {
 
 		# AM642 has 2 cluster of 2 R5s cores.
 		set _r5_cores 4
-		set _mcu_r5_cores 0
-		set _main0_r5_cores 2
-		set _main1_r5_cores 2
 		set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
 		set R5_DBGBASE {0x9d410000 0x9d412000 0x9d510000 0x9d512000}
 		set R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000}
@@ -103,9 +97,6 @@ switch $_soc {
 
 		# J721E has 3 clusters of 2 R5 cores each.
 		set _r5_cores 6
-		set _mcu_r5_cores 2
-		set _main0_r5_cores 2
-		set _main1_r5_cores 2
 	}
 	j7200 {
 		set _CHIPNAME j7200
@@ -117,9 +108,6 @@ switch $_soc {
 
 		# J7200 has 2 clusters of 2 R5 cores each.
 		set _r5_cores 4
-		set _mcu_r5_cores 2
-		set _main0_r5_cores 2
-		set _main1_r5_cores 0
 		set R5_DBGBASE {0x9d010000 0x9d012000 0x9d110000 0x9d112000}
 		set R5_CTIBASE {0x9d018000 0x9d019000 0x9d118000 0x9d119000}
 
@@ -158,6 +146,14 @@ $_TARGETNAME.sysctrl configure -event gdb-attach {
 	halt 1000
 }
 
+proc _cpu_no_smp_up {} {
+	set _current_target [target current]
+	set _current_type [$_current_target cget -type]
+
+	$_current_target arp_examine
+	$_current_target $_current_type dbginit
+}
+
 set _v8_smp_targets ""
 
 for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
@@ -206,32 +202,18 @@ for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
 	# inactive core examination will fail - wait till startup of additional core
 	target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \
 		-dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine
-}
 
-if { $_mcu_r5_cores != 0 } {
-	proc mcu_r5_up { args } {
-		foreach { _core } [set args] {
-			$::_TARGETNAME.mcu_r5.$_core arp_examine
-			$::_TARGETNAME.mcu_r5.$_core cortex_r4 dbginit
-		}
-	}
-}
-
-if { $_main0_r5_cores != 0 } {
-	proc main0_r5_up { args } {
-		foreach { _core } [set args] {
-			$::_TARGETNAME.main0_r5.$_core arp_examine
-			$::_TARGETNAME.main0_r5.$_core cortex_r4 dbginit
-		}
+	$_TARGETNAME.$_r5_name configure -event gdb-attach {
+		_cpu_no_smp_up
+		# gdb-attach default rule
+		halt 1000
 	}
 }
 
-if { $_main1_r5_cores != 0 } {
-	proc main1_r5_up { args } {
-		foreach { _core } [set args] {
-			$::_TARGETNAME.main1_r5.$_core arp_examine
-			$::_TARGETNAME.main1_r5.$_core cortex_r4 dbginit
-		}
+proc r5_up { args } {
+	foreach  _core $args {
+		targets $_core
+		_cpu_no_smp_up
 	}
 }
 

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/ti_k3.cfg | 89 ++++++++++++++++++++++++++--------------------------
 1 file changed, 44 insertions(+), 45 deletions(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.11.0-600-g4ea21b95f