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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.11.0-598-g4b12c9e8c
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From: OpenOCD-Gerrit <ope...@us...> - 2022-03-12 09:40:59
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- Log -----------------------------------------------------------------
commit 4b12c9e8c507a1ba748de32c9ab9f3e7654c22b4
Author: Nishanth Menon <nm...@ti...>
Date: Mon Oct 4 09:03:49 2021 -0500
tcl/target/ti_k3: Rename R5 targets to be more descriptive
R5 targets are currently named r5.0..n and the only way for user to
determine the actual type is external documentation. Lets just rename
the target names to make them descriptive to not require external
documentation for finding which R5 to connect to.
NOTE: we leave the _mcu_r5_cores _main0_r5_cores _main1_r5_cores alone
for now to allow existing startup proc functions to work, but we will
drop it in the follow on patch.
Previously:
Info : starting gdb server for j721e.cpu.r5.0 on 3336
Info : Listening on port 3336 for gdb connections
Info : starting gdb server for j721e.cpu.r5.1 on 3337
Info : Listening on port 3337 for gdb connections
Info : starting gdb server for j721e.cpu.r5.2 on 3338
Info : Listening on port 3338 for gdb connections
Info : starting gdb server for j721e.cpu.r5.3 on 3339
Info : Listening on port 3339 for gdb connections
Info : starting gdb server for j721e.cpu.r5.4 on 3340
Info : Listening on port 3340 for gdb connections
Info : starting gdb server for j721e.cpu.r5.5 on 3341
Info : Listening on port 3341 for gdb connections
With this patch:
Info : starting gdb server for j721e.cpu.mcu_r5.0 on 3336
Info : Listening on port 3336 for gdb connections
Info : starting gdb server for j721e.cpu.mcu_r5.1 on 3337
Info : Listening on port 3337 for gdb connections
Info : starting gdb server for j721e.cpu.main0_r5.0 on 3338
Info : Listening on port 3338 for gdb connections
Info : starting gdb server for j721e.cpu.main0_r5.1 on 3339
Info : Listening on port 3339 for gdb connections
Info : starting gdb server for j721e.cpu.main1_r5.0 on 3340
Info : Listening on port 3340 for gdb connections
Info : starting gdb server for j721e.cpu.main1_r5.1 on 3341
Info : Listening on port 3341 for gdb connections
Signed-off-by: Nishanth Menon <nm...@ti...>
Change-Id: I2989efe3ae3e16754f98fa1dc9363ec4c898f7c3
Reviewed-on: https://review.openocd.org/c/openocd/+/6627
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index e397d2255..6c2c2e1da 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -42,6 +42,7 @@ set ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000}
# (0)MCU 0 (1)MCU 1 (2)MAIN_0_0 (3)MAIN_0_1 (4)MAIN_1_0 (5)MAIN_1_1
set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000}
set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000}
+set R5_NAMES {mcu_r5.0 mcu_r5.1 main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
# Finally an General Purpose(GP) MCU
set CM4_CTIBASE {0x20001000}
@@ -64,11 +65,9 @@ switch $_soc {
# AM654 has 1 cluster of 2 R5s cores.
set _r5_cores 2
set _mcu_r5_cores 2
- set _mcu_base_core_id 0
set _main0_r5_cores 0
- set _main0_base_core_id 0
set _main1_r5_cores 0
- set _main1_base_core_id 0
+ set R5_NAMES {mcu_r5.0 mcu_r5.1}
# Sysctrl power-ap unlock offsets
set _sysctrl_ap_unlock_offsets {0xf0 0x50}
@@ -86,11 +85,9 @@ switch $_soc {
# AM642 has 2 cluster of 2 R5s cores.
set _r5_cores 4
set _mcu_r5_cores 0
- set _mcu_base_core_id 0
set _main0_r5_cores 2
- set _main0_base_core_id 0
set _main1_r5_cores 2
- set _main1_base_core_id 2
+ set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
set R5_DBGBASE {0x9d410000 0x9d412000 0x9d510000 0x9d512000}
set R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000}
@@ -107,11 +104,8 @@ switch $_soc {
# J721E has 3 clusters of 2 R5 cores each.
set _r5_cores 6
set _mcu_r5_cores 2
- set _mcu_base_core_id 0
set _main0_r5_cores 2
- set _main0_base_core_id 2
set _main1_r5_cores 2
- set _main1_base_core_id 4
}
j7200 {
set _CHIPNAME j7200
@@ -124,11 +118,8 @@ switch $_soc {
# J7200 has 2 clusters of 2 R5 cores each.
set _r5_cores 4
set _mcu_r5_cores 2
- set _mcu_base_core_id 0
set _main0_r5_cores 2
- set _main0_base_core_id 2
set _main1_r5_cores 0
- set _main1_base_core_id 0
set R5_DBGBASE {0x9d010000 0x9d012000 0x9d110000 0x9d112000}
set R5_CTIBASE {0x9d018000 0x9d019000 0x9d118000 0x9d119000}
@@ -208,20 +199,20 @@ if { $_v8_smp_debug == 0 } {
}
for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
- cti create $_CTINAME.r5.$_core -dap $_CHIPNAME.dap -ap-num 1 \
+ set _r5_name [lindex $R5_NAMES $_core]
+ cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num 1 \
-baseaddr [lindex $R5_CTIBASE $_core]
# inactive core examination will fail - wait till startup of additional core
- target create $_TARGETNAME.r5.$_core cortex_r4 -dap $_CHIPNAME.dap \
+ target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \
-dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine
}
if { $_mcu_r5_cores != 0 } {
proc mcu_r5_up { args } {
foreach { _core } [set args] {
- set _core [expr {$_core + $::_mcu_base_core_id}]
- $::_TARGETNAME.r5.$_core arp_examine
- $::_TARGETNAME.r5.$_core cortex_r4 dbginit
+ $::_TARGETNAME.mcu_r5.$_core arp_examine
+ $::_TARGETNAME.mcu_r5.$_core cortex_r4 dbginit
}
}
}
@@ -229,9 +220,8 @@ if { $_mcu_r5_cores != 0 } {
if { $_main0_r5_cores != 0 } {
proc main0_r5_up { args } {
foreach { _core } [set args] {
- set _core [expr {$_core + $::_main0_base_core_id}]
- $::_TARGETNAME.r5.$_core arp_examine
- $::_TARGETNAME.r5.$_core cortex_r4 dbginit
+ $::_TARGETNAME.main0_r5.$_core arp_examine
+ $::_TARGETNAME.main0_r5.$_core cortex_r4 dbginit
}
}
}
@@ -239,9 +229,8 @@ if { $_main0_r5_cores != 0 } {
if { $_main1_r5_cores != 0 } {
proc main1_r5_up { args } {
foreach { _core } [set args] {
- set _core [expr {$_core + $::_main1_base_core_id}]
- $::_TARGETNAME.r5.$_core arp_examine
- $::_TARGETNAME.r5.$_core cortex_r4 dbginit
+ $::_TARGETNAME.main1_r5.$_core arp_examine
+ $::_TARGETNAME.main1_r5.$_core cortex_r4 dbginit
}
}
}
commit 4ddca7dd7186a908397570a25f7ad7454bab3a20
Author: Nishanth Menon <nm...@ti...>
Date: Fri Oct 1 23:18:09 2021 -0500
tcl/target/ti_k3: Rename m4 target as general purpose mcu
The MCU is present on few of the SoCs and is meant as General Purpose
(GP) MCU of the system. Lets rename it to make clear what we are
debugging - esp when multiple MCUs are present in the system.
Signed-off-by: Nishanth Menon <nm...@ti...>
Change-Id: I16132d321daf6e9b1d893fe6f92026d5aa9eb152
Reviewed-on: https://review.openocd.org/c/openocd/+/6619
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index ee4a5c8b3..e397d2255 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -43,13 +43,13 @@ set ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000}
set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000}
set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000}
-# Finally an M4F
+# Finally an General Purpose(GP) MCU
set CM4_CTIBASE {0x20001000}
-# M4 may be present on some very few SoCs
-set _mcu_m4_cores 0
-# M4 power-ap unlock offsets
-set _m4_ap_unlock_offsets {0xf0 0x60}
+# General Purpose MCU (M4) may be present on some very few SoCs
+set _gp_mcu_cores 0
+# General Purpose MCU power-ap unlock offsets
+set _gp_mcu_ap_unlock_offsets {0xf0 0x60}
# Set configuration overrides for each SOC
switch $_soc {
@@ -95,7 +95,7 @@ switch $_soc {
set R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000}
# M4 processor
- set _mcu_m4_cores 1
+ set _gp_mcu_cores 1
}
j721e {
set _CHIPNAME j721e
@@ -246,22 +246,22 @@ if { $_main1_r5_cores != 0 } {
}
}
-if { $_mcu_m4_cores != 0 } {
- cti create $_CTINAME.m4 -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0]
- target create $_TARGETNAME.m4 cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine
- $_TARGETNAME.m4 configure -event reset-assert { }
+if { $_gp_mcu_cores != 0 } {
+ cti create $_CTINAME.gp_mcu -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0]
+ target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine
+ $_TARGETNAME.gp_mcu configure -event reset-assert { }
- proc m4_up {} {
- # To access M4, we need to enable the JTAG access for the same.
+ proc gp_mcu_up {} {
+ # To access GP MCU, we need to enable the JTAG access for the same.
# Ensure Power-AP unlocked
- $::_CHIPNAME.dap apreg 3 [lindex $::_m4_ap_unlock_offsets 0] 0x00190000
- $::_CHIPNAME.dap apreg 3 [lindex $::_m4_ap_unlock_offsets 1] 0x00102098
+ $::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 0] 0x00190000
+ $::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 1] 0x00102098
- $::_TARGETNAME.m4 arp_examine
+ $::_TARGETNAME.gp_mcu arp_examine
}
- $_TARGETNAME.m4 configure -event gdb-attach {
- m4_up
+ $_TARGETNAME.gp_mcu configure -event gdb-attach {
+ gp_mcu_up
# gdb-attach default rule
halt 1000
}
-----------------------------------------------------------------------
Summary of changes:
tcl/target/ti_k3.cfg | 69 ++++++++++++++++++++++------------------------------
1 file changed, 29 insertions(+), 40 deletions(-)
hooks/post-receive
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Main OpenOCD repository
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