[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.11.0-596-g77b02b89a

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- Log -----------------------------------------------------------------
commit 77b02b89ae689867bb38e11d3fa6ff59c8d22357
Author: Nishanth Menon <nm...@ti...>
Date:   Fri Oct 1 23:02:23 2021 -0500

    tcl/target/ti_k3: Rename m3 target as sysctrl
    
    The M3 is the system controller of the system. Lets rename it to make
    clear what we are debugging - esp when multiple MCUs are present in the
    system.
    
    Signed-off-by: Nishanth Menon <nm...@ti...>
    Change-Id: I4cd03b6068b8ce140fd254f9dd88151c4c7006d7
    Reviewed-on: https://review.openocd.org/c/openocd/+/6618
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index 8fb71482c..ee4a5c8b3 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -27,11 +27,11 @@ if { [info exists V8_SMP_DEBUG] } {
 
 # Common Definitions
 
-# CM3 the very first processor - all current SoCs have it.
+# System Controller is the very first processor - all current SoCs have it.
 set CM3_CTIBASE		{0x3C016000}
 
-# M3 power-ap unlock offsets
-set _m3_ap_unlock_offsets {0xf0 0x44}
+# sysctrl power-ap unlock offsets
+set _sysctrl_ap_unlock_offsets {0xf0 0x44}
 
 # All the ARMV8s are the next processors.
 #		   CL0,CORE0  CL0,CORE1  CL1,CORE0  CL1,CORE1
@@ -70,8 +70,8 @@ switch $_soc {
 		set _main1_r5_cores 0
 		set _main1_base_core_id 0
 
-		# M3 power-ap unlock offsets
-		set _m3_ap_unlock_offsets {0xf0 0x50}
+		# Sysctrl power-ap unlock offsets
+		set _sysctrl_ap_unlock_offsets {0xf0 0x50}
 	}
 	am642 {
 		set _CHIPNAME am642
@@ -147,22 +147,22 @@ set _TARGETNAME $_CHIPNAME.cpu
 
 set _CTINAME $_CHIPNAME.cti
 
-# M3 is always present
-cti create $_CTINAME.m3 -dap $_CHIPNAME.dap -ap-num 7 -baseaddr [lindex $CM3_CTIBASE 0]
-target create $_TARGETNAME.m3 cortex_m -dap $_CHIPNAME.dap -ap-num 7 -defer-examine
-$_TARGETNAME.m3 configure -event reset-assert { }
+# sysctrl is always present
+cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap -ap-num 7 -baseaddr [lindex $CM3_CTIBASE 0]
+target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap -ap-num 7 -defer-examine
+$_TARGETNAME.sysctrl configure -event reset-assert { }
 
-proc m3_up {} {
-	# To access M3, we need to enable the JTAG access for the same.
+proc sysctrl_up {} {
+	# To access sysctrl, we need to enable the JTAG access for the same.
 	# Ensure Power-AP unlocked
-	$::_CHIPNAME.dap apreg 3 [lindex $::_m3_ap_unlock_offsets 0] 0x00190000
-	$::_CHIPNAME.dap apreg 3 [lindex $::_m3_ap_unlock_offsets 1] 0x00102098
+	$::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 0] 0x00190000
+	$::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 1] 0x00102098
 
-	$::_TARGETNAME.m3 arp_examine
+	$::_TARGETNAME.sysctrl arp_examine
 }
 
-$_TARGETNAME.m3 configure -event gdb-attach {
-	m3_up
+$_TARGETNAME.sysctrl configure -event gdb-attach {
+	sysctrl_up
 	# gdb-attach default rule
 	halt 1000
 }

commit c280c9835705a7d104996569068826a73b665010
Author: Nishanth Menon <nm...@ti...>
Date:   Fri Oct 1 22:48:34 2021 -0500

    tcl/target/ti_k3: Add a gdb-attach event hook for m3 and m4
    
    Add gdb-attach event to call the "up" function of m3 and m4 allowing for
    more seamless integration with gdb for end users. We still retain _up
    functions for non-gdb functionality.
    
    NOTE: we add a halt 1000 to retain the default gdb-attach hook behavior
    
    Suggested-by: Antonio Borneo <bor...@gm...>
    Signed-off-by: Nishanth Menon <nm...@ti...>
    Change-Id: I2e51fdbd8756f156551e589c748c3a338afa655c
    Reviewed-on: https://review.openocd.org/c/openocd/+/6615
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index 325ee0004..8fb71482c 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -161,6 +161,12 @@ proc m3_up {} {
 	$::_TARGETNAME.m3 arp_examine
 }
 
+$_TARGETNAME.m3 configure -event gdb-attach {
+	m3_up
+	# gdb-attach default rule
+	halt 1000
+}
+
 set _v8_smp_targets ""
 
 for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
@@ -253,4 +259,10 @@ if { $_mcu_m4_cores != 0 } {
 
 		$::_TARGETNAME.m4 arp_examine
 	}
+
+	$_TARGETNAME.m4 configure -event gdb-attach {
+		m4_up
+		# gdb-attach default rule
+		halt 1000
+	}
 }

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/ti_k3.cfg | 40 ++++++++++++++++++++++++++--------------
 1 file changed, 26 insertions(+), 14 deletions(-)


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