From: OpenOCD-Gerrit <ope...@us...> - 2021-07-24 09:40:17
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This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via ae6de2f93d960c7d35e8d4c86d9c17dda17c561e (commit) via e2ef1c9090ad01e78aa537418ca3f543e4c1282b (commit) from c0c7d6fe8b04f521a7262303083ef5eb6ebaf4e5 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit ae6de2f93d960c7d35e8d4c86d9c17dda17c561e Author: Florian Fainelli <f.f...@gm...> Date: Tue Jul 6 11:21:54 2021 -0700 arm_adi_v5: Added Cortex-A76 identifiers Add identifiers of the Cortex-A76 ROM and debug unit. Change-Id: Ieef0d990189d3c0502e8d530874dc9cbca4417d8 Signed-off-by: Florian Fainelli <f.f...@gm...> Reviewed-on: http://openocd.zylin.com/6358 Tested-by: jenkins Reviewed-by: Antonio Borneo <bor...@gm...> diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index 16fe69a8d..c421fe6a3 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -1138,6 +1138,7 @@ static const struct { { ARM_ID, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", }, { ARM_ID, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", }, { ARM_ID, 0x4e0, "Cortex-A35 ROM", "(v7 Memory Map ROM Table)", }, + { ARM_ID, 0x4e4, "Cortex-A76 ROM", "(ROM Table)", }, { ARM_ID, 0x906, "CoreSight CTI", "(Cross Trigger)", }, { ARM_ID, 0x907, "CoreSight ETB", "(Trace Buffer)", }, { ARM_ID, 0x908, "CoreSight CSTF", "(Trace Funnel)", }, @@ -1194,6 +1195,7 @@ static const struct { { ARM_ID, 0xd04, "Cortex-A35 Debug", "(Debug Unit)", }, { ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", }, { ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", }, + { ARM_ID, 0xd0b, "Cortex-A76 Debug", "(Debug Unit)", }, { 0x097, 0x9af, "MSP432 ROM", "(ROM Table)" }, { 0x09f, 0xcd0, "Atmel CPU with DSU", "(CPU)" }, { 0x0c1, 0x1db, "XMC4500 ROM", "(ROM Table)" }, commit e2ef1c9090ad01e78aa537418ca3f543e4c1282b Author: Florian Fainelli <f.f...@gm...> Date: Fri Jul 9 11:04:27 2021 -0700 arm_adi_v5: Provide Brahma-B53 identifiers The Broadcom Brahma-B53 CPUs contains a number of custom ROM table entries for its PMU, Debug unit, and a couple of ROM tables. Change-Id: I1f21f07ed296579c374f24e781325789bf4ebf51 Signed-off-by: Florian Fainelli <f.f...@gm...> Reviewed-on: http://openocd.zylin.com/6368 Tested-by: jenkins Reviewed-by: Antonio Borneo <bor...@gm...> diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index dc6f63d46..16fe69a8d 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -1201,6 +1201,10 @@ static const struct { { 0x0c1, 0x1ed, "XMC1000 ROM", "(ROM Table)" }, { 0x0E5, 0x000, "SHARC+/Blackfin+", "", }, { 0x0F0, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", }, + { 0x1bf, 0x100, "Brahma-B53 Debug", "(Debug Unit)", }, + { 0x1bf, 0x9d3, "Brahma-B53 PMU", "(Performance Monitor Unit)", }, + { 0x1bf, 0x4a1, "Brahma-B53 ROM", "(ROM Table)", }, + { 0x1bf, 0x721, "Brahma-B53 ROM", "(ROM Table)", }, { 0x3eb, 0x181, "Tegra 186 ROM", "(ROM Table)", }, { 0x3eb, 0x202, "Denver ETM", "(Denver Embedded Trace)", }, { 0x3eb, 0x211, "Tegra 210 ROM", "(ROM Table)", }, ----------------------------------------------------------------------- Summary of changes: src/target/arm_adi_v5.c | 6 ++++++ 1 file changed, 6 insertions(+) hooks/post-receive -- Main OpenOCD repository |