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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.11.0-274-g20b29b776
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From: OpenOCD-Gerrit <ope...@us...> - 2021-07-20 13:57:10
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- Log -----------------------------------------------------------------
commit 20b29b7767097f999fe2eb4f7fb6c2917e9f66a6
Author: Antonio Borneo <bor...@gm...>
Date: Sat Jul 3 18:18:57 2021 +0200
openocd: manually fix Yoda conditions
Fix the remaining Yoda conditions, detected by checkpatch but not
fixed automatically.
While there, apply minor style changes.
Change-Id: I6e1978b89c4d56a20aceaeb2b52968eb6384432a
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/6356
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <li...@re...>
Reviewed-by: Xiang W <wx...@12...>
diff --git a/src/flash/nand/at91sam9.c b/src/flash/nand/at91sam9.c
index 4341935fe..c8886d17a 100644
--- a/src/flash/nand/at91sam9.c
+++ b/src/flash/nand/at91sam9.c
@@ -383,7 +383,7 @@ static int at91sam9_read_page(struct nand_device *nand, uint32_t page,
oob_data = at91sam9_oob_init(nand, oob, &oob_size);
retval = nand_read_data_page(nand, oob_data, oob_size);
- if (ERROR_OK == retval && data) {
+ if (retval == ERROR_OK && data) {
target_read_u32(target, info->ecc + AT91C_ECCX_SR, &status);
if (status & 1) {
LOG_ERROR("Error detected!");
diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c
index 15ca29628..4a7c1cdab 100644
--- a/src/flash/nor/at91sam3.c
+++ b/src/flash/nor/at91sam3.c
@@ -3626,7 +3626,7 @@ COMMAND_HANDLER(sam3_handle_gpnvm_command)
who = -1;
break;
case 2:
- if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all")))
+ if ((strcmp(CMD_ARGV[0], "show") == 0) && (strcmp(CMD_ARGV[1], "all") == 0))
who = -1;
else {
uint32_t v32;
@@ -3636,7 +3636,7 @@ COMMAND_HANDLER(sam3_handle_gpnvm_command)
break;
}
- if (0 == strcmp("show", CMD_ARGV[0])) {
+ if (strcmp("show", CMD_ARGV[0]) == 0) {
if (who == -1) {
showall:
r = ERROR_OK;
@@ -3664,10 +3664,10 @@ showall:
return ERROR_COMMAND_SYNTAX_ERROR;
}
- if (0 == strcmp("set", CMD_ARGV[0]))
+ if (strcmp("set", CMD_ARGV[0]) == 0)
r = flashd_set_gpnvm(&(chip->details.bank[0]), who);
- else if ((0 == strcmp("clr", CMD_ARGV[0])) ||
- (0 == strcmp("clear", CMD_ARGV[0]))) /* quietly accept both */
+ else if ((strcmp("clr", CMD_ARGV[0]) == 0) ||
+ (strcmp("clear", CMD_ARGV[0]) == 0)) /* quietly accept both */
r = flashd_clr_gpnvm(&(chip->details.bank[0]), who);
else {
command_print(CMD, "Unknown command: %s", CMD_ARGV[0]);
diff --git a/src/flash/nor/at91sam4.c b/src/flash/nor/at91sam4.c
index b45cf071d..958ec5ec0 100644
--- a/src/flash/nor/at91sam4.c
+++ b/src/flash/nor/at91sam4.c
@@ -3173,7 +3173,7 @@ COMMAND_HANDLER(sam4_handle_gpnvm_command)
who = -1;
break;
case 2:
- if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all")))
+ if ((strcmp(CMD_ARGV[0], "show") == 0) && (strcmp(CMD_ARGV[1], "all") == 0))
who = -1;
else {
uint32_t v32;
@@ -3183,7 +3183,7 @@ COMMAND_HANDLER(sam4_handle_gpnvm_command)
break;
}
- if (0 == strcmp("show", CMD_ARGV[0])) {
+ if (strcmp("show", CMD_ARGV[0]) == 0) {
if (who == -1) {
showall:
r = ERROR_OK;
@@ -3211,10 +3211,10 @@ showall:
return ERROR_COMMAND_SYNTAX_ERROR;
}
- if (0 == strcmp("set", CMD_ARGV[0]))
+ if (strcmp("set", CMD_ARGV[0]) == 0)
r = flashd_set_gpnvm(&(chip->details.bank[0]), who);
- else if ((0 == strcmp("clr", CMD_ARGV[0])) ||
- (0 == strcmp("clear", CMD_ARGV[0]))) /* quietly accept both */
+ else if ((strcmp("clr", CMD_ARGV[0]) == 0) ||
+ (strcmp("clear", CMD_ARGV[0]) == 0)) /* quietly accept both */
r = flashd_clr_gpnvm(&(chip->details.bank[0]), who);
else {
command_print(CMD, "Unknown command: %s", CMD_ARGV[0]);
diff --git a/src/flash/nor/max32xxx.c b/src/flash/nor/max32xxx.c
index a1bb668eb..1327da6e1 100644
--- a/src/flash/nor/max32xxx.c
+++ b/src/flash/nor/max32xxx.c
@@ -801,7 +801,7 @@ COMMAND_HANDLER(max32xxx_handle_protection_set_command)
info = bank->driver_priv;
/* Convert the range to the page numbers */
- if (1 != sscanf(CMD_ARGV[1], "0x%"SCNx32, &addr)) {
+ if (sscanf(CMD_ARGV[1], "0x%"SCNx32, &addr) != 1) {
LOG_WARNING("Error parsing address");
command_print(CMD, "max32xxx protection_set <bank> <addr> <size>");
return ERROR_FAIL;
@@ -809,7 +809,7 @@ COMMAND_HANDLER(max32xxx_handle_protection_set_command)
/* Mask off the top portion on the address */
addr = (addr & 0x0FFFFFFF);
- if (1 != sscanf(CMD_ARGV[2], "0x%"SCNx32, &len)) {
+ if (sscanf(CMD_ARGV[2], "0x%"SCNx32, &len) != 1) {
LOG_WARNING("Error parsing length");
command_print(CMD, "max32xxx protection_set <bank> <addr> <size>");
return ERROR_FAIL;
@@ -857,7 +857,7 @@ COMMAND_HANDLER(max32xxx_handle_protection_clr_command)
info = bank->driver_priv;
/* Convert the range to the page numbers */
- if (1 != sscanf(CMD_ARGV[1], "0x%"SCNx32, &addr)) {
+ if (sscanf(CMD_ARGV[1], "0x%"SCNx32, &addr) != 1) {
LOG_WARNING("Error parsing address");
command_print(CMD, "max32xxx protection_clr <bank> <addr> <size>");
return ERROR_FAIL;
@@ -865,7 +865,7 @@ COMMAND_HANDLER(max32xxx_handle_protection_clr_command)
/* Mask off the top portion on the address */
addr = (addr & 0x0FFFFFFF);
- if (1 != sscanf(CMD_ARGV[2], "0x%"SCNx32, &len)) {
+ if (sscanf(CMD_ARGV[2], "0x%"SCNx32, &len) != 1) {
LOG_WARNING("Error parsing length");
command_print(CMD, "max32xxx protection_clr <bank> <addr> <size>");
return ERROR_FAIL;
diff --git a/src/flash/nor/msp432.c b/src/flash/nor/msp432.c
index b418bf152..81c94b6db 100644
--- a/src/flash/nor/msp432.c
+++ b/src/flash/nor/msp432.c
@@ -315,8 +315,8 @@ static int msp432_init(struct flash_bank *bank)
}
/* Issue warnings if this is a device we may not be able to flash */
- if (MSP432P401X_GUESS == msp432_bank->device_type ||
- MSP432P411X_GUESS == msp432_bank->device_type) {
+ if (msp432_bank->device_type == MSP432P401X_GUESS ||
+ msp432_bank->device_type == MSP432P411X_GUESS) {
/* Explicit device type check failed. Report this. */
LOG_WARNING(
"msp432: Unrecognized MSP432P4 Device ID and Hardware "
@@ -489,9 +489,9 @@ COMMAND_HANDLER(msp432_mass_erase_command)
all = false;
} else if (2 == CMD_ARGC) {
/* Check argument for how much to erase */
- if (0 == strcmp(CMD_ARGV[1], "main"))
+ if (strcmp(CMD_ARGV[1], "main") == 0)
all = false;
- else if (0 == strcmp(CMD_ARGV[1], "all"))
+ else if (strcmp(CMD_ARGV[1], "all") == 0)
all = true;
else
return ERROR_COMMAND_SYNTAX_ERROR;
@@ -543,9 +543,9 @@ COMMAND_HANDLER(msp432_bsl_command)
}
if (2 == CMD_ARGC) {
- if (0 == strcmp(CMD_ARGV[1], "lock"))
+ if (strcmp(CMD_ARGV[1], "lock") == 0)
msp432_bank->unlock_bsl = false;
- else if (0 == strcmp(CMD_ARGV[1], "unlock"))
+ else if (strcmp(CMD_ARGV[1], "unlock") == 0)
msp432_bank->unlock_bsl = true;
else
return ERROR_COMMAND_SYNTAX_ERROR;
@@ -597,8 +597,8 @@ static int msp432_erase(struct flash_bank *bank, unsigned int first,
struct msp432_bank *msp432_bank = bank->driver_priv;
struct msp432_algo_params algo_params;
- bool is_main = FLASH_BASE == bank->base;
- bool is_info = P4_FLASH_INFO_BASE == bank->base;
+ bool is_main = bank->base == FLASH_BASE;
+ bool is_info = bank->base == P4_FLASH_INFO_BASE;
int retval;
@@ -676,7 +676,7 @@ static int msp432_write(struct flash_bank *bank, const uint8_t *buffer,
long long start_ms;
long long elapsed_ms;
- bool is_info = P4_FLASH_INFO_BASE == bank->base;
+ bool is_info = bank->base == P4_FLASH_INFO_BASE;
int retval;
@@ -812,8 +812,8 @@ static int msp432_probe(struct flash_bank *bank)
uint32_t size;
unsigned int num_sectors;
- bool is_main = FLASH_BASE == bank->base;
- bool is_info = P4_FLASH_INFO_BASE == bank->base;
+ bool is_main = bank->base == FLASH_BASE;
+ bool is_info = bank->base == P4_FLASH_INFO_BASE;
int retval;
@@ -960,8 +960,8 @@ static int msp432_auto_probe(struct flash_bank *bank)
{
struct msp432_bank *msp432_bank = bank->driver_priv;
- bool is_main = FLASH_BASE == bank->base;
- bool is_info = P4_FLASH_INFO_BASE == bank->base;
+ bool is_main = bank->base == FLASH_BASE;
+ bool is_info = bank->base == P4_FLASH_INFO_BASE;
int retval = ERROR_OK;
@@ -1030,7 +1030,7 @@ static int msp432_protect_check(struct flash_bank *bank)
static void msp432_flash_free_driver_priv(struct flash_bank *bank)
{
- bool is_main = FLASH_BASE == bank->base;
+ bool is_main = bank->base == FLASH_BASE;
/* A single private struct is shared between main and info banks */
/* Only free it on the call for main bank */
diff --git a/src/flash/nor/tms470.c b/src/flash/nor/tms470.c
index f1eba9cd3..50783148b 100644
--- a/src/flash/nor/tms470.c
+++ b/src/flash/nor/tms470.c
@@ -296,9 +296,9 @@ COMMAND_HANDLER(tms470_handle_flash_keyset_command)
int i;
for (i = 0; i < 4; i++) {
- int start = (0 == strncmp(CMD_ARGV[i], "0x", 2)) ? 2 : 0;
+ int start = (strncmp(CMD_ARGV[i], "0x", 2) == 0) ? 2 : 0;
- if (1 != sscanf(&CMD_ARGV[i][start], "%" SCNx32 "", &flash_keys[i])) {
+ if (sscanf(&CMD_ARGV[i][start], "%" SCNx32 "", &flash_keys[i]) != 1) {
command_print(CMD, "could not process flash key %s",
CMD_ARGV[i]);
LOG_ERROR("could not process flash key %s", CMD_ARGV[i]);
diff --git a/src/helper/fileio.c b/src/helper/fileio.c
index 5138fa180..d544b8544 100644
--- a/src/helper/fileio.c
+++ b/src/helper/fileio.c
@@ -198,7 +198,7 @@ int fileio_read_u32(struct fileio *fileio, uint32_t *data)
retval = fileio_local_read(fileio, sizeof(uint32_t), buf, &size_read);
- if (ERROR_OK == retval && sizeof(uint32_t) != size_read)
+ if (retval == ERROR_OK && sizeof(uint32_t) != size_read)
retval = -EIO;
if (retval == ERROR_OK)
*data = be_to_h_u32(buf);
@@ -252,7 +252,7 @@ int fileio_write_u32(struct fileio *fileio, uint32_t data)
retval = fileio_write(fileio, 4, buf, &size_written);
- if (ERROR_OK == retval && size_written != sizeof(uint32_t))
+ if (retval == ERROR_OK && size_written != sizeof(uint32_t))
retval = -EIO;
return retval;
diff --git a/src/helper/log.c b/src/helper/log.c
index 785a8bded..b39cb9136 100644
--- a/src/helper/log.c
+++ b/src/helper/log.c
@@ -290,7 +290,7 @@ void log_init(void)
if (NULL != debug_env) {
int value;
int retval = parse_int(debug_env, &value);
- if (ERROR_OK == retval &&
+ if (retval == ERROR_OK &&
debug_level >= LOG_LVL_SILENT &&
debug_level <= LOG_LVL_DEBUG_IO)
debug_level = value;
diff --git a/src/jtag/aice/aice_usb.c b/src/jtag/aice/aice_usb.c
index 1c90b476c..f0bb6ccae 100644
--- a/src/jtag/aice/aice_usb.c
+++ b/src/jtag/aice/aice_usb.c
@@ -1929,12 +1929,12 @@ static int aice_read_reg(uint32_t coreid, uint32_t num, uint32_t *val)
instructions[2] = DSB;
instructions[3] = BEQ_MINUS_12;
} else {
- if (FS0 <= num && num <= FS31) { /* single precision */
+ if (num >= FS0 && num <= FS31) { /* single precision */
instructions[0] = FMFSR(0, nds32_reg_sr_index(num));
instructions[1] = MTSR_DTR(0);
instructions[2] = DSB;
instructions[3] = BEQ_MINUS_12;
- } else if (FD0 <= num && num <= FD31) { /* double precision */
+ } else if (num >= FD0 && num <= FD31) { /* double precision */
instructions[0] = FMFDR(0, nds32_reg_sr_index(num));
instructions[1] = MTSR_DTR(0);
instructions[2] = DSB;
@@ -2035,12 +2035,12 @@ static int aice_write_reg(uint32_t coreid, uint32_t num, uint32_t val)
} else if (num == FPCFG) {
/* FPCFG is readonly */
} else {
- if (FS0 <= num && num <= FS31) { /* single precision */
+ if (num >= FS0 && num <= FS31) { /* single precision */
instructions[0] = MFSR_DTR(0);
instructions[1] = FMTSR(0, nds32_reg_sr_index(num));
instructions[2] = DSB;
instructions[3] = BEQ_MINUS_12;
- } else if (FD0 <= num && num <= FD31) { /* double precision */
+ } else if (num >= FD0 && num <= FD31) { /* double precision */
instructions[0] = MFSR_DTR(0);
instructions[1] = FMTDR(0, nds32_reg_sr_index(num));
instructions[2] = DSB;
diff --git a/src/jtag/drivers/versaloon/versaloon.c b/src/jtag/drivers/versaloon/versaloon.c
index b8602ddeb..c6e390c93 100644
--- a/src/jtag/drivers/versaloon/versaloon.c
+++ b/src/jtag/drivers/versaloon/versaloon.c
@@ -212,7 +212,7 @@ RESULT versaloon_send_command(uint16_t out_len, uint16_t *inlen)
ret = libusb_bulk_transfer(versaloon_usb_device_handle,
versaloon_interface.usb_setting.ep_out,
versaloon_buf, out_len, &transferred, versaloon_usb_to);
- if (0 != ret || transferred != out_len) {
+ if (ret != 0 || transferred != out_len) {
LOG_ERROR(ERRMSG_FAILURE_OPERATION, "send usb data");
return ERRCODE_FAILURE_OPERATION;
}
diff --git a/src/jtag/drivers/xds110.c b/src/jtag/drivers/xds110.c
index 7b560df9d..1a17f70cc 100644
--- a/src/jtag/drivers/xds110.c
+++ b/src/jtag/drivers/xds110.c
@@ -379,8 +379,8 @@ static bool usb_connect(void)
/* Get the device's serial number string */
result = libusb_get_string_descriptor_ascii(dev,
desc.iSerialNumber, data, max_data);
- if (0 < result &&
- 0 == strcmp((char *)data, (char *)xds110.serial)) {
+ if (result > 0 &&
+ strcmp((char *)data, (char *)xds110.serial) == 0) {
found = true;
break;
}
@@ -497,7 +497,7 @@ static bool usb_write(unsigned char *buffer, int size, int *written)
result = libusb_bulk_transfer(xds110.dev, xds110.endpoint_out, buffer,
size, &bytes_written, 0);
- while (LIBUSB_ERROR_PIPE == result && retries < 3) {
+ while (result == LIBUSB_ERROR_PIPE && retries < 3) {
/* Try clearing the pipe stall and retry transfer */
libusb_clear_halt(xds110.dev, xds110.endpoint_out);
result = libusb_bulk_transfer(xds110.dev, xds110.endpoint_out, buffer,
@@ -508,7 +508,7 @@ static bool usb_write(unsigned char *buffer, int size, int *written)
if (NULL != written)
*written = bytes_written;
- return (0 == result && size == bytes_written) ? true : false;
+ return (result == 0 && size == bytes_written) ? true : false;
}
static bool usb_get_response(uint32_t *total_bytes_read, uint32_t timeout)
@@ -1021,7 +1021,7 @@ static bool xds_set_supply(uint32_t voltage)
xds110.write_payload[0] = XDS_SET_SUPPLY;
xds110_set_u32(volts_pntr, voltage);
- *source_pntr = (uint8_t)(0 != voltage ? 1 : 0);
+ *source_pntr = (uint8_t)(voltage != 0 ? 1 : 0);
success = xds_execute(XDS_OUT_LEN + 5, XDS_IN_LEN, DEFAULT_ATTEMPTS,
DEFAULT_TIMEOUT);
diff --git a/src/jtag/tcl.c b/src/jtag/tcl.c
index 79eea5460..2355babf0 100644
--- a/src/jtag/tcl.c
+++ b/src/jtag/tcl.c
@@ -133,7 +133,7 @@ static int jim_command_drscan(Jim_Interp *interp, int argc, Jim_Obj * const *arg
/* get arg as a string. */
cp = Jim_GetString(args[i], NULL);
/* is it the magic? */
- if (0 == strcmp("-endstate", cp)) {
+ if (strcmp("-endstate", cp) == 0) {
/* is the statename valid? */
cp = Jim_GetString(args[i + 1], NULL);
diff --git a/src/rtos/mqx.c b/src/rtos/mqx.c
index 377bca96c..9f59c6d7c 100644
--- a/src/rtos/mqx.c
+++ b/src/rtos/mqx.c
@@ -199,28 +199,22 @@ static int mqx_is_scheduler_running(
uint32_t capability_value = 0;
/* get '_mqx_kernel_data' symbol */
- if (ERROR_OK != mqx_get_symbol(
- rtos, MQX_VAL_MQX_KERNEL_DATA, &kernel_data_symbol
- )) {
+ if (mqx_get_symbol(rtos, MQX_VAL_MQX_KERNEL_DATA, &kernel_data_symbol) != ERROR_OK)
return ERROR_FAIL;
- }
+
/* get '_mqx_kernel_data' */
- if (ERROR_OK != mqx_get_member(
- rtos, kernel_data_symbol, 0, 4,
- "_mqx_kernel_data", &kernel_data_addr
- )) {
+ if (mqx_get_member(rtos, kernel_data_symbol, 0, 4,
+ "_mqx_kernel_data", &kernel_data_addr) != ERROR_OK)
return ERROR_FAIL;
- }
+
/* return if '_mqx_kernel_data' is NULL or default 0xFFFFFFFF */
- if (0 == kernel_data_addr || (uint32_t)(-1) == kernel_data_addr)
+ if (kernel_data_addr == 0 || kernel_data_addr == (uint32_t)(-1))
return ERROR_FAIL;
/* get kernel_data->ADDRESSING_CAPABILITY */
- if (ERROR_OK != mqx_get_member(
- rtos, kernel_data_addr, MQX_KERNEL_OFFSET_CAPABILITY, 4,
- "kernel_data->ADDRESSING_CAPABILITY", (void *)&capability_value
- )) {
+ if (mqx_get_member(rtos, kernel_data_addr, MQX_KERNEL_OFFSET_CAPABILITY, 4,
+ "kernel_data->ADDRESSING_CAPABILITY", (void *)&capability_value) != ERROR_OK)
return ERROR_FAIL;
- }
+
/* check first member, the '_mqx_kernel_data->ADDRESSING_CAPABILITY'.
it suppose to be set to value 8 */
if (capability_value != 8) {
@@ -228,12 +222,10 @@ static int mqx_is_scheduler_running(
return ERROR_FAIL;
}
/* get active ptr */
- if (ERROR_OK != mqx_get_member(
- rtos, kernel_data_addr, MQX_KERNEL_OFFSET_ACTIVE_TASK, 4,
- "kernel_data->ACTIVE_PTR", (void *)&active_td_addr
- )) {
+ if (mqx_get_member(rtos, kernel_data_addr, MQX_KERNEL_OFFSET_ACTIVE_TASK, 4,
+ "kernel_data->ACTIVE_PTR", (void *)&active_td_addr) != ERROR_OK)
return ERROR_FAIL;
- }
+
/* active task is system task, scheduler has not not run yet */
system_td_addr = kernel_data_addr + MQX_KERNEL_OFFSET_SYSTEM_TASK;
if (active_td_addr == system_td_addr) {
@@ -302,33 +294,25 @@ static int mqx_update_threads(
if (ERROR_OK != mqx_is_scheduler_running(rtos))
return ERROR_FAIL;
/* get kernel_data symbol */
- if (ERROR_OK != mqx_get_symbol(
- rtos, MQX_VAL_MQX_KERNEL_DATA, &kernel_data_addr
- )) {
+ if (mqx_get_symbol(rtos, MQX_VAL_MQX_KERNEL_DATA, &kernel_data_addr) != ERROR_OK)
return ERROR_FAIL;
- }
+
/* read kernel_data */
- if (ERROR_OK != mqx_get_member(
- rtos, kernel_data_addr, 0, 4, "_mqx_kernel_data", &kernel_data_addr
- )) {
+ if (mqx_get_member(rtos, kernel_data_addr, 0, 4,
+ "_mqx_kernel_data", &kernel_data_addr) != ERROR_OK)
return ERROR_FAIL;
- }
+
/* get task queue address */
task_queue_addr = kernel_data_addr + MQX_KERNEL_OFFSET_TDLIST;
/* get task queue size */
- if (ERROR_OK != mqx_get_member(
- rtos, task_queue_addr, MQX_QUEUE_OFFSET_SIZE, 2,
- "kernel_data->TD_LIST.SIZE", &task_queue_size
- )) {
+ if (mqx_get_member(rtos, task_queue_addr, MQX_QUEUE_OFFSET_SIZE, 2,
+ "kernel_data->TD_LIST.SIZE", &task_queue_size) != ERROR_OK)
return ERROR_FAIL;
- }
+
/* get active ptr */
- if (ERROR_OK != mqx_get_member(
- rtos, kernel_data_addr, MQX_KERNEL_OFFSET_ACTIVE_TASK, 4,
- "kernel_data->ACTIVE_PTR", (void *)&active_td_addr
- )) {
+ if (mqx_get_member(rtos, kernel_data_addr, MQX_KERNEL_OFFSET_ACTIVE_TASK, 4,
+ "kernel_data->ACTIVE_PTR", (void *)&active_td_addr) != ERROR_OK)
return ERROR_FAIL;
- }
/* setup threads info */
rtos->thread_count = task_queue_size;
@@ -355,60 +339,46 @@ static int mqx_update_threads(
char *state_name = "Unknown";
/* set current taskpool address */
- if (ERROR_OK != mqx_get_member(
- rtos, taskpool_addr, MQX_TASK_OFFSET_NEXT, 4,
- "td_struct_ptr->NEXT", &taskpool_addr
- )) {
+ if (mqx_get_member(rtos, taskpool_addr, MQX_TASK_OFFSET_NEXT, 4,
+ "td_struct_ptr->NEXT", &taskpool_addr) != ERROR_OK)
return ERROR_FAIL;
- }
+
/* get task address from taskpool */
task_addr = taskpool_addr - MQX_TASK_OFFSET_TDLIST;
/* get address of 'td_struct_ptr->TEMPLATE_LIST_PTR' */
- if (ERROR_OK != mqx_get_member(
- rtos, task_addr, MQX_TASK_OFFSET_TEMPLATE, 4,
- "td_struct_ptr->TEMPLATE_LIST_PTR", &task_template
- )) {
+ if (mqx_get_member(rtos, task_addr, MQX_TASK_OFFSET_TEMPLATE, 4,
+ "td_struct_ptr->TEMPLATE_LIST_PTR", &task_template) != ERROR_OK)
return ERROR_FAIL;
- }
+
/* get address of 'td_struct_ptr->TEMPLATE_LIST_PTR->NAME' */
- if (ERROR_OK != mqx_get_member(
- rtos, task_template, MQX_TASK_TEMPLATE_OFFSET_NAME, 4,
- "td_struct_ptr->TEMPLATE_LIST_PTR->NAME", &task_name_addr
- )) {
+ if (mqx_get_member(rtos, task_template, MQX_TASK_TEMPLATE_OFFSET_NAME, 4,
+ "td_struct_ptr->TEMPLATE_LIST_PTR->NAME", &task_name_addr) != ERROR_OK)
return ERROR_FAIL;
- }
+
/* get value of 'td_struct->TEMPLATE_LIST_PTR->NAME' */
- if (ERROR_OK != mqx_get_member(
- rtos, task_name_addr, 0, MQX_THREAD_NAME_LENGTH,
- "*td_struct_ptr->TEMPLATE_LIST_PTR->NAME", task_name
- )) {
+ if (mqx_get_member(rtos, task_name_addr, 0, MQX_THREAD_NAME_LENGTH,
+ "*td_struct_ptr->TEMPLATE_LIST_PTR->NAME", task_name) != ERROR_OK)
return ERROR_FAIL;
- }
+
/* always terminate last character by force,
otherwise openocd might fail if task_name
has corrupted data */
task_name[MQX_THREAD_NAME_LENGTH] = '\0';
/* get value of 'td_struct_ptr->TASK_ID' */
- if (ERROR_OK != mqx_get_member(
- rtos, task_addr, MQX_TASK_OFFSET_ID, 4,
- "td_struct_ptr->TASK_ID", &task_id
- )) {
+ if (mqx_get_member(rtos, task_addr, MQX_TASK_OFFSET_ID, 4,
+ "td_struct_ptr->TASK_ID", &task_id) != ERROR_OK)
return ERROR_FAIL;
- }
+
/* get task errno */
- if (ERROR_OK != mqx_get_member(
- rtos, task_addr, MQX_TASK_OFFSET_ERROR_CODE, 4,
- "td_struct_ptr->TASK_ERROR_CODE", &task_errno
- )) {
+ if (mqx_get_member(rtos, task_addr, MQX_TASK_OFFSET_ERROR_CODE, 4,
+ "td_struct_ptr->TASK_ERROR_CODE", &task_errno) != ERROR_OK)
return ERROR_FAIL;
- }
+
/* get value of 'td_struct_ptr->STATE' */
- if (ERROR_OK != mqx_get_member(
- rtos, task_addr, MQX_TASK_OFFSET_STATE, 4,
- "td_struct_ptr->STATE", &task_state
- )) {
+ if (mqx_get_member(rtos, task_addr, MQX_TASK_OFFSET_STATE, 4,
+ "td_struct_ptr->STATE", &task_state) != ERROR_OK)
return ERROR_FAIL;
- }
+
task_state &= MQX_TASK_STATE_MASK;
/* and search for defined state */
for (state_index = 0; state_index < ARRAY_SIZE(mqx_states); state_index++) {
@@ -471,26 +441,21 @@ static int mqx_get_thread_reg_list(
if (ERROR_OK != mqx_is_scheduler_running(rtos))
return ERROR_FAIL;
/* get kernel_data symbol */
- if (ERROR_OK != mqx_get_symbol(
- rtos, MQX_VAL_MQX_KERNEL_DATA, &kernel_data_addr
- )) {
+ if (mqx_get_symbol(rtos, MQX_VAL_MQX_KERNEL_DATA, &kernel_data_addr) != ERROR_OK)
return ERROR_FAIL;
- }
+
/* read kernel_data */
- if (ERROR_OK != mqx_get_member(
- rtos, kernel_data_addr, 0, 4, "_mqx_kernel_data", &kernel_data_addr
- )) {
+ if (mqx_get_member(rtos, kernel_data_addr, 0, 4,
+ "_mqx_kernel_data", &kernel_data_addr) != ERROR_OK)
return ERROR_FAIL;
- }
+
/* get task queue address */
task_queue_addr = kernel_data_addr + MQX_KERNEL_OFFSET_TDLIST;
/* get task queue size */
- if (ERROR_OK != mqx_get_member(
- rtos, task_queue_addr, MQX_QUEUE_OFFSET_SIZE, 2,
- "kernel_data->TD_LIST.SIZE", &task_queue_size
- )) {
+ if (mqx_get_member(rtos, task_queue_addr, MQX_QUEUE_OFFSET_SIZE, 2,
+ "kernel_data->TD_LIST.SIZE", &task_queue_size) != ERROR_OK)
return ERROR_FAIL;
- }
+
/* search for taskid */
for (
uint32_t i = 0, taskpool_addr = task_queue_addr;
@@ -501,21 +466,17 @@ static int mqx_get_thread_reg_list(
uint32_t task_id = 0;
/* set current taskpool address */
tmp_address = taskpool_addr;
- if (ERROR_OK != mqx_get_member(
- rtos, tmp_address, MQX_TASK_OFFSET_NEXT, 4,
- "td_struct_ptr->NEXT", &taskpool_addr
- )) {
+ if (mqx_get_member(rtos, tmp_address, MQX_TASK_OFFSET_NEXT, 4,
+ "td_struct_ptr->NEXT", &taskpool_addr) != ERROR_OK)
return ERROR_FAIL;
- }
+
/* get task address from taskpool */
task_addr = taskpool_addr - MQX_TASK_OFFSET_TDLIST;
/* get value of td_struct->TASK_ID */
- if (ERROR_OK != mqx_get_member(
- rtos, task_addr, MQX_TASK_OFFSET_ID, 4,
- "td_struct_ptr->TASK_ID", &task_id
- )) {
+ if (mqx_get_member(rtos, task_addr, MQX_TASK_OFFSET_ID, 4,
+ "td_struct_ptr->TASK_ID", &task_id) != ERROR_OK)
return ERROR_FAIL;
- }
+
/* found taskid, break */
if (task_id == thread_id) {
my_task_addr = task_addr;
@@ -527,11 +488,10 @@ static int mqx_get_thread_reg_list(
return ERROR_FAIL;
}
/* get task stack head address */
- if (ERROR_OK != mqx_get_member(
- rtos, my_task_addr, MQX_TASK_OFFSET_STACK, 4, "task->STACK_PTR", &stack_ptr
- )) {
+ if (mqx_get_member(rtos, my_task_addr, MQX_TASK_OFFSET_STACK, 4,
+ "task->STACK_PTR", &stack_ptr) != ERROR_OK)
return ERROR_FAIL;
- }
+
return rtos_generic_stack_read(
rtos->target, ((struct mqx_params *)rtos->rtos_specific_params)->stacking_info, stack_ptr, reg_list, num_regs
);
diff --git a/src/rtos/rtos.c b/src/rtos/rtos.c
index 8e3febc06..7d96825b9 100644
--- a/src/rtos/rtos.c
+++ b/src/rtos/rtos.c
@@ -140,7 +140,7 @@ int rtos_create(struct jim_getopt_info *goi, struct target *target)
if (e != JIM_OK)
return e;
- if (0 == strcmp(cp, "auto")) {
+ if (strcmp(cp, "auto") == 0) {
/* Auto detect tries to look up all symbols for each RTOS,
* and runs the RTOS driver's _detect() function when GDB
* finds all symbols for any RTOS. See rtos_qsymbol(). */
diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c
index 9de7048f4..1e5b5e252 100644
--- a/src/target/arm_semihosting.c
+++ b/src/target/arm_semihosting.c
@@ -367,7 +367,7 @@ int arm_semihosting(struct target *target, int *retval)
}
/* Check for ARM operation numbers. */
- if (0 <= semihosting->op && semihosting->op <= 0x31) {
+ if (semihosting->op >= 0 && semihosting->op <= 0x31) {
*retval = semihosting_common(target);
if (*retval != ERROR_OK) {
LOG_ERROR("Failed semihosting operation (0x%02X)", semihosting->op);
diff --git a/src/target/nds32.c b/src/target/nds32.c
index 184f2fecc..4b1d1177c 100644
--- a/src/target/nds32.c
+++ b/src/target/nds32.c
@@ -422,7 +422,7 @@ static struct reg_cache *nds32_build_reg_cache(struct target *target,
reg_list[i].reg_data_type = calloc(sizeof(struct reg_data_type), 1);
- if (FD0 <= reg_arch_info[i].num && reg_arch_info[i].num <= FD31) {
+ if (reg_arch_info[i].num >= FD0 && reg_arch_info[i].num <= FD31) {
reg_list[i].value = reg_arch_info[i].value;
reg_list[i].type = &nds32_reg_access_type_64;
@@ -456,20 +456,20 @@ static struct reg_cache *nds32_build_reg_cache(struct target *target,
}
}
- if (R16 <= reg_arch_info[i].num && reg_arch_info[i].num <= R25)
+ if (reg_arch_info[i].num >= R16 && reg_arch_info[i].num <= R25)
reg_list[i].caller_save = true;
else
reg_list[i].caller_save = false;
reg_list[i].feature = malloc(sizeof(struct reg_feature));
- if (R0 <= reg_arch_info[i].num && reg_arch_info[i].num <= IFC_LP)
+ if (reg_arch_info[i].num >= R0 && reg_arch_info[i].num <= IFC_LP)
reg_list[i].feature->name = "org.gnu.gdb.nds32.core";
- else if (CR0 <= reg_arch_info[i].num && reg_arch_info[i].num <= SECUR0)
+ else if (reg_arch_info[i].num >= CR0 && reg_arch_info[i].num <= SECUR0)
reg_list[i].feature->name = "org.gnu.gdb.nds32.system";
- else if (D0L24 <= reg_arch_info[i].num && reg_arch_info[i].num <= CBE3)
+ else if (reg_arch_info[i].num >= D0L24 && reg_arch_info[i].num <= CBE3)
reg_list[i].feature->name = "org.gnu.gdb.nds32.audio";
- else if (FPCSR <= reg_arch_info[i].num && reg_arch_info[i].num <= FD31)
+ else if (reg_arch_info[i].num >= FPCSR && reg_arch_info[i].num <= FD31)
reg_list[i].feature->name = "org.gnu.gdb.nds32.fpu";
cache->num_regs++;
@@ -1545,7 +1545,7 @@ int nds32_restore_context(struct target *target)
i, buf_get_u32(reg->value, 0, 32));
reg_arch_info = reg->arch_info;
- if (FD0 <= reg_arch_info->num && reg_arch_info->num <= FD31) {
+ if (reg_arch_info->num >= FD0 && reg_arch_info->num <= FD31) {
uint64_t val = buf_get_u64(reg_arch_info->value, 0, 64);
aice_write_reg_64(aice, reg_arch_info->num, val);
} else {
@@ -1735,8 +1735,7 @@ int nds32_cache_sync(struct target *target, target_addr_t address, uint32_t leng
* be physical address. L1I_VA_INVALIDATE uses PSW.IT to decide
* address translation or not. */
target_addr_t physical_addr;
- if (ERROR_FAIL == target->type->virt2phys(target, cur_address,
- &physical_addr))
+ if (target->type->virt2phys(target, cur_address, &physical_addr) == ERROR_FAIL)
return ERROR_FAIL;
/* I$ invalidate */
@@ -1926,8 +1925,7 @@ int nds32_examine_debug_reason(struct nds32 *nds32)
if (ERROR_OK != nds32_read_opcode(nds32, value_pc, &opcode))
return ERROR_FAIL;
- if (ERROR_OK != nds32_evaluate_opcode(nds32, opcode, value_pc,
- &instruction))
+ if (nds32_evaluate_opcode(nds32, opcode, value_pc, &instruction) != ERROR_OK)
return ERROR_FAIL;
/* hit 'break 0x7FFF' */
@@ -1966,8 +1964,7 @@ int nds32_examine_debug_reason(struct nds32 *nds32)
case NDS32_DEBUG_DATA_VALUE_WATCHPOINT_IMPRECISE:
case NDS32_DEBUG_DATA_ADDR_WATCHPOINT_NEXT_PRECISE:
case NDS32_DEBUG_DATA_VALUE_WATCHPOINT_NEXT_PRECISE:
- if (ERROR_OK != nds32->get_watched_address(nds32,
- &(nds32->watched_address), reason))
+ if (nds32->get_watched_address(nds32, &(nds32->watched_address), reason) != ERROR_OK)
return ERROR_FAIL;
target->debug_reason = DBG_REASON_WATCHPOINT;
diff --git a/src/target/nds32_cmd.c b/src/target/nds32_cmd.c
index 3931707be..af1f8b18a 100644
--- a/src/target/nds32_cmd.c
+++ b/src/target/nds32_cmd.c
@@ -577,8 +577,7 @@ COMMAND_HANDLER(handle_nds32_decode_command)
while (i < insn_count) {
if (ERROR_OK != nds32_read_opcode(nds32, read_addr, &opcode))
return ERROR_FAIL;
- if (ERROR_OK != nds32_evaluate_opcode(nds32, opcode,
- read_addr, &instruction))
+ if (nds32_evaluate_opcode(nds32, opcode, read_addr, &instruction) != ERROR_OK)
return ERROR_FAIL;
command_print(CMD, "%s", instruction.text);
diff --git a/src/target/nds32_disassembler.c b/src/target/nds32_disassembler.c
index 0cfd197d2..0bf74e178 100644
--- a/src/target/nds32_disassembler.c
+++ b/src/target/nds32_disassembler.c
@@ -2849,7 +2849,7 @@ static uint32_t field_mask[9] = {
static uint8_t nds32_extract_field_8u(uint16_t opcode, uint32_t start, uint32_t length)
{
- if (0 < length && length < 9)
+ if (length > 0 && length < 9)
return (opcode >> start) & field_mask[length];
return 0;
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c
index b70c259dc..b93e5494a 100644
--- a/src/target/riscv/riscv-013.c
+++ b/src/target/riscv/riscv-013.c
@@ -4653,10 +4653,10 @@ int riscv013_test_compliance(struct target *target)
for (unsigned int i = 1; i < 32; i = i << 1) {
riscv_reg_t testval = i | ((i + 1ULL) << 32);
riscv_reg_t testval_read;
- COMPLIANCE_TEST(ERROR_OK == register_write_direct(target, GDB_REGNO_ZERO + i, testval),
+ COMPLIANCE_TEST(register_write_direct(target, GDB_REGNO_ZERO + i, testval) == ERROR_OK,
"GPR Writes should be supported.");
COMPLIANCE_MUST_PASS(write_abstract_arg(target, 0, 0xDEADBEEFDEADBEEF, 64));
- COMPLIANCE_TEST(ERROR_OK == register_read_direct(target, &testval_read, GDB_REGNO_ZERO + i),
+ COMPLIANCE_TEST(register_read_direct(target, &testval_read, GDB_REGNO_ZERO + i) == ERROR_OK,
"GPR Reads should be supported.");
if (riscv_xlen(target) > 32) {
/* Dummy comment to satisfy linter, since removing the branches here doesn't actually compile. */
@@ -4680,7 +4680,7 @@ int riscv013_test_compliance(struct target *target)
if (info->progbufsize >= 3) {
testvar = 0;
- COMPLIANCE_TEST(ERROR_OK == register_write_direct(target, GDB_REGNO_S0, 0),
+ COMPLIANCE_TEST(register_write_direct(target, GDB_REGNO_S0, 0) == ERROR_OK,
"Need to be able to write S0 to test ABSTRACTAUTO");
struct riscv_program program;
COMPLIANCE_MUST_PASS(riscv_program_init(&program, target));
@@ -4721,7 +4721,7 @@ int riscv013_test_compliance(struct target *target)
}
COMPLIANCE_WRITE(target, DM_ABSTRACTAUTO, 0);
- COMPLIANCE_TEST(ERROR_OK == register_read_direct(target, &value, GDB_REGNO_S0),
+ COMPLIANCE_TEST(register_read_direct(target, &value, GDB_REGNO_S0) == ERROR_OK,
"Need to be able to read S0 to test ABSTRACTAUTO");
COMPLIANCE_TEST(testvar == value,
@@ -4797,8 +4797,8 @@ int riscv013_test_compliance(struct target *target)
/* Pulse reset. */
target->reset_halt = true;
COMPLIANCE_MUST_PASS(riscv_set_current_hartid(target, 0));
- COMPLIANCE_TEST(ERROR_OK == assert_reset(target), "Must be able to assert NDMRESET");
- COMPLIANCE_TEST(ERROR_OK == deassert_reset(target), "Must be able to deassert NDMRESET");
+ COMPLIANCE_TEST(assert_reset(target) == ERROR_OK, "Must be able to assert NDMRESET");
+ COMPLIANCE_TEST(deassert_reset(target) == ERROR_OK, "Must be able to deassert NDMRESET");
/* Verify that most stuff is not affected by ndmreset. */
COMPLIANCE_READ(target, &testvar_read, DM_ABSTRACTCS);
diff --git a/src/target/riscv/riscv_semihosting.c b/src/target/riscv/riscv_semihosting.c
index c0e81eae4..90b8ddb4f 100644
--- a/src/target/riscv/riscv_semihosting.c
+++ b/src/target/riscv/riscv_semihosting.c
@@ -137,7 +137,7 @@ semihosting_result_t riscv_semihosting(struct target *target, int *retval)
semihosting->word_size_bytes = riscv_xlen(target) / 8;
/* Check for ARM operation numbers. */
- if (0 <= semihosting->op && semihosting->op <= 0x31) {
+ if (semihosting->op >= 0 && semihosting->op <= 0x31) {
*retval = semihosting_common(target);
if (*retval != ERROR_OK) {
LOG_ERROR("Failed semihosting operation (0x%02X)", semihosting->op);
commit 28c24a5c41c47a66e9310912f88148814f730a25
Author: Antonio Borneo <bor...@gm...>
Date: Sat Jul 3 16:47:35 2021 +0200
openocd: fix simple cases of Yoda condition
There are ~900 Yoda conditions to be aligned to the coding style.
For recurrent Yoda conditions it's preferable using a trivial
script in order to minimize the review effort.
E.g. comparison of uppercase macro/enum with lowercase variable:
- ...(ERROR_OK == retval)...
+ ...(retval == ERROR_OK)...
Patch generated automatically with the command:
sed -i \
's/(\([A-Z][A-Z0-9_]*\) \([=!]=\) \([a-z][a-z0-9_]*\))/(\3 \2 \1)/g' \
$(find src/ -type f)
While there, remove the braces {} around a single statement block
to prevent warning from checkpatch.
Change-Id: If585b0a4b4578879c87b2dd74d9e0025e275ec6b
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/6354
Tested-by: jenkins
Reviewed-by: Xiang W <wx...@12...>
diff --git a/src/flash/common.c b/src/flash/common.c
index 3e2551192..e8e795a4e 100644
--- a/src/flash/common.c
+++ b/src/flash/common.c
@@ -32,7 +32,7 @@ unsigned get_flash_name_index(const char *name)
unsigned requested;
int retval = parse_uint(name_index + 1, &requested);
/* detect parsing error by forcing past end of bank list */
- return (ERROR_OK == retval) ? requested : ~0U;
+ return (retval == ERROR_OK) ? requested : ~0U;
}
bool flash_driver_name_matches(const char *name, const char *expected)
diff --git a/src/flash/nand/at91sam9.c b/src/flash/nand/at91sam9.c
index 534f20ede..4341935fe 100644
--- a/src/flash/nand/at91sam9.c
+++ b/src/flash/nand/at91sam9.c
@@ -368,16 +368,16 @@ static int at91sam9_read_page(struct nand_device *nand, uint32_t page,
uint32_t status;
retval = at91sam9_ecc_init(target, info);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
retval = nand_page_command(nand, page, NAND_CMD_READ0, !data);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (data) {
retval = nand_read_data_page(nand, data, data_size);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
}
@@ -443,16 +443,16 @@ static int at91sam9_write_page(struct nand_device *nand, uint32_t page,
uint32_t parity, nparity;
retval = at91sam9_ecc_init(target, info);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (data) {
retval = nand_write_data_page(nand, data, data_size);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Unable to write data to NAND device");
return retval;
}
@@ -476,7 +476,7 @@ static int at91sam9_write_page(struct nand_device *nand, uint32_t page,
if (!oob)
free(oob_data);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Unable to write OOB data to NAND");
return retval;
}
diff --git a/src/flash/nand/core.c b/src/flash/nand/core.c
index baef5d59c..8e2af2338 100644
--- a/src/flash/nand/core.c
+++ b/src/flash/nand/core.c
@@ -750,7 +750,7 @@ int nand_page_command(struct nand_device *nand, uint32_t page,
nand->controller->address(nand, (page >> 16) & 0xff);
/* large page devices need a start command if reading */
- if (NAND_CMD_READ0 == cmd)
+ if (cmd == NAND_CMD_READ0)
nand->controller->command(nand, NAND_CMD_READSTART);
}
@@ -772,7 +772,7 @@ int nand_read_data_page(struct nand_device *nand, uint8_t *data, uint32_t size)
if (nand->controller->read_block_data != NULL)
retval = (nand->controller->read_block_data)(nand, data, size);
- if (ERROR_NAND_NO_BUFFER == retval) {
+ if (retval == ERROR_NAND_NO_BUFFER) {
uint32_t i;
int incr = (nand->device->options & NAND_BUSWIDTH_16) ? 2 : 1;
@@ -793,7 +793,7 @@ int nand_read_page_raw(struct nand_device *nand, uint32_t page,
int retval;
retval = nand_page_command(nand, page, NAND_CMD_READ0, !data);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (data)
@@ -812,7 +812,7 @@ int nand_write_data_page(struct nand_device *nand, uint8_t *data, uint32_t size)
if (nand->controller->write_block_data != NULL)
retval = (nand->controller->write_block_data)(nand, data, size);
- if (ERROR_NAND_NO_BUFFER == retval) {
+ if (retval == ERROR_NAND_NO_BUFFER) {
bool is16bit = nand->device->options & NAND_BUSWIDTH_16;
uint32_t incr = is16bit ? 2 : 1;
uint16_t write_data;
@@ -825,7 +825,7 @@ int nand_write_data_page(struct nand_device *nand, uint8_t *data, uint32_t size)
write_data = *data;
retval = nand->controller->write_data(nand, write_data);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
break;
data += incr;
@@ -849,7 +849,7 @@ int nand_write_finish(struct nand_device *nand)
return ERROR_NAND_OPERATION_TIMEOUT;
retval = nand_read_status(nand, &status);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("couldn't read status");
return ERROR_NAND_OPERATION_FAILED;
}
@@ -870,12 +870,12 @@ int nand_write_page_raw(struct nand_device *nand, uint32_t page,
int retval;
retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (data) {
retval = nand_write_data_page(nand, data, data_size);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Unable to write data to NAND device");
return retval;
}
@@ -883,7 +883,7 @@ int nand_write_page_raw(struct nand_device *nand, uint32_t page,
if (oob) {
retval = nand_write_data_page(nand, oob, oob_size);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Unable to write OOB data to NAND device");
return retval;
}
diff --git a/src/flash/nand/driver.c b/src/flash/nand/driver.c
index f7665603f..b525f3d0a 100644
--- a/src/flash/nand/driver.c
+++ b/src/flash/nand/driver.c
@@ -75,7 +75,7 @@ int nand_driver_walk(nand_driver_walker_t f, void *x)
{
for (unsigned i = 0; nand_flash_controllers[i]; i++) {
int retval = (*f)(nand_flash_controllers[i], x);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
}
return ERROR_OK;
diff --git a/src/flash/nand/fileio.c b/src/flash/nand/fileio.c
index fee401292..5504841b5 100644
--- a/src/flash/nand/fileio.c
+++ b/src/flash/nand/fileio.c
@@ -67,8 +67,8 @@ int nand_fileio_start(struct command_invocation *cmd,
if (NULL != filename) {
int retval = fileio_open(&state->fileio, filename, filemode, FILEIO_BINARY);
- if (ERROR_OK != retval) {
- const char *msg = (FILEIO_READ == filemode) ? "read" : "write";
+ if (retval != ERROR_OK) {
+ const char *msg = (filemode == FILEIO_READ) ? "read" : "write";
command_print(cmd, "failed to open '%s' for %s access",
filename, msg);
return retval;
@@ -124,7 +124,7 @@ COMMAND_HELPER(nand_fileio_parse_args, struct nand_fileio_state *state,
struct nand_device *nand;
int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &nand);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (NULL == nand->device) {
@@ -159,7 +159,7 @@ COMMAND_HELPER(nand_fileio_parse_args, struct nand_fileio_state *state,
}
retval = nand_fileio_start(CMD, nand, CMD_ARGV[1], filemode, state);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
if (!need_size) {
diff --git a/src/flash/nand/lpc3180.c b/src/flash/nand/lpc3180.c
index 6ce05753e..bda7b87c3 100644
--- a/src/flash/nand/lpc3180.c
+++ b/src/flash/nand/lpc3180.c
@@ -589,7 +589,7 @@ static int lpc3180_write_page(struct nand_device *nand,
oob_size);
}
retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
/* allocate a working area */
@@ -970,7 +970,7 @@ static int lpc3180_read_page(struct nand_device *nand,
/* read always the data and also oob areas*/
retval = nand_page_command(nand, page, NAND_CMD_READ0, 0);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
/* allocate a working area */
diff --git a/src/flash/nand/lpc32xx.c b/src/flash/nand/lpc32xx.c
index 3e2add49b..49890c2ab 100644
--- a/src/flash/nand/lpc32xx.c
+++ b/src/flash/nand/lpc32xx.c
@@ -141,7 +141,7 @@ static float lpc32xx_cycle_time(struct nand_device *nand)
/* determine current SYSCLK (13'MHz or main oscillator) */
retval = target_read_u32(target, 0x40004050, &sysclk_ctrl);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not read SYSCLK_CTRL");
return ERROR_NAND_OPERATION_FAILED;
}
@@ -153,7 +153,7 @@ static float lpc32xx_cycle_time(struct nand_device *nand)
/* determine selected HCLK source */
retval = target_read_u32(target, 0x40004044, &pwr_ctrl);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not read HCLK_CTRL");
return ERROR_NAND_OPERATION_FAILED;
}
@@ -162,14 +162,14 @@ static float lpc32xx_cycle_time(struct nand_device *nand)
hclk = sysclk;
else {
retval = target_read_u32(target, 0x40004058, &hclkpll_ctrl);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not read HCLKPLL_CTRL");
return ERROR_NAND_OPERATION_FAILED;
}
hclk_pll = lpc32xx_pll(sysclk, hclkpll_ctrl);
retval = target_read_u32(target, 0x40004040, &hclkdiv_ctrl);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not read CLKDIV_CTRL");
return ERROR_NAND_OPERATION_FAILED;
}
@@ -235,21 +235,21 @@ static int lpc32xx_init(struct nand_device *nand)
/* FLASHCLK_CTRL = 0x22 (enable clk for MLC) */
retval = target_write_u32(target, 0x400040c8, 0x22);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set FLASHCLK_CTRL");
return ERROR_NAND_OPERATION_FAILED;
}
/* MLC_CEH = 0x0 (Force nCE assert) */
retval = target_write_u32(target, 0x200b804c, 0x0);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_CEH");
return ERROR_NAND_OPERATION_FAILED;
}
/* MLC_LOCK = 0xa25e (unlock protected registers) */
retval = target_write_u32(target, 0x200b8044, 0xa25e);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_LOCK");
return ERROR_NAND_OPERATION_FAILED;
}
@@ -264,7 +264,7 @@ static int lpc32xx_init(struct nand_device *nand)
if (bus_width == 16)
mlc_icr_value |= 0x1;
retval = target_write_u32(target, 0x200b8030, mlc_icr_value);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ICR");
return ERROR_NAND_OPERATION_FAILED;
}
@@ -282,7 +282,7 @@ static int lpc32xx_init(struct nand_device *nand)
/* MLC_LOCK = 0xa25e (unlock protected registers) */
retval = target_write_u32(target, 0x200b8044, 0xa25e);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_LOCK");
return ERROR_NAND_OPERATION_FAILED;
}
@@ -296,13 +296,13 @@ static int lpc32xx_init(struct nand_device *nand)
| ((trhz & 0x7) << 16)
| ((trbwb & 0x1f) << 19)
| ((tcea & 0x3) << 24));
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_TIME_REG");
return ERROR_NAND_OPERATION_FAILED;
}
retval = lpc32xx_reset(nand);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return ERROR_NAND_OPERATION_FAILED;
} else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
float cycle;
@@ -311,7 +311,7 @@ static int lpc32xx_init(struct nand_device *nand)
/* FLASHCLK_CTRL = 0x05 (enable clk for SLC) */
retval = target_write_u32(target, 0x400040c8, 0x05);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set FLASHCLK_CTRL");
return ERROR_NAND_OPERATION_FAILED;
}
@@ -320,7 +320,7 @@ static int lpc32xx_init(struct nand_device *nand)
* so reset calling is here at the beginning
*/
retval = lpc32xx_reset(nand);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return ERROR_NAND_OPERATION_FAILED;
/* SLC_CFG =
@@ -333,14 +333,14 @@ static int lpc32xx_init(struct nand_device *nand)
*/
retval = target_write_u32(target, 0x20020014,
0x3e | ((bus_width == 16) ? 1 : 0));
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set SLC_CFG");
return ERROR_NAND_OPERATION_FAILED;
}
/* SLC_IEN = 3 (INT_RDY_EN = 1) ,(INT_TC_STAT = 1) */
retval = target_write_u32(target, 0x20020020, 0x03);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set SLC_IEN");
return ERROR_NAND_OPERATION_FAILED;
}
@@ -349,14 +349,14 @@ static int lpc32xx_init(struct nand_device *nand)
/* DMACLK_CTRL = 0x01 (enable clock for DMA controller) */
retval = target_write_u32(target, 0x400040e8, 0x01);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set DMACLK_CTRL");
return ERROR_NAND_OPERATION_FAILED;
}
/* DMACConfig = DMA enabled*/
retval = target_write_u32(target, 0x31000030, 0x01);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set DMACConfig");
return ERROR_NAND_OPERATION_FAILED;
}
@@ -380,7 +380,7 @@ static int lpc32xx_init(struct nand_device *nand)
| ((w_hold & 0xf) << 20)
| ((w_width & 0xf) << 24)
| ((w_rdy & 0xf) << 28));
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set SLC_TAC");
return ERROR_NAND_OPERATION_FAILED;
}
@@ -407,7 +407,7 @@ static int lpc32xx_reset(struct nand_device *nand)
} else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
/* MLC_CMD = 0xff (reset controller and NAND device) */
retval = target_write_u32(target, 0x200b8000, 0xff);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_CMD");
return ERROR_NAND_OPERATION_FAILED;
}
@@ -420,7 +420,7 @@ static int lpc32xx_reset(struct nand_device *nand)
} else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
/* SLC_CTRL = 0x6 (ECC_CLEAR, SW_RESET) */
retval = target_write_u32(target, 0x20020010, 0x6);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set SLC_CTRL");
return ERROR_NAND_OPERATION_FAILED;
}
@@ -453,14 +453,14 @@ static int lpc32xx_command(struct nand_device *nand, uint8_t command)
} else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
/* MLC_CMD = command */
retval = target_write_u32(target, 0x200b8000, command);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_CMD");
return ERROR_NAND_OPERATION_FAILED;
}
} else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
/* SLC_CMD = command */
retval = target_write_u32(target, 0x20020008, command);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set SLC_CMD");
return ERROR_NAND_OPERATION_FAILED;
}
@@ -487,14 +487,14 @@ static int lpc32xx_address(struct nand_device *nand, uint8_t address)
} else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
/* MLC_ADDR = address */
retval = target_write_u32(target, 0x200b8004, address);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
} else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
/* SLC_ADDR = address */
retval = target_write_u32(target, 0x20020004, address);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set SLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
@@ -521,14 +521,14 @@ static int lpc32xx_write_data(struct nand_device *nand, uint16_t data)
} else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
/* MLC_DATA = data */
retval = target_write_u32(target, 0x200b0000, data);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_DATA");
return ERROR_NAND_OPERATION_FAILED;
}
} else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
/* SLC_DATA = data */
retval = target_write_u32(target, 0x20020000, data);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set SLC_DATA");
return ERROR_NAND_OPERATION_FAILED;
}
@@ -561,7 +561,7 @@ static int lpc32xx_read_data(struct nand_device *nand, void *data)
LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
return ERROR_NAND_OPERATION_FAILED;
}
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not read MLC_DATA");
return ERROR_NAND_OPERATION_FAILED;
}
@@ -570,7 +570,7 @@ static int lpc32xx_read_data(struct nand_device *nand, void *data)
/* data = SLC_DATA, must use 32-bit access */
retval = target_read_u32(target, 0x20020000, &data32);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not read SLC_DATA");
return ERROR_NAND_OPERATION_FAILED;
}
@@ -600,7 +600,7 @@ static int lpc32xx_write_page_mlc(struct nand_device *nand, uint32_t page,
/* MLC_CMD = sequential input */
retval = target_write_u32(target, 0x200b8000, NAND_CMD_SEQIN);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_CMD");
return ERROR_NAND_OPERATION_FAILED;
}
@@ -608,20 +608,20 @@ static int lpc32xx_write_page_mlc(struct nand_device *nand, uint32_t page,
if (nand->page_size == 512) {
/* MLC_ADDR = 0x0 (one column cycle) */
retval = target_write_u32(target, 0x200b8004, 0x0);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
/* MLC_ADDR = row */
retval = target_write_u32(target, 0x200b8004, page & 0xff);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
retval = target_write_u32(target, 0x200b8004,
(page >> 8) & 0xff);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
@@ -629,7 +629,7 @@ static int lpc32xx_write_page_mlc(struct nand_device *nand, uint32_t page,
if (nand->address_cycles == 4) {
retval = target_write_u32(target, 0x200b8004,
(page >> 16) & 0xff);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
@@ -637,25 +637,25 @@ static int lpc32xx_write_page_mlc(struct nand_device *nand, uint32_t page,
} else {
/* MLC_ADDR = 0x0 (two column cycles) */
retval = target_write_u32(target, 0x200b8004, 0x0);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
retval = target_write_u32(target, 0x200b8004, 0x0);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
/* MLC_ADDR = row */
retval = target_write_u32(target, 0x200b8004, page & 0xff);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
retval = target_write_u32(target, 0x200b8004,
(page >> 8) & 0xff);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
@@ -687,27 +687,27 @@ static int lpc32xx_write_page_mlc(struct nand_device *nand, uint32_t page,
/* write MLC_ECC_ENC_REG to start encode cycle */
retval = target_write_u32(target, 0x200b8008, 0x0);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ECC_ENC_REG");
return ERROR_NAND_OPERATION_FAILED;
}
retval = target_write_memory(target, 0x200a8000,
4, 128, page_buffer);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_BUF (data)");
return ERROR_NAND_OPERATION_FAILED;
}
retval = target_write_memory(target, 0x200a8000,
1, 6, oob_buffer);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_BUF (oob)");
return ERROR_NAND_OPERATION_FAILED;
}
/* write MLC_ECC_AUTO_ENC_REG to start auto encode */
retval = target_write_u32(target, 0x200b8010, 0x0);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_ECC_AUTO_ENC_REG");
return ERROR_NAND_OPERATION_FAILED;
}
@@ -721,7 +721,7 @@ static int lpc32xx_write_page_mlc(struct nand_device *nand, uint32_t page,
/* MLC_CMD = auto program command */
retval = target_write_u32(target, 0x200b8000, NAND_CMD_PAGEPROG);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("could not set MLC_CMD");
return ERROR_NAND_OPERATION_FAILED;
}
@@ -901,14 +901,14 @@ static int lpc32xx_start_slc_dma(struct nand_device *nand, uint32_t count,
/* DMACIntTCClear = ch0 */
retval = target_write_u32(target, 0x31000008, 1);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not set DMACIntTCClear");
return retval;
}
/* DMACIntErrClear = ch0 */
retval = target_write_u32(target, 0x31000010, 1);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not set DMACIntErrClear");
return retval;
}
@@ -926,28 +926,28 @@ static int lpc32xx_start_slc_dma(struct nand_device *nand, uint32_t count,
retval = target_write_u32(target, 0x31000110,
1 | 1<<1 | 1<<6 | 2<<11 | 0<<14
| 0<<15 | 0<<16 | 0<<18);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not set DMACC0Config");
return retval;
}
/* SLC_CTRL = 3 (START DMA), ECC_CLEAR */
retval = target_write_u32(target, 0x20020010, 0x3);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not set SLC_CTRL");
return retval;
}
/* SLC_ICR = 2, INT_TC_CLR, clear pending TC*/
retval = target_write_u32(target, 0x20020028, 2);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not set SLC_ICR");
return retval;
}
/* SLC_TC */
retval = target_write_u32(target, 0x20020030, count);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("lpc32xx_start_slc_dma: Could not set SLC_TC");
return retval;
}
@@ -974,13 +974,13 @@ static int lpc32xx_dma_ready(struct nand_device *nand, int timeout)
/* Read DMACRawIntTCStat */
retval = target_read_u32(target, 0x31000014, &tc_stat);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not read DMACRawIntTCStat");
return 0;
}
/* Read DMACRawIntErrStat */
retval = target_read_u32(target, 0x31000018, &err_stat);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not read DMACRawIntErrStat");
return 0;
}
@@ -1065,13 +1065,13 @@ static int lpc32xx_write_page_slc(struct nand_device *nand,
retval = target_write_memory(target, target_mem_base, 4,
nll * sizeof(struct dmac_ll) / 4,
(uint8_t *)dmalist);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not write DMA descriptors to IRAM");
return retval;
}
retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("NAND_CMD_SEQIN failed");
return retval;
}
@@ -1085,7 +1085,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand,
WIDTH = bus_width
*/
retval = target_write_u32(target, 0x20020014, 0x3c);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not set SLC_CFG");
return retval;
}
@@ -1097,7 +1097,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand,
retval = target_write_memory(target,
target_mem_base + DATA_OFFS,
4, nand->page_size/4, fdata);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not write data to IRAM");
return retval;
}
@@ -1106,7 +1106,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand,
retval = target_write_memory(target, 0x31000100, 4,
sizeof(struct dmac_ll) / 4,
(uint8_t *)dmalist);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not write DMA descriptor to DMAC");
return retval;
}
@@ -1115,7 +1115,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand,
int tot_size = nand->page_size;
tot_size += tot_size == 2048 ? 64 : 16;
retval = lpc32xx_start_slc_dma(nand, tot_size, 0);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("DMA failed");
return retval;
}
@@ -1139,7 +1139,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand,
static uint32_t hw_ecc[8];
retval = target_read_memory(target, target_mem_base + ECC_OFFS,
4, ecc_count, (uint8_t *)hw_ecc);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Reading hw generated ECC from IRAM failed");
return retval;
}
@@ -1154,7 +1154,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand,
}
retval = target_write_memory(target, target_mem_base + SPARE_OFFS, 4,
foob_size / 4, foob);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Writing OOB to IRAM failed");
return retval;
}
@@ -1163,7 +1163,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand,
retval = target_write_memory(target, 0x31000100, 4,
sizeof(struct dmac_ll) / 4,
(uint8_t *)(&dmalist[nll-1]));
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not write OOB DMA descriptor to DMAC");
return retval;
}
@@ -1173,7 +1173,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand,
/* DMACIntTCClear = ch0 */
retval = target_write_u32(target, 0x31000008, 1);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not set DMACIntTCClear");
return retval;
}
@@ -1190,7 +1190,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand,
retval = target_write_u32(target, 0x31000110,
1 | 1<<1 | 1<<6 | 2<<11 | 0<<14
| 0<<15 | 0<<16 | 0<<18);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("Could not set DMACC0Config");
return retval;
}
@@ -1203,7 +1203,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand,
} else {
/* Start xfer of data from iram to flash using DMA */
retval = lpc32xx_start_slc_dma(nand, foob_size, 1);
- if (ERROR_OK != retval) {
+ if (retval != ERROR_OK) {
LOG_ERROR("DMA OOB failed");
return retval;
}
@@ -1211,7 +...
[truncated message content] |
