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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.11.0-238-g3d135a5c7
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From: OpenOCD-Gerrit <ope...@us...> - 2021-07-02 16:11:05
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- Log -----------------------------------------------------------------
commit 3d135a5c70db67ed13cc93eeab0b700f6ef8a412
Author: Antonio Borneo <bor...@gm...>
Date: Mon Apr 26 23:53:42 2021 +0200
flash: rename CamelCase symbols
Each driver is almost self-contained, with no cross dependency.
Changing symbol names in one drive does not impact the other.
Change-Id: Ic09f844f922a35cf0a9dc23fcd61d035b38308b3
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/6299
Tested-by: jenkins
Reviewed-by: Marc Schink <de...@za...>
diff --git a/src/flash/nand/at91sam9.c b/src/flash/nand/at91sam9.c
index 234dd70c1..534f20ede 100644
--- a/src/flash/nand/at91sam9.c
+++ b/src/flash/nand/at91sam9.c
@@ -25,13 +25,13 @@
#include "imp.h"
#include "arm_io.h"
-#define AT91C_PIOx_SODR (0x30) /**< Offset to PIO SODR. */
-#define AT91C_PIOx_CODR (0x34) /**< Offset to PIO CODR. */
-#define AT91C_PIOx_PDSR (0x3C) /**< Offset to PIO PDSR. */
-#define AT91C_ECCx_CR (0x00) /**< Offset to ECC CR. */
-#define AT91C_ECCx_SR (0x08) /**< Offset to ECC SR. */
-#define AT91C_ECCx_PR (0x0C) /**< Offset to ECC PR. */
-#define AT91C_ECCx_NPR (0x10) /**< Offset to ECC NPR. */
+#define AT91C_PIOX_SODR (0x30) /**< Offset to PIO SODR. */
+#define AT91C_PIOX_CODR (0x34) /**< Offset to PIO CODR. */
+#define AT91C_PIOX_PDSR (0x3C) /**< Offset to PIO PDSR. */
+#define AT91C_ECCX_CR (0x00) /**< Offset to ECC CR. */
+#define AT91C_ECCX_SR (0x08) /**< Offset to ECC SR. */
+#define AT91C_ECCX_PR (0x0C) /**< Offset to ECC PR. */
+#define AT91C_ECCX_NPR (0x10) /**< Offset to ECC NPR. */
/**
* Representation of a pin on an AT91SAM9 chip.
@@ -113,7 +113,7 @@ static int at91sam9_enable(struct nand_device *nand)
struct at91sam9_nand *info = nand->controller_priv;
struct target *target = nand->target;
- return target_write_u32(target, info->ce.pioc + AT91C_PIOx_CODR, 1 << info->ce.num);
+ return target_write_u32(target, info->ce.pioc + AT91C_PIOX_CODR, 1 << info->ce.num);
}
/**
@@ -127,7 +127,7 @@ static int at91sam9_disable(struct nand_device *nand)
struct at91sam9_nand *info = nand->controller_priv;
struct target *target = nand->target;
- return target_write_u32(target, info->ce.pioc + AT91C_PIOx_SODR, 1 << info->ce.num);
+ return target_write_u32(target, info->ce.pioc + AT91C_PIOX_SODR, 1 << info->ce.num);
}
/**
@@ -237,7 +237,7 @@ static int at91sam9_nand_ready(struct nand_device *nand, int timeout)
return 0;
do {
- target_read_u32(target, info->busy.pioc + AT91C_PIOx_PDSR, &status);
+ target_read_u32(target, info->busy.pioc + AT91C_PIOX_PDSR, &status);
if (status & (1 << info->busy.num))
return 1;
@@ -311,7 +311,7 @@ static int at91sam9_ecc_init(struct target *target, struct at91sam9_nand *info)
}
/* reset ECC parity registers */
- return target_write_u32(target, info->ecc + AT91C_ECCx_CR, 1);
+ return target_write_u32(target, info->ecc + AT91C_ECCX_CR, 1);
}
/**
@@ -384,7 +384,7 @@ static int at91sam9_read_page(struct nand_device *nand, uint32_t page,
oob_data = at91sam9_oob_init(nand, oob, &oob_size);
retval = nand_read_data_page(nand, oob_data, oob_size);
if (ERROR_OK == retval && data) {
- target_read_u32(target, info->ecc + AT91C_ECCx_SR, &status);
+ target_read_u32(target, info->ecc + AT91C_ECCX_SR, &status);
if (status & 1) {
LOG_ERROR("Error detected!");
if (status & 4)
@@ -394,7 +394,7 @@ static int at91sam9_read_page(struct nand_device *nand, uint32_t page,
uint32_t parity;
target_read_u32(target,
- info->ecc + AT91C_ECCx_PR,
+ info->ecc + AT91C_ECCX_PR,
&parity);
uint32_t word = (parity & 0x0000FFF0) >> 4;
uint32_t bit = parity & 0x0F;
@@ -462,8 +462,8 @@ static int at91sam9_write_page(struct nand_device *nand, uint32_t page,
if (!oob) {
/* no OOB given, so read in the ECC parity from the ECC controller */
- target_read_u32(target, info->ecc + AT91C_ECCx_PR, &parity);
- target_read_u32(target, info->ecc + AT91C_ECCx_NPR, &nparity);
+ target_read_u32(target, info->ecc + AT91C_ECCX_PR, &parity);
+ target_read_u32(target, info->ecc + AT91C_ECCX_NPR, &nparity);
oob_data[0] = (uint8_t) parity;
oob_data[1] = (uint8_t) (parity >> 8);
diff --git a/src/flash/nand/lpc32xx.c b/src/flash/nand/lpc32xx.c
index f117eadcc..3e2add49b 100644
--- a/src/flash/nand/lpc32xx.c
+++ b/src/flash/nand/lpc32xx.c
@@ -90,7 +90,7 @@ NAND_DEVICE_COMMAND_HANDLER(lpc32xx_nand_device_command)
"1000 and 20000 kHz, was %i",
lpc32xx_info->osc_freq);
- lpc32xx_info->selected_controller = LPC32xx_NO_CONTROLLER;
+ lpc32xx_info->selected_controller = LPC32XX_NO_CONTROLLER;
lpc32xx_info->sw_write_protection = 0;
lpc32xx_info->sw_wp_lower_bound = 0x0;
lpc32xx_info->sw_wp_upper_bound = 0x0;
@@ -222,13 +222,13 @@ static int lpc32xx_init(struct nand_device *nand)
}
/* select MLC controller if none is currently selected */
- if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_DEBUG("no LPC32xx NAND flash controller selected, "
"using default 'slc'");
- lpc32xx_info->selected_controller = LPC32xx_SLC_CONTROLLER;
+ lpc32xx_info->selected_controller = LPC32XX_SLC_CONTROLLER;
}
- if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
uint32_t mlc_icr_value = 0x0;
float cycle;
int twp, twh, trp, treh, trhz, trbwb, tcea;
@@ -304,7 +304,7 @@ static int lpc32xx_init(struct nand_device *nand)
retval = lpc32xx_reset(nand);
if (ERROR_OK != retval)
return ERROR_NAND_OPERATION_FAILED;
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
float cycle;
int r_setup, r_hold, r_width, r_rdy;
int w_setup, w_hold, w_width, w_rdy;
@@ -401,10 +401,10 @@ static int lpc32xx_reset(struct nand_device *nand)
return ERROR_NAND_OPERATION_FAILED;
}
- if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
- } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
/* MLC_CMD = 0xff (reset controller and NAND device) */
retval = target_write_u32(target, 0x200b8000, 0xff);
if (ERROR_OK != retval) {
@@ -417,7 +417,7 @@ static int lpc32xx_reset(struct nand_device *nand)
"after reset");
return ERROR_NAND_OPERATION_TIMEOUT;
}
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
/* SLC_CTRL = 0x6 (ECC_CLEAR, SW_RESET) */
retval = target_write_u32(target, 0x20020010, 0x6);
if (ERROR_OK != retval) {
@@ -447,17 +447,17 @@ static int lpc32xx_command(struct nand_device *nand, uint8_t command)
return ERROR_NAND_OPERATION_FAILED;
}
- if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
- } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
/* MLC_CMD = command */
retval = target_write_u32(target, 0x200b8000, command);
if (ERROR_OK != retval) {
LOG_ERROR("could not set MLC_CMD");
return ERROR_NAND_OPERATION_FAILED;
}
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
/* SLC_CMD = command */
retval = target_write_u32(target, 0x20020008, command);
if (ERROR_OK != retval) {
@@ -481,17 +481,17 @@ static int lpc32xx_address(struct nand_device *nand, uint8_t address)
return ERROR_NAND_OPERATION_FAILED;
}
- if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
- } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
/* MLC_ADDR = address */
retval = target_write_u32(target, 0x200b8004, address);
if (ERROR_OK != retval) {
LOG_ERROR("could not set MLC_ADDR");
return ERROR_NAND_OPERATION_FAILED;
}
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
/* SLC_ADDR = address */
retval = target_write_u32(target, 0x20020004, address);
if (ERROR_OK != retval) {
@@ -515,17 +515,17 @@ static int lpc32xx_write_data(struct nand_device *nand, uint16_t data)
return ERROR_NAND_OPERATION_FAILED;
}
- if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
- } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
/* MLC_DATA = data */
retval = target_write_u32(target, 0x200b0000, data);
if (ERROR_OK != retval) {
LOG_ERROR("could not set MLC_DATA");
return ERROR_NAND_OPERATION_FAILED;
}
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
/* SLC_DATA = data */
retval = target_write_u32(target, 0x20020000, data);
if (ERROR_OK != retval) {
@@ -549,10 +549,10 @@ static int lpc32xx_read_data(struct nand_device *nand, void *data)
return ERROR_NAND_OPERATION_FAILED;
}
- if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
- } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
/* data = MLC_DATA, use sized access */
if (nand->bus_width == 8) {
uint8_t *data8 = data;
@@ -565,7 +565,7 @@ static int lpc32xx_read_data(struct nand_device *nand, void *data)
LOG_ERROR("could not read MLC_DATA");
return ERROR_NAND_OPERATION_FAILED;
}
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
uint32_t data32;
/* data = SLC_DATA, must use 32-bit access */
@@ -1233,10 +1233,10 @@ static int lpc32xx_write_page(struct nand_device *nand, uint32_t page,
return ERROR_NAND_OPERATION_FAILED;
}
- if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
- } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
if (!data && oob) {
LOG_ERROR("LPC32xx MLC controller can't write "
"OOB data only");
@@ -1256,7 +1256,7 @@ static int lpc32xx_write_page(struct nand_device *nand, uint32_t page,
retval = lpc32xx_write_page_mlc(nand, page, data, data_size,
oob, oob_size);
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
struct working_area *pworking_area;
if (!data && oob) {
/*
@@ -1584,17 +1584,17 @@ static int lpc32xx_read_page(struct nand_device *nand, uint32_t page,
return ERROR_NAND_OPERATION_FAILED;
}
- if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_NO_CONTROLLER) {
LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
return ERROR_NAND_OPERATION_FAILED;
- } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
if (data_size > (uint32_t)nand->page_size) {
LOG_ERROR("data size exceeds page size");
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
}
retval = lpc32xx_read_page_mlc(nand, page, data, data_size,
oob, oob_size);
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
struct working_area *pworking_area;
retval = target_alloc_working_area(target,
@@ -1628,7 +1628,7 @@ static int lpc32xx_controller_ready(struct nand_device *nand, int timeout)
LOG_DEBUG("lpc32xx_controller_ready count start=%d", timeout);
do {
- if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
uint8_t status;
/* Read MLC_ISR, wait for controller to become ready */
@@ -1643,7 +1643,7 @@ static int lpc32xx_controller_ready(struct nand_device *nand, int timeout)
timeout);
return 1;
}
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
uint32_t status;
/* Read SLC_STAT and check READY bit */
@@ -1681,7 +1681,7 @@ static int lpc32xx_nand_ready(struct nand_device *nand, int timeout)
LOG_DEBUG("lpc32xx_nand_ready count start=%d", timeout);
do {
- if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
+ if (lpc32xx_info->selected_controller == LPC32XX_MLC_CONTROLLER) {
uint8_t status = 0x0;
/* Read MLC_ISR, wait for NAND flash device to
@@ -1697,7 +1697,7 @@ static int lpc32xx_nand_ready(struct nand_device *nand, int timeout)
timeout);
return 1;
}
- } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
+ } else if (lpc32xx_info->selected_controller == LPC32XX_SLC_CONTROLLER) {
uint32_t status = 0x0;
/* Read SLC_STAT and check READY bit */
@@ -1770,10 +1770,10 @@ COMMAND_HANDLER(handle_lpc32xx_select_command)
if (CMD_ARGC >= 2) {
if (strcmp(CMD_ARGV[1], "mlc") == 0) {
lpc32xx_info->selected_controller =
- LPC32xx_MLC_CONTROLLER;
+ LPC32XX_MLC_CONTROLLER;
} else if (strcmp(CMD_ARGV[1], "slc") == 0) {
lpc32xx_info->selected_controller =
- LPC32xx_SLC_CONTROLLER;
+ LPC32XX_SLC_CONTROLLER;
} else
return ERROR_COMMAND_SYNTAX_ERROR;
}
diff --git a/src/flash/nand/lpc32xx.h b/src/flash/nand/lpc32xx.h
index 90b20b247..12c8f48e6 100644
--- a/src/flash/nand/lpc32xx.h
+++ b/src/flash/nand/lpc32xx.h
@@ -20,9 +20,9 @@
#define OPENOCD_FLASH_NAND_LPC32XX_H
enum lpc32xx_selected_controller {
- LPC32xx_NO_CONTROLLER,
- LPC32xx_MLC_CONTROLLER,
- LPC32xx_SLC_CONTROLLER,
+ LPC32XX_NO_CONTROLLER,
+ LPC32XX_MLC_CONTROLLER,
+ LPC32XX_SLC_CONTROLLER,
};
struct lpc32xx_nand_controller {
diff --git a/src/flash/nand/s3c24xx_regs.h b/src/flash/nand/s3c24xx_regs.h
index 88bc66567..46bda6bfe 100644
--- a/src/flash/nand/s3c24xx_regs.h
+++ b/src/flash/nand/s3c24xx_regs.h
@@ -61,7 +61,7 @@
#define S3C2410_NFCONF_512BYTE (1 << 14)
#define S3C2410_NFCONF_4STEP (1 << 13)
#define S3C2410_NFCONF_INITECC (1 << 12)
-#define S3C2410_NFCONF_nFCE (1 << 11)
+#define S3C2410_NFCONF_NFCE (1 << 11)
#define S3C2410_NFCONF_TACLS(x) ((x) << 8)
#define S3C2410_NFCONF_TWRPH0(x) ((x) << 4)
#define S3C2410_NFCONF_TWRPH1(x) ((x) << 0)
@@ -83,12 +83,12 @@
#define S3C2440_NFCONT_SPARE_ECCLOCK (1 << 6)
#define S3C2440_NFCONT_MAIN_ECCLOCK (1 << 5)
#define S3C2440_NFCONT_INITECC (1 << 4)
-#define S3C2440_NFCONT_nFCE (1 << 1)
+#define S3C2440_NFCONT_NFCE (1 << 1)
#define S3C2440_NFCONT_ENABLE (1 << 0)
#define S3C2440_NFSTAT_READY (1 << 0)
-#define S3C2440_NFSTAT_nCE (1 << 1)
-#define S3C2440_NFSTAT_RnB_CHANGE (1 << 2)
+#define S3C2440_NFSTAT_NCE (1 << 1)
+#define S3C2440_NFSTAT_RNB_CHANGE (1 << 2)
#define S3C2440_NFSTAT_ILLEGAL_ACCESS (1 << 3)
#define S3C2412_NFCONF_NANDBOOT (1 << 31)
@@ -103,16 +103,16 @@
#define S3C2412_NFCONT_ECC4_DECINT (1 << 12)
#define S3C2412_NFCONT_MAIN_ECC_LOCK (1 << 7)
#define S3C2412_NFCONT_INIT_MAIN_ECC (1 << 5)
-#define S3C2412_NFCONT_nFCE1 (1 << 2)
-#define S3C2412_NFCONT_nFCE0 (1 << 1)
+#define S3C2412_NFCONT_NFCE1 (1 << 2)
+#define S3C2412_NFCONT_NFCE0 (1 << 1)
#define S3C2412_NFSTAT_ECC_ENCDONE (1 << 7)
#define S3C2412_NFSTAT_ECC_DECDONE (1 << 6)
#define S3C2412_NFSTAT_ILLEGAL_ACCESS (1 << 5)
-#define S3C2412_NFSTAT_RnB_CHANGE (1 << 4)
-#define S3C2412_NFSTAT_nFCE1 (1 << 3)
-#define S3C2412_NFSTAT_nFCE0 (1 << 2)
-#define S3C2412_NFSTAT_Res1 (1 << 1)
+#define S3C2412_NFSTAT_RNB_CHANGE (1 << 4)
+#define S3C2412_NFSTAT_NFCE1 (1 << 3)
+#define S3C2412_NFSTAT_NFCE0 (1 << 2)
+#define S3C2412_NFSTAT_RES1 (1 << 1)
#define S3C2412_NFSTAT_READY (1 << 0)
#define S3C2412_NFECCERR_SERRDATA(x) (((x) >> 21) & 0xf)
diff --git a/src/flash/nor/aduc702x.c b/src/flash/nor/aduc702x.c
index b7d2299f7..492b65813 100644
--- a/src/flash/nor/aduc702x.c
+++ b/src/flash/nor/aduc702x.c
@@ -31,15 +31,15 @@ static int aduc702x_build_sector_list(struct flash_bank *bank);
static int aduc702x_check_flash_completion(struct target *target, unsigned int timeout_ms);
static int aduc702x_set_write_enable(struct target *target, int enable);
-#define ADUC702x_FLASH 0xfffff800
-#define ADUC702x_FLASH_FEESTA (0*4)
-#define ADUC702x_FLASH_FEEMOD (1*4)
-#define ADUC702x_FLASH_FEECON (2*4)
-#define ADUC702x_FLASH_FEEDAT (3*4)
-#define ADUC702x_FLASH_FEEADR (4*4)
-#define ADUC702x_FLASH_FEESIGN (5*4)
-#define ADUC702x_FLASH_FEEPRO (6*4)
-#define ADUC702x_FLASH_FEEHIDE (7*4)
+#define ADUC702X_FLASH 0xfffff800
+#define ADUC702X_FLASH_FEESTA (0*4)
+#define ADUC702X_FLASH_FEEMOD (1*4)
+#define ADUC702X_FLASH_FEECON (2*4)
+#define ADUC702X_FLASH_FEEDAT (3*4)
+#define ADUC702X_FLASH_FEEADR (4*4)
+#define ADUC702X_FLASH_FEESIGN (5*4)
+#define ADUC702X_FLASH_FEEPRO (6*4)
+#define ADUC702X_FLASH_FEEHIDE (7*4)
/* flash bank aduc702x 0 0 0 0 <target#>
* The ADC7019-28 devices all have the same flash layout */
@@ -87,9 +87,9 @@ static int aduc702x_erase(struct flash_bank *bank, unsigned int first,
/* mass erase */
if (((first | last) == 0) || ((first == 0) && (last >= bank->num_sectors))) {
LOG_DEBUG("performing mass erase.");
- target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEDAT, 0x3cff);
- target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEADR, 0xffc3);
- target_write_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEECON, 0x06);
+ target_write_u16(target, ADUC702X_FLASH + ADUC702X_FLASH_FEEDAT, 0x3cff);
+ target_write_u16(target, ADUC702X_FLASH + ADUC702X_FLASH_FEEADR, 0xffc3);
+ target_write_u8(target, ADUC702X_FLASH + ADUC702X_FLASH_FEECON, 0x06);
if (aduc702x_check_flash_completion(target, 3500) != ERROR_OK) {
LOG_ERROR("mass erase failed");
@@ -106,8 +106,8 @@ static int aduc702x_erase(struct flash_bank *bank, unsigned int first,
for (x = 0; x < count; ++x) {
adr = bank->base + ((first + x) * 512);
- target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEADR, adr);
- target_write_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEECON, 0x05);
+ target_write_u16(target, ADUC702X_FLASH + ADUC702X_FLASH_FEEADR, adr);
+ target_write_u8(target, ADUC702X_FLASH + ADUC702X_FLASH_FEECON, 0x05);
if (aduc702x_check_flash_completion(target, 50) != ERROR_OK) {
LOG_ERROR("failed to erase sector at address 0x%08lX", adr);
@@ -283,7 +283,7 @@ static int aduc702x_write_single(struct flash_bank *bank,
for (x = 0; x < count; x += 2) {
/* FEEADR = address */
- target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEADR, offset + x);
+ target_write_u16(target, ADUC702X_FLASH + ADUC702X_FLASH_FEEADR, offset + x);
/* set up data */
if ((x + 1) == count) {
@@ -292,10 +292,10 @@ static int aduc702x_write_single(struct flash_bank *bank,
} else
b = buffer[x + 1];
- target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEDAT, buffer[x] | (b << 8));
+ target_write_u16(target, ADUC702X_FLASH + ADUC702X_FLASH_FEEDAT, buffer[x] | (b << 8));
/* do single-write command */
- target_write_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEECON, 0x02);
+ target_write_u8(target, ADUC702X_FLASH + ADUC702X_FLASH_FEECON, 0x02);
if (aduc702x_check_flash_completion(target, 1) != ERROR_OK) {
LOG_ERROR("single write failed for address 0x%08lX",
@@ -345,7 +345,7 @@ static int aduc702x_probe(struct flash_bank *bank)
static int aduc702x_set_write_enable(struct target *target, int enable)
{
/* don't bother to preserve int enable bit here */
- target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEMOD, enable ? 8 : 0);
+ target_write_u16(target, ADUC702X_FLASH + ADUC702X_FLASH_FEEMOD, enable ? 8 : 0);
return ERROR_OK;
}
@@ -361,7 +361,7 @@ static int aduc702x_check_flash_completion(struct target *target, unsigned int t
int64_t endtime = timeval_ms() + timeout_ms;
while (1) {
- target_read_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEESTA, &v);
+ target_read_u8(target, ADUC702X_FLASH + ADUC702X_FLASH_FEESTA, &v);
if ((v & 4) == 0)
break;
alive_sleep(1);
diff --git a/src/flash/nor/ambiqmicro.c b/src/flash/nor/ambiqmicro.c
index c4c69ce2b..162e1bb78 100644
--- a/src/flash/nor/ambiqmicro.c
+++ b/src/flash/nor/ambiqmicro.c
@@ -123,7 +123,7 @@ static struct {
uint8_t class;
uint8_t partno;
const char *partname;
-} ambiqmicroParts[6] = {
+} ambiqmicro_parts[6] = {
{0xFF, 0x00, "Unknown"},
{0x01, 0x00, "Apollo"},
{0x02, 0x00, "Apollo2"},
@@ -132,7 +132,7 @@ static struct {
{0x05, 0x00, "Apollo"},
};
-static char *ambiqmicroClassname[6] = {
+static char *ambiqmicro_classname[6] = {
"Unknown", "Apollo", "Apollo2", "Unknown", "Unknown", "Apollo"
};
@@ -172,10 +172,10 @@ static int get_ambiqmicro_info(struct flash_bank *bank, struct command_invocatio
}
/* Check class name in range. */
- if (ambiqmicro_info->target_class < sizeof(ambiqmicroClassname))
- classname = ambiqmicroClassname[ambiqmicro_info->target_class];
+ if (ambiqmicro_info->target_class < sizeof(ambiqmicro_classname))
+ classname = ambiqmicro_classname[ambiqmicro_info->target_class];
else
- classname = ambiqmicroClassname[0];
+ classname = ambiqmicro_classname[0];
command_print_sameline(cmd, "\nAmbiq Micro information: Chip is "
"class %d (%s) %s\n",
@@ -195,24 +195,24 @@ static int ambiqmicro_read_part_info(struct flash_bank *bank)
{
struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
struct target *target = bank->target;
- uint32_t PartNum = 0;
+ uint32_t part_num = 0;
int retval;
/*
* Read Part Number.
*/
- retval = target_read_u32(target, 0x40020000, &PartNum);
+ retval = target_read_u32(target, 0x40020000, &part_num);
if (retval != ERROR_OK) {
- LOG_ERROR("status(0x%x):Could not read PartNum.\n", retval);
- /* Set PartNum to default device */
- PartNum = 0;
+ LOG_ERROR("status(0x%x):Could not read part_num.\n", retval);
+ /* Set part_num to default device */
+ part_num = 0;
}
- LOG_DEBUG("Part number: 0x%" PRIx32, PartNum);
+ LOG_DEBUG("Part number: 0x%" PRIx32, part_num);
/*
* Determine device class.
*/
- ambiqmicro_info->target_class = (PartNum & 0xFF000000) >> 24;
+ ambiqmicro_info->target_class = (part_num & 0xFF000000) >> 24;
switch (ambiqmicro_info->target_class) {
case 1: /* 1 - Apollo */
@@ -220,9 +220,9 @@ static int ambiqmicro_read_part_info(struct flash_bank *bank)
bank->base = bank->bank_number * 0x40000;
ambiqmicro_info->pagesize = 2048;
ambiqmicro_info->flshsiz =
- apollo_flash_size[(PartNum & 0x00F00000) >> 20];
+ apollo_flash_size[(part_num & 0x00F00000) >> 20];
ambiqmicro_info->sramsiz =
- apollo_sram_size[(PartNum & 0x000F0000) >> 16];
+ apollo_sram_size[(part_num & 0x000F0000) >> 16];
ambiqmicro_info->num_pages = ambiqmicro_info->flshsiz /
ambiqmicro_info->pagesize;
if (ambiqmicro_info->num_pages > 128) {
@@ -248,12 +248,12 @@ static int ambiqmicro_read_part_info(struct flash_bank *bank)
}
- if (ambiqmicro_info->target_class < ARRAY_SIZE(ambiqmicroParts))
+ if (ambiqmicro_info->target_class < ARRAY_SIZE(ambiqmicro_parts))
ambiqmicro_info->target_name =
- ambiqmicroParts[ambiqmicro_info->target_class].partname;
+ ambiqmicro_parts[ambiqmicro_info->target_class].partname;
else
ambiqmicro_info->target_name =
- ambiqmicroParts[0].partname;
+ ambiqmicro_parts[0].partname;
LOG_DEBUG("num_pages: %" PRIu32 ", pagesize: %" PRIu32 ", flash: %" PRIu32 ", sram: %" PRIu32,
ambiqmicro_info->num_pages,
diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c
index e0c779a33..15ca29628 100644
--- a/src/flash/nor/at91sam3.c
+++ b/src/flash/nor/at91sam3.c
@@ -104,10 +104,10 @@
#define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
#define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
-#define offset_EFC_FMR 0
-#define offset_EFC_FCR 4
-#define offset_EFC_FSR 8
-#define offset_EFC_FRR 12
+#define OFFSET_EFC_FMR 0
+#define OFFSET_EFC_FCR 4
+#define OFFSET_EFC_FSR 8
+#define OFFSET_EFC_FRR 12
extern const struct flash_driver at91sam3_flash;
@@ -191,13 +191,13 @@ struct sam3_bank_private {
/* DANGER: THERE ARE DRAGONS HERE.. */
/* NOTE: If you add more 'ghost' pointers */
/* be aware that you must *manually* update */
- /* these pointers in the function sam3_GetDetails() */
+ /* these pointers in the function sam3_get_details() */
/* See the comment "Here there be dragons" */
/* so we can find the chip we belong to */
- struct sam3_chip *pChip;
+ struct sam3_chip *chip;
/* so we can find the original bank pointer */
- struct flash_bank *pBank;
+ struct flash_bank *bank;
unsigned bank_number;
uint32_t controller_address;
uint32_t base_address;
@@ -214,7 +214,7 @@ struct sam3_chip_details {
/* note: If you add pointers here */
/* be careful about them as they */
/* may need to be updated inside */
- /* the function: "sam3_GetDetails() */
+ /* the function: "sam3_get_details() */
/* which copy/overwrites the */
/* 'runtime' copy of this structure */
uint32_t chipid_cidr;
@@ -244,7 +244,7 @@ struct sam3_chip {
struct sam3_reg_list {
uint32_t address; size_t struct_offset; const char *name;
- void (*explain_func)(struct sam3_chip *pInfo);
+ void (*explain_func)(struct sam3_chip *chip);
};
static struct sam3_chip *all_sam3_chips;
@@ -277,7 +277,7 @@ static struct sam3_chip *get_current_sam3(struct command_invocation *cmd)
return NULL;
}
-/* these are used to *initialize* the "pChip->details" structure. */
+/* these are used to *initialize* the "chip->details" structure. */
static const struct sam3_chip_details all_sam3_details[] = {
/* Start at91sam3u* series */
{
@@ -307,8 +307,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
@@ -323,8 +323,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_U,
.controller_address = 0x400e0a00,
@@ -358,8 +358,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
@@ -400,8 +400,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
@@ -449,8 +449,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
/* .bank[0] = { */
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
@@ -464,8 +464,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_U,
.controller_address = 0x400e0a00,
@@ -499,8 +499,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
@@ -541,8 +541,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
@@ -579,8 +579,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
@@ -612,8 +612,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
@@ -644,8 +644,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
@@ -676,8 +676,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
@@ -708,8 +708,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
@@ -740,8 +740,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_SD,
.controller_address = 0x400e0a00,
@@ -755,8 +755,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_512K_SD,
.controller_address = 0x400e0a00,
@@ -780,8 +780,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_SD,
.controller_address = 0x400e0a00,
@@ -795,8 +795,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_512K_SD,
.controller_address = 0x400e0a00,
@@ -820,8 +820,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_SD,
.controller_address = 0x400e0a00,
@@ -835,8 +835,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_512K_SD,
.controller_address = 0x400e0a00,
@@ -860,8 +860,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
@@ -892,8 +892,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
@@ -924,8 +924,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
@@ -956,8 +956,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
@@ -988,8 +988,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
@@ -1020,8 +1020,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
@@ -1052,8 +1052,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
@@ -1102,8 +1102,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
@@ -1151,8 +1151,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
@@ -1200,8 +1200,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
@@ -1249,8 +1249,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
@@ -1298,8 +1298,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
@@ -1347,8 +1347,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
@@ -1396,8 +1396,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
@@ -1445,8 +1445,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
@@ -1494,8 +1494,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
@@ -1528,8 +1528,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
@@ -1562,8 +1562,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
@@ -1596,8 +1596,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
@@ -1630,8 +1630,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
@@ -1681,8 +1681,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_AX,
.controller_address = 0x400e0a00,
@@ -1696,8 +1696,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_512K_AX,
.controller_address = 0x400e0c00,
@@ -1722,8 +1722,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_AX,
.controller_address = 0x400e0a00,
@@ -1737,8 +1737,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_256K_AX,
.controller_address = 0x400e0c00,
@@ -1781,8 +1781,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_AX,
.controller_address = 0x400e0a00,
@@ -1796,8 +1796,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_512K_AX,
.controller_address = 0x400e0c00,
@@ -1823,8 +1823,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_AX,
.controller_address = 0x400e0a00,
@@ -1838,8 +1838,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_512K_AX,
.controller_address = 0x400e0c00,
@@ -1864,8 +1864,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_AX,
.controller_address = 0x400e0a00,
@@ -1879,8 +1879,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_512K_AX,
.controller_address = 0x400e0c00,
@@ -1905,8 +1905,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_AX,
.controller_address = 0x400e0a00,
@@ -1920,8 +1920,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_512K_AX,
.controller_address = 0x400e0c00,
@@ -1946,8 +1946,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_AX,
.controller_address = 0x400e0a00,
@@ -1961,8 +1961,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_256K_AX,
.controller_address = 0x400e0c00,
@@ -1987,8 +1987,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_AX,
.controller_address = 0x400e0a00,
@@ -2002,8 +2002,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.probed = false,
- .pChip = NULL,
- .pBank = NULL,
+ .chip = NULL,
+ .bank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_256K_AX,
.controller_address = 0x400e0c00,
@@ -2036,14 +2036,14 @@ static const struct sam3_chip_details all_sam3_details[] = {
/**
* Get the current status of the EEFC and
* the value of some status bits (LOCKE, PROGE).
- * @param pPrivate - info about the bank
+ * @param private - info about the bank
* @param v - result goes here
*/
-static int EFC_GetStatus(struct sam3_bank_private *pPrivate, uint32_t *v)
+static int efc_get_status(struct sam3_bank_private *private, uint32_t *v)
{
int r;
- r = target_read_u32(pPrivate->pChip->target,
- pPrivate->controller_address + offset_EFC_FSR,
+ r = target_read_u32(private->chip->target,
+ private->controller_address + OFFSET_EFC_FSR,
v);
LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
(unsigned int)(*v),
@@ -2056,15 +2056,15 @@ static int EFC_GetStatus(struct sam3_bank_private *pPrivate, uint32_t *v)
/**
* Get the result of the last executed command.
- * @param pPrivate - info about the bank
+ * @param private - info about the bank
* @param v - result goes here
*/
-static int EFC_GetResult(struct sam3_bank_private *pPrivate, uint32_t *v)
+static int efc_get_result(struct sam3_bank_private *private, uint32_t *v)
{
int r;
uint32_t rv;
- r = target_read_u32(pPrivate->pChip->target,
- pPrivate->controller_address + offset_EFC_FRR,
+ r = target_read_u32(private->chip->target,
+ private->controller_address + OFFSET_EFC_FRR,
&rv);
if (v)
*v = rv;
@@ -2072,7 +2072,7 @@ static int EFC_GetResult(struct sam3_bank_private *pPrivate, uint32_t *v)
return r;
}
-static int EFC_StartCommand(struct sam3_bank_private *pPrivate,
+static int efc_start_command(struct sam3_bank_private *private,
unsigned command, unsigned argument)
{
uint32_t n, v;
@@ -2093,16 +2093,16 @@ do_retry:
/* case AT91C_EFC_FCMD_EPA: */
case AT91C_EFC_FCMD_SLB:
case AT91C_EFC_FCMD_CLB:
- n = (pPrivate->size_bytes / pPrivate->page_size);
+ n = (private->size_bytes / private->page_size);
if (argument >= n)
LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
break;
case AT91C_EFC_FCMD_SFB:
case AT91C_EFC_FCMD_CFB:
- if (argument >= pPrivate->pChip->details.n_gpnvms) {
+ if (argument >= private->chip->details.n_gpnvms) {
LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
- pPrivate->pChip->details.n_gpnvms);
+ private->chip->details.n_gpnvms);
}
break;
@@ -2127,7 +2127,7 @@ do_retry:
/* Situation (2) - normal, finished reading unique id */
} else {
/* it should be "ready" */
- EFC_GetStatus(pPrivate, &v);
+ efc_get_status(private, &v);
if (v & 1) {
/* then it is ready */
/* we go on */
@@ -2136,14 +2136,14 @@ do_retry:
/* we have done this before */
/* the controller is not responding. */
LOG_ERROR("flash controller(%d) is not ready! Error",
- pPrivate->bank_number);
+ private->bank_number);
return ERROR_FAIL;
} else {
retry++;
LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
- pPrivate->bank_number);
+ private->bank_number);
/* we do that by issuing the *STOP* command */
- EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
+ efc_start_command(private, AT91C_EFC_FCMD_SPUI, 0);
/* above is recursive, and further recursion is blocked by */
/* if (command == AT91C_EFC_FCMD_SPUI) above */
goto do_retry;
@@ -2153,8 +2153,8 @@ do_retry:
v = (0x5A << 24) | (argument << 8) | command;
LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
- r = target_write_u32(pPrivate->pBank->target,
- pPrivate->controller_address + offset_EFC_FCR, v);
+ r = target_write_u32(private->bank->target,
+ private->controller_address + OFFSET_EFC_FCR, v);
if (r != ERROR_OK)
LOG_DEBUG("Error Write failed");
return r;
@@ -2162,12 +2162,12 @@ do_retry:
/**
* Performs the given command and wait until its completion (or an error).
- * @param pPrivate - info about the bank
+ * @param private - info about the bank
* @param command - Command to perform.
* @param argument - Optional command argument.
* @param status - put command status bits here
*/
-static int EFC_PerformCommand(struct sam3_bank_private *pPrivate,
+static int efc_perform_command(struct sam3_bank_private *private,
unsigned command,
unsigned argument,
uint32_t *status)
@@ -2181,14 +2181,14 @@ static int EFC_PerformCommand(struct sam3_bank_private *pPrivate,
if (status)
*status = 0;
- r = EFC_StartCommand(pPrivate, command, argument);
+ r = efc_start_command(private, command, argument);
if (r != ERROR_OK)
return r;
ms_end = 500 + timeval_ms();
do {
- r = EFC_GetStatus(pPrivate, &v);
+ r = efc_get_status(private, &v);
if (r != ERROR_OK)
return r;
ms_now = timeval_ms();
@@ -2208,87 +2208,87 @@ static int EFC_PerformCommand(struct sam3_bank_private *pPrivate,
/**
* Read the unique ID.
- * @param pPrivate - info about the bank
- * The unique ID is stored in the 'pPrivate' structure.
+ * @param private - info about the bank
+ * The unique ID is stored in the 'private' structure.
*/
-static int FLASHD_ReadUniqueID(struct sam3_bank_private *pPrivate)
+static int flashd_read_uid(struct sam3_bank_private *private)
{
int r;
uint32_t v;
int x;
/* assume 0 */
- pPrivate->pChip->cfg.unique_id[0] = 0;
- pPrivate->pChip->cfg.unique_id[1] = 0;
- pPrivate->pChip->cfg.unique_id[2] = 0;
- pPrivate->pChip->cfg.unique_id[3] = 0;
+ private->chip->cfg.unique_id[0] = 0;
+ private->chip->cfg.unique_id[1] = 0;
+ private->chip->cfg.unique_id[2] = 0;
+ private->chip->cfg.unique_id[3] = 0;
LOG_DEBUG("Begin");
- r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
+ r = efc_start_command(private, AT91C_EFC_FCMD_STUI, 0);
if (r < 0)
return r;
for (x = 0; x < 4; x++) {
- r = target_read_u32(pPrivate->pChip->target,
- pPrivate->pBank->base + (x * 4),
+ r = target_read_u32(private->chip->target,
+ private->bank->base + (x * 4),
&v);
if (r < 0)
return r;
- pPrivate->pChip->cfg.unique_id[x] = v;
+ private->chip->cfg.unique_id[x] = v;
}
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_SPUI, 0, NULL);
LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
r,
- (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
- (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
- (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
- (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
+ (unsigned int)(private->chip->cfg.unique_id[0]),
+ (unsigned int)(private->chip->cfg.unique_id[1]),
+ (unsigned int)(private->chip->cfg.unique_id[2]),
+ (unsigned int)(private->chip->cfg.unique_id[3]));
return r;
}
/**
* Erases the entire flash.
- * @param pPrivate - the info about the bank.
+ * @param private - the info about the bank.
*/
-static int FLASHD_EraseEntireBank(struct sam3_bank_private *pPrivate)
+static int flashd_erase_entire_bank(struct sam3_bank_private *private)
{
LOG_DEBUG("Here");
- return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
+ return efc_perform_command(private, AT91C_EFC_FCMD_EA, 0, NULL);
}
/**
* Gets current GPNVM state.
- * @param pPrivate - info about the bank.
+ * @param private - info about the bank.
* @param gpnvm - GPNVM bit index.
* @param puthere - result stored here.
*/
/* ------------------------------------------------------------------------------ */
-static int FLASHD_GetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
+static int flashd_get_gpnvm(struct sam3_bank_private *private, unsigned gpnvm, unsigned *puthere)
{
uint32_t v;
int r;
LOG_DEBUG("Here");
- if (pPrivate->bank_number != 0) {
+ if (private->bank_number != 0) {
LOG_ERROR("GPNVM only works with Bank0");
return ERROR_FAIL;
}
- if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
+ if (gpnvm >= private->chip->details.n_gpnvms) {
LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
- gpnvm, pPrivate->pChip->details.n_gpnvms);
+ gpnvm, private->chip->details.n_gpnvms);
return ERROR_FAIL;
}
/* Get GPNVMs status */
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_GFB, 0, NULL);
if (r != ERROR_OK) {
LOG_ERROR("Failed");
return r;
}
- r = EFC_GetResult(pPrivate, &v);
+ r = efc_get_result(private, &v);
if (puthere) {
/* Check if GPNVM is set */
@@ -2301,59 +2301,59 @@ static int FLASHD_GetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm, u
/**
* Clears the selected GPNVM bit.
- * @param pPrivate info about the bank
+ * @param private info about the bank
* @param gpnvm GPNVM index.
* @returns 0 if successful; otherwise returns an error code.
*/
-static int FLASHD_ClrGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
+static int flashd_clr_gpnvm(struct sam3_bank_private *private, unsigned gpnvm)
{
int r;
unsigned v;
LOG_DEBUG("Here");
- if (pPrivate->bank_number != 0) {
+ if (private->bank_number != 0) {
LOG_ERROR("GPNVM only works with Bank0");
return ERROR_FAIL;
}
- if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
+ if (gpnvm >= private->chip->details.n_gpnvms) {
LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
- gpnvm, pPrivate->pChip->details.n_gpnvms);
+ gpnvm, private->chip->details.n_gpnvms);
return ERROR_FAIL;
}
- r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
+ r = flashd_get_gpnvm(private, gpnvm, &v);
if (r != ERROR_OK) {
LOG_DEBUG("Failed: %d", r);
return r;
}
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
LOG_DEBUG("End: %d", r);
return r;
}
/**
* Sets the selected GPNVM bit.
- * @param pPrivate info about the bank
+ * @param private info about the bank
* @param gpnvm GPNVM index.
*/
-static int FLASHD_SetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
+static int flashd_set_gpnvm(struct sam3_bank_private *private, unsigned gpnvm)
{
int r;
unsigned v;
- if (pPrivate->bank_number != 0) {
+ if (private->bank_number != 0) {
LOG_ERROR("GPNVM only works with Bank0");
return ERROR_FAIL;
}
- if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
+ if (gpnvm >= private->chip->details.n_gpnvms) {
LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
- gpnvm, pPrivate->pChip->details.n_gpnvms);
+ gpnvm, private->chip->details.n_gpnvms);
return ERROR_FAIL;
}
- r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
+ r = flashd_get_gpnvm(private, gpnvm, &v);
if (r != ERROR_OK)
return r;
if (v) {
@@ -2361,35 +2361,35 @@ static int FLASHD_SetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
r = ERROR_OK;
} else {
/* set it */
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
}
return r;
}
/**
* Returns a bit field (at most 64) of locked regions within a page.
- * @param pPrivate info about the bank
+ * @param private info about the bank
* @param v where to store locked bits
*/
-static int FLASHD_GetLockBits(struct sam3_bank_private *pPrivate, uint32_t *v)
+static int flashd_get_lock_bits(struct sam3_bank_private *private, uint32_t *v)
{
int r;
LOG_DEBUG("Here");
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_GLB, 0, NULL);
if (r == ERROR_OK)
- r = EFC_GetResult(pPrivate, v);
+ r = efc_get_result(private, v);
LOG_DEBUG("End: %d", r);
return r;
}
/**
* Unlocks all the regions in the given address range.
- * @param pPrivate info about the bank
+ * @param private info about the bank
* @param start_sector first sector to unlock
* @param end_sector last (inclusive) to unlock
*/
-static int FLASHD_Unlock(struct sam3_bank_private *pPrivate,
+static int flashd_unlock(struct sam3_bank_private *private,
unsigned start_sector,
unsigned end_sector)
{
@@ -2398,13 +2398,13 @@ static int FLASHD_Unlock(struct sam3_bank_private *pPrivate,
uint32_t pg;
uint32_t pages_per_sector;
- pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
+ pages_per_sector = private->sector_size / private->page_size;
/* Unlock all pages */
while (start_sector <= end_sector) {
pg = start_sector * pages_per_sector;
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_CLB, pg, &status);
if (r != ERROR_OK)
return r;
start_sector++;
@@ -2415,11 +2415,11 @@ static int FLASHD_Unlock(struct sam3_bank_private *pPrivate,
/**
* Locks regions
- * @param pPrivate - info about the bank
+ * @param private - info about the bank
* @param start_sector - first sector to lock
* @param end_sector - last sector (inclusive) to lock
*/
-static int FLASHD_Lock(struct sam3_bank_private *pPrivate,
+static int flashd_lock(struct sam3_bank_private *private,
unsigned start_sector,
unsigned end_sector)
{
@@ -2428,13 +2428,13 @@ static int FLASHD_Lock(struct sam3_bank_private *pPrivate,
uint32_t pages_per_sector;
int r;
- pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
+ pages_per_sector = private->sector_size / private->page_size;
/* Lock all pages */
while (start_sector <= end_sector) {
pg = start_sector * pages_per_sector;
- r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
+ r = efc_perform_command(private, AT91C_EFC_FCMD_SLB, pg, &status);
if (r != ERROR_OK)
return r;
start_sector++;
@@ -2446,7 +2446,7 @@ static int FLASHD_Lock(struct sam3_bank_private *pPrivate,
/* begin helpful debug code */
/* print the fieldname, the field value, in dec & hex, and return field value */
-static uint32_t sam3_reg_fieldname(struct sam3_chip *pChip,
+static uint32_t sam3_reg_fieldname(struct sam3_chip *chip,
const char *regname,
uint32_t value,
unsigned shift,
@@ -2598,72 +2598,72 @@ static const char *const _rc_freq[] = {
"4 MHz", "8 MHz", "12 MHz", "reserved"
};
-static void sam3_explain_ckgr_mor(struct sam3_chip *pChip)
+static void sam3_explain_ckgr_mor(struct sam3_chip *chip)
{
uint32_t v;
uint32_t rcen;
- v = sam3_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
+ v = sam3_reg_fieldname(chip, "MOSCXTEN", chip->cfg.CKGR_MOR, 0, 1);
LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
- v = sam3_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
+ v = sam3_reg_fieldname(chip, "MOSCXTBY", chip->cfg.CKGR_MOR, 1, 1);
LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
- rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
+ rcen = sam3_reg_fieldname(chip, "MOSCRCEN", chip->cfg.CKGR_MOR, 3, 1);
LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
- v = sam3_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
+ v = sam3_reg_fieldname(chip, "MOSCRCF", chip->cfg.CKGR_MOR, 4, 3);
LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
- pChip->cfg.rc_freq = 0;
+ chip->cfg.rc_freq = 0;
if (rcen) {
switch (v) {
default:
- pChip->cfg.rc_freq = 0;
+ chip->cfg.rc_freq = 0;
break;
case 0:
- pChip->cfg.rc_freq = 4 * 1000 * 1000;
+ chip->cfg.rc_freq = 4 * 1000 * 1000;
break;
case 1:
- pChip->cfg.rc_freq = 8 * 1000 * 1000;
+ chip->cfg.rc_freq = 8 * 1000 * 1000;
break;
...
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