[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.11.0-179-g4e872a797

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- Log -----------------------------------------------------------------
commit 4e872a797f81595d5de790138bdec62f2bf175f0
Author: Olivier DANET <od...@ca...>
Date:   Mon May 17 14:47:14 2021 +0200

    target/zynqmp : Add AXI AP access port
    
    The Xilinx Zynq UltraScale+ SoC have an "AXI-AP" access port for direct memory accesses without halting CPUs.
    
    Change-Id: I6303331c217795657575de4759444938e775dee1
    Signed-off-by: Olivier DANET <od...@ca...>
    Reviewed-on: http://openocd.zylin.com/6263
    Reviewed-by: Tarek BOCHKATI <tar...@gm...>
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/target/xilinx_zynqmp.cfg b/tcl/target/xilinx_zynqmp.cfg
index b21603f62..e66289a70 100644
--- a/tcl/target/xilinx_zynqmp.cfg
+++ b/tcl/target/xilinx_zynqmp.cfg
@@ -92,6 +92,8 @@ for { set _core 0 } { $_core < $_cores } { incr _core } {
     eval $_command
 }
 
+target create uscale.axi mem_ap -dap uscale.dap -ap-num 0
+
 eval $_smp_command
 targets $_TARGETNAME.0
 

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/xilinx_zynqmp.cfg | 2 ++
 1 file changed, 2 insertions(+)


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