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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.11.0-178-g036de3b48
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From: OpenOCD-Gerrit <ope...@us...> - 2021-05-22 09:12:39
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- Log -----------------------------------------------------------------
commit 036de3b48217e9c0b5ec0bbf6638e9cad6cae517
Author: Antonio Borneo <bor...@gm...>
Date: Sun May 16 14:02:53 2021 +0200
riscv: replace macro DIM() with ARRAY_SIZE()
OpenOCD already defines the macro ARRAY_SIZE, while riscv code
uses a local macro DIM.
Prefer using the macro ARRAY_SIZE() instead of DIM().
Not all the riscv code has been upstreamed, yes; this patch only
covers the code already upstreamed.
Change-Id: I89a58a6d91916d85c53ba5e4091b558271f8d618
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/6258
Reviewed-by: Xiang W <wx...@12...>
Tested-by: jenkins
Reviewed-by: Tim Newsome <ti...@si...>
diff --git a/src/target/riscv/riscv-011.c b/src/target/riscv/riscv-011.c
index 9b5f7491b..7a5e990ca 100644
--- a/src/target/riscv/riscv-011.c
+++ b/src/target/riscv/riscv-011.c
@@ -70,8 +70,6 @@
#define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
#define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
-#define DIM(x) (sizeof(x)/sizeof(*x))
-
/* Constants for legacy SiFive hardware breakpoints. */
#define CSR_BPCONTROL_X (1<<0)
#define CSR_BPCONTROL_W (1<<1)
@@ -1634,7 +1632,7 @@ static riscv_error_t handle_halt_routine(struct target *target)
/* Read S0 from dscratch */
unsigned int csr[] = {CSR_DSCRATCH0, CSR_DPC, CSR_DCSR};
- for (unsigned int i = 0; i < DIM(csr); i++) {
+ for (unsigned int i = 0; i < ARRAY_SIZE(csr); i++) {
scans_add_write32(scans, 0, csrr(S0, csr[i]), true);
scans_add_read(scans, SLOT0, false);
}
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c
index 32a7f0248..b70c259dc 100644
--- a/src/target/riscv/riscv-013.c
+++ b/src/target/riscv/riscv-013.c
@@ -86,8 +86,6 @@ static int riscv013_test_compliance(struct target *target);
#define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
#define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
-#define DIM(x) (sizeof(x)/sizeof(*x))
-
#define CSR_DCSR_CAUSE_SWBP 1
#define CSR_DCSR_CAUSE_TRIGGER 2
#define CSR_DCSR_CAUSE_DEBUGINT 3
@@ -358,7 +356,7 @@ static void decode_dmi(char *text, unsigned address, unsigned data)
};
text[0] = 0;
- for (unsigned i = 0; i < DIM(description); i++) {
+ for (unsigned i = 0; i < ARRAY_SIZE(description); i++) {
if (description[i].address == address) {
uint64_t mask = description[i].mask;
unsigned value = get_field(data, mask);
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index 7b7b7284d..fa07fe821 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -23,8 +23,6 @@
#define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
#define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
-#define DIM(x) (sizeof(x)/sizeof(*x))
-
/* Constants for legacy SiFive hardware breakpoints. */
#define CSR_BPCONTROL_X (1<<0)
#define CSR_BPCONTROL_W (1<<1)
@@ -184,10 +182,10 @@ struct scan_field _bscan_tunnel_nested_tap_select_dmi[] = {
}
};
struct scan_field *bscan_tunnel_nested_tap_select_dmi = _bscan_tunnel_nested_tap_select_dmi;
-uint32_t bscan_tunnel_nested_tap_select_dmi_num_fields = DIM(_bscan_tunnel_nested_tap_select_dmi);
+uint32_t bscan_tunnel_nested_tap_select_dmi_num_fields = ARRAY_SIZE(_bscan_tunnel_nested_tap_select_dmi);
struct scan_field *bscan_tunnel_data_register_select_dmi = _bscan_tunnel_data_register_select_dmi;
-uint32_t bscan_tunnel_data_register_select_dmi_num_fields = DIM(_bscan_tunnel_data_register_select_dmi);
+uint32_t bscan_tunnel_data_register_select_dmi_num_fields = ARRAY_SIZE(_bscan_tunnel_data_register_select_dmi);
struct trigger {
uint64_t address;
@@ -348,8 +346,8 @@ uint32_t dtmcontrol_scan_via_bscan(struct target *target, uint32_t out)
tunneled_dr[0].in_value = NULL;
}
jtag_add_ir_scan(target->tap, &select_user4, TAP_IDLE);
- jtag_add_dr_scan(target->tap, DIM(tunneled_ir), tunneled_ir, TAP_IDLE);
- jtag_add_dr_scan(target->tap, DIM(tunneled_dr), tunneled_dr, TAP_IDLE);
+ jtag_add_dr_scan(target->tap, ARRAY_SIZE(tunneled_ir), tunneled_ir, TAP_IDLE);
+ jtag_add_dr_scan(target->tap, ARRAY_SIZE(tunneled_dr), tunneled_dr, TAP_IDLE);
select_dmi_via_bscan(target);
int retval = jtag_execute_queue();
@@ -1788,7 +1786,7 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
GDB_REGNO_PC,
GDB_REGNO_MSTATUS, GDB_REGNO_MEPC, GDB_REGNO_MCAUSE,
};
- for (unsigned i = 0; i < DIM(regnums); i++) {
+ for (unsigned i = 0; i < ARRAY_SIZE(regnums); i++) {
enum gdb_regno regno = regnums[i];
riscv_reg_t reg_value;
if (riscv_get_register(target, ®_value, regno) != ERROR_OK)
@@ -3768,7 +3766,7 @@ int riscv_init_registers(struct target *target)
#undef DECLARE_CSR
};
/* encoding.h does not contain the registers in sorted order. */
- qsort(csr_info, DIM(csr_info), sizeof(*csr_info), cmp_csr_info);
+ qsort(csr_info, ARRAY_SIZE(csr_info), sizeof(*csr_info), cmp_csr_info);
unsigned csr_info_index = 0;
unsigned custom_range_index = 0;
@@ -4028,7 +4026,7 @@ int riscv_init_registers(struct target *target)
unsigned csr_number = number - GDB_REGNO_CSR0;
while (csr_info[csr_info_index].number < csr_number &&
- csr_info_index < DIM(csr_info) - 1) {
+ csr_info_index < ARRAY_SIZE(csr_info) - 1) {
csr_info_index++;
}
if (csr_info[csr_info_index].number == csr_number) {
commit 8d207b5d2e034c94b7a989fcb20e90d496aa8c3b
Author: Antonio Borneo <bor...@gm...>
Date: Sun May 16 11:58:31 2021 +0200
riscv: drop unused variable
The array newly_halted[] is assigned but its value is never used.
Drop it!
Change-Id: I678812a31c45a3ec03716e3eee6a30b8e8947926
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/6257
Tested-by: jenkins
Reviewed-by: Xiang W <wx...@12...>
Reviewed-by: Tim Newsome <ti...@si...>
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index 1e93ded9e..7b7b7284d 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -2040,7 +2040,6 @@ int riscv_openocd_poll(struct target *target)
} else if (target->smp) {
unsigned halts_discovered = 0;
unsigned total_targets = 0;
- bool newly_halted[RISCV_MAX_HARTS] = {0};
unsigned should_remain_halted = 0;
unsigned should_resume = 0;
unsigned i = 0;
@@ -2049,7 +2048,6 @@ int riscv_openocd_poll(struct target *target)
total_targets++;
struct target *t = list->target;
riscv_info_t *r = riscv_info(t);
- assert(i < DIM(newly_halted));
enum riscv_poll_hart out = riscv_poll_hart(t, r->current_hartid);
switch (out) {
case RPH_NO_CHANGE:
@@ -2060,7 +2058,6 @@ int riscv_openocd_poll(struct target *target)
break;
case RPH_DISCOVERED_HALTED:
halts_discovered++;
- newly_halted[i] = true;
t->state = TARGET_HALTED;
enum riscv_halt_reason halt_reason =
riscv_halt_reason(t, r->current_hartid);
commit 2fe2cafe2028c9c3c6faf82b0a545d33f6344ace
Author: Antonio Borneo <bor...@gm...>
Date: Wed Jan 6 18:01:00 2021 +0100
mem_ap: fix target arch_info type
The target mem_ap appears as an ARM target, thus it allows the
execution of ARM specific commands causing the crash of OpenOCD.
E.g. 'arm mrc ...' can be executed and segfaults.
Replace the incorrect ARM magic number with a dedicated one.
While there, remove the 'struct arm', that is now holding only the
mem_ap's dap, and replace it with a pointer to the dap.
Change-Id: I881332d3fdf8d8f8271b8711607737b052a5699b
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/6213
Tested-by: jenkins
diff --git a/src/target/mem_ap.c b/src/target/mem_ap.c
index 89c0c02c0..0c3d7f78a 100644
--- a/src/target/mem_ap.c
+++ b/src/target/mem_ap.c
@@ -18,14 +18,16 @@
#include "target.h"
#include "target_type.h"
-#include "arm.h"
#include "arm_adi_v5.h"
#include "register.h"
#include <jtag/jtag.h>
+#define MEM_AP_COMMON_MAGIC 0x4DE4DA50
+
struct mem_ap {
- struct arm arm;
+ int common_magic;
+ struct adiv5_dap *dap;
struct adiv5_ap *ap;
int ap_num;
};
@@ -51,8 +53,8 @@ static int mem_ap_target_create(struct target *target, Jim_Interp *interp)
}
mem_ap->ap_num = pc->ap_num;
- mem_ap->arm.common_magic = ARM_COMMON_MAGIC;
- mem_ap->arm.dap = pc->dap;
+ mem_ap->common_magic = MEM_AP_COMMON_MAGIC;
+ mem_ap->dap = pc->dap;
target->arch_info = mem_ap;
@@ -137,7 +139,7 @@ static int mem_ap_examine(struct target *target)
struct mem_ap *mem_ap = target->arch_info;
if (!target_was_examined(target)) {
- mem_ap->ap = dap_ap(mem_ap->arm.dap, mem_ap->ap_num);
+ mem_ap->ap = dap_ap(mem_ap->dap, mem_ap->ap_num);
target_set_examined(target);
target->state = TARGET_UNKNOWN;
target->debug_reason = DBG_REASON_UNDEFINED;
-----------------------------------------------------------------------
Summary of changes:
src/target/mem_ap.c | 12 +++++++-----
src/target/riscv/riscv-011.c | 4 +---
src/target/riscv/riscv-013.c | 4 +---
src/target/riscv/riscv.c | 19 +++++++------------
4 files changed, 16 insertions(+), 23 deletions(-)
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