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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.11.0-144-gf855fdcf0
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From: OpenOCD-Gerrit <ope...@us...> - 2021-05-08 08:49:45
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- Log -----------------------------------------------------------------
commit f855fdcf0d95ff9ba18a83f9a97d5368844d4f2c
Author: Antonio Borneo <bor...@gm...>
Date: Sat Apr 10 17:37:04 2021 +0200
tcl: [2/3] prepare for jimtcl 0.81 'expr' syntax change
Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single
arg") drops the support for multi-argument syntax for the TCL
command 'expr'.
Enclose within double quote the argument of 'expr' when there is
the need to concatenate strings.
Change-Id: Ic0ea990ed37337a7e6c3a99670583685b570b8b1
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/6160
Tested-by: jenkins
diff --git a/tcl/chip/atmel/at91/rtt.tcl b/tcl/chip/atmel/at91/rtt.tcl
index 3e3d414f4..d49ce7114 100644
--- a/tcl/chip/atmel/at91/rtt.tcl
+++ b/tcl/chip/atmel/at91/rtt.tcl
@@ -17,7 +17,7 @@ proc show_RTTC_RTMR_helper { NAME ADDR VAL } {
global AT91C_SLOWOSC_FREQ
# Nasty hack, make this a float by tacking a .0 on the end
# otherwise, jim makes the value an integer
- set f [expr $AT91C_SLOWOSC_FREQ.0 / $rtpres.0]
+ set f [expr "$AT91C_SLOWOSC_FREQ.0 / $rtpres.0"]
echo [format "\tPrescale value: 0x%04x (%5d) => %f Hz" $rtpres $rtpres $f]
if { $VAL & $BIT16 } {
echo "\tBit16 -> Alarm IRQ Enabled"
diff --git a/tcl/chip/atmel/at91/usarts.tcl b/tcl/chip/atmel/at91/usarts.tcl
index 95aced882..f840b78c3 100644
--- a/tcl/chip/atmel/at91/usarts.tcl
+++ b/tcl/chip/atmel/at91/usarts.tcl
@@ -89,7 +89,7 @@ foreach WHO { US0 US1 US2 US3 US4 US5 US6 US7 US8 US9 } {
set vn [set WHO]_[set REG]
# vn = USx_IER
# vv = variable value
- set vv [expr $$n + [set USx_[set REG]]]
+ set vv [expr "$$n + [set USx_[set REG]]"]
# And VV is the address in memory of that register
diff --git a/tcl/fpga/xilinx-xadc.cfg b/tcl/fpga/xilinx-xadc.cfg
index 043e55393..c451ca2f2 100644
--- a/tcl/fpga/xilinx-xadc.cfg
+++ b/tcl/fpga/xilinx-xadc.cfg
@@ -101,7 +101,7 @@ proc xadc_select {tap} {
proc xadc_xfer {tap cmd addr data} {
set ret [drscan $tap 32 [xadc_cmd $cmd $addr $data]]
runtest 10
- return [expr 0x$ret]
+ return [expr "0x$ret"]
}
# XADC register write
diff --git a/tcl/target/u8500.cfg b/tcl/target/u8500.cfg
index 5ef98e9e1..15bacf308 100644
--- a/tcl/target/u8500.cfg
+++ b/tcl/target/u8500.cfg
@@ -52,9 +52,9 @@ proc pwrsts { } {
irscan $_CHIPNAME.jrc 0x3a
drscan $_CHIPNAME.jrc 4 0
set pwrsts [drscan $_CHIPNAME.jrc 16 0]
- echo "pwrsts ="$pwrsts
- set a9 [expr (0x$pwrsts & 0xc)]
- set ape [expr (0x$pwrsts & 0x3)]
+ echo "pwrsts ="$pwrsts
+ set a9 [expr "0x$pwrsts & 0xc"]
+ set ape [expr "0x$pwrsts & 0x3"]
if {[string equal "0" $ape]} {
echo "ape off"
} else {
@@ -81,12 +81,12 @@ proc poll_pwrsts { } {
irscan $_CHIPNAME.jrc 0x3a
drscan $_CHIPNAME.jrc 4 0
set pwrsts [drscan $_CHIPNAME.jrc 16 0]
- set pwrsts [expr (0x$pwrsts & 0xc)]
+ set pwrsts [expr "0x$pwrsts & 0xc"]
while {[string equal "4" $pwrsts] && $i<20} {
irscan $_CHIPNAME.jrc 0x3a
drscan $_CHIPNAME.jrc 4 0;
set pwrsts [drscan $_CHIPNAME.jrc 16 0]
- set pwrsts [expr (0x$pwrsts & 0xc)]
+ set pwrsts [expr "0x$pwrsts & 0xc"]
if {![string equal "4" $pwrsts]} {
set result 1
} else {
@@ -239,7 +239,7 @@ proc secsts1 { } {
drscan $_CHIPNAME.jrc 4 4
set secsts1 [drscan $_CHIPNAME.jrc 16 0]
echo "secsts1 ="$secsts1
- set secsts1 [expr (0x$secsts1 & 0x4)]
+ set secsts1 [expr "0x$secsts1 & 0x4"]
if {![string equal "4" $secsts1]} {
echo "APE target secured"
} else {
@@ -254,7 +254,7 @@ proc att { } {
drscan $_CHIPNAME.jrc 4 4
set secsts1 [drscan $_CHIPNAME.jrc 16 0]
echo "secsts1 ="$secsts1
- set secsts1 [expr (0x$secsts1 & 0x4)]
+ set secsts1 [expr "0x$secsts1 & 0x4"]
if {[string equal "4" $secsts1]} {
if {[poll_pwrsts]==1} {
enable_apetap
@@ -291,13 +291,13 @@ proc rst_run { } {
drscan $_CHIPNAME.jrc 4 4
set secsts1 [drscan $_CHIPNAME.jrc 16 0]
echo "secsts1 ="$secsts1
- set secsts1 [expr (0x$secsts1 & 0x4)]
+ set secsts1 [expr "0x$secsts1 & 0x4"]
while {![string equal "4" $secsts1]} {
irscan u8500.jrc 0x3a
drscan u8500.jrc 4 4
set secsts1 [drscan $_CHIPNAME.jrc 16 0]
echo "secsts1 ="$secsts1
- set secsts1 [expr (0x$secsts1 & 0x4)]
+ set secsts1 [expr "0x$secsts1 & 0x4"]
}
echo "ape debugable"
enable_apetap
commit f5657aa76e795e4ed5b13a9f5df943181a123e49
Author: Antonio Borneo <bor...@gm...>
Date: Sat Apr 10 01:23:57 2021 +0200
tcl: [1/3] prepare for jimtcl 0.81 'expr' syntax change
Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single
arg") drops the support for multi-argument syntax for the TCL
command 'expr'.
In the TCL scripts distributed with OpenOCD there are 1700+ lines
that should be modified before switching to jimtcl 0.81.
Apply the script below on every script in tcl folder. It fixes
more than 92% of the lines
%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---
#!/usr/bin/perl -Wpi
my $re_sym = qr{[a-z_][a-z0-9_]*}i;
my $re_var = qr{(?:\$|\$::)$re_sym};
my $re_const = qr{0x[0-9a-f]+|[0-9]+|[0-9]*\.[0-9]*}i;
my $re_item = qr{(?:~\s*)?(?:$re_var|$re_const)};
my $re_op = qr{<<|>>|[+\-*/&|]};
my $re_expr = qr{(
(?:\(\s*(?:$re_item|(?-1))\s*\)|$re_item)
\s*$re_op\s*
(?:$re_item|(?-1)|\(\s*(?:$re_item|(?-1))\s*\))
)}x;
# [expr [dict get $regsC100 SYM] + HEXNUM]
s/\[expr (\[dict get $re_var $re_sym\s*\] \+ *$re_const)\]/\[expr \{$1\}\]/;
# [ expr (EXPR) ]
# [ expr EXPR ]
# note: $re_expr captures '$3'
s/\[(\s*expr\s*)\((\s*$re_expr\s*)\)(\s*)\]/\[$1\{$2\}$4\]/;
s/\[(\s*expr\s*)($re_expr)(\s*)\]/\[$1\{$2\}$4\]/;
%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---
Change-Id: I0d6bddc6abf6dd29062f2b4e72b5a2b5080293b9
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/6159
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/tcl/bitsbytes.tcl b/tcl/bitsbytes.tcl
index 52ca83db2..5f9cae114 100644
--- a/tcl/bitsbytes.tcl
+++ b/tcl/bitsbytes.tcl
@@ -5,30 +5,30 @@
# Creat helper variables ...
# BIT0.. BIT31
-for { set x 0 } { $x < 32 } { set x [expr $x + 1]} {
+for { set x 0 } { $x < 32 } { set x [expr {$x + 1}]} {
set vn [format "BIT%d" $x]
global $vn
- set $vn [expr (1 << $x)]
+ set $vn [expr {1 << $x}]
}
# Create K bytes values
# __1K ... to __2048K
-for { set x 1 } { $x < 2048 } { set x [expr $x * 2]} {
+for { set x 1 } { $x < 2048 } { set x [expr {$x * 2}]} {
set vn [format "__%dK" $x]
global $vn
- set $vn [expr (1024 * $x)]
+ set $vn [expr {1024 * $x}]
}
# Create M bytes values
# __1M ... to __2048K
-for { set x 1 } { $x < 2048 } { set x [expr $x * 2]} {
+for { set x 1 } { $x < 2048 } { set x [expr {$x * 2}]} {
set vn [format "__%dM" $x]
global $vn
- set $vn [expr (1024 * 1024 * $x)]
+ set $vn [expr {1024 * 1024 * $x}]
}
proc create_mask { MSB LSB } {
- return [expr (((1 << ($MSB - $LSB + 1))-1) << $LSB)]
+ return [expr {((1 << ($MSB - $LSB + 1))-1) << $LSB}]
}
# Cut Bits $MSB to $LSB out of this value.
@@ -52,8 +52,8 @@ proc normalize_bitfield { VALUE MSB LSB } {
proc show_normalize_bitfield { VALUE MSB LSB } {
set m [create_mask $MSB $LSB]
- set mr [expr $VALUE & $m]
- set sr [expr $mr >> $LSB]
+ set mr [expr {$VALUE & $m}]
+ set sr [expr {$mr >> $LSB}]
echo [format "((0x%08x & 0x%08x) -> 0x%08x) >> %2d => (0x%x) %5d " $VALUE $m $mr $LSB $sr $sr]
return $sr
}
diff --git a/tcl/board/at91cap7a-stk-sdram.cfg b/tcl/board/at91cap7a-stk-sdram.cfg
index 8395ba33b..8a371e064 100644
--- a/tcl/board/at91cap7a-stk-sdram.cfg
+++ b/tcl/board/at91cap7a-stk-sdram.cfg
@@ -38,7 +38,7 @@ proc peek32 {address} {
# Wait for an expression to be true with a timeout
proc wait_state {expression} {
- for {set i 0} {$i < 1000} {set i [expr $i + 1]} {
+ for {set i 0} {$i < 1000} {set i [expr {$i + 1}]} {
if {[uplevel 1 $expression] == 0} {
return
}
diff --git a/tcl/board/at91sam9261-ek.cfg b/tcl/board/at91sam9261-ek.cfg
index 3963e9373..d6e8c2d15 100644
--- a/tcl/board/at91sam9261-ek.cfg
+++ b/tcl/board/at91sam9261-ek.cfg
@@ -30,29 +30,29 @@ proc at91sam9261ek_reset_init { } {
;# set master_pll_mul 13
set val [expr $::AT91_WDT_WDV] ;# Counter Value
- set val [expr ($val | $::AT91_WDT_WDDIS)] ;# Watchdog Disable
- set val [expr ($val | $::AT91_WDT_WDD)] ;# Delta Value
- set val [expr ($val | $::AT91_WDT_WDDBGHLT)] ;# Debug Halt
- set val [expr ($val | $::AT91_WDT_WDIDLEHLT)] ;# Idle Halt
+ set val [expr {$val | $::AT91_WDT_WDDIS}] ;# Watchdog Disable
+ set val [expr {$val | $::AT91_WDT_WDD}] ;# Delta Value
+ set val [expr {$val | $::AT91_WDT_WDDBGHLT}] ;# Debug Halt
+ set val [expr {$val | $::AT91_WDT_WDIDLEHLT}] ;# Idle Halt
set config(wdt_mr_val) $val
;# EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash
set config(matrix_ebicsa_addr) $::AT91_MATRIX_EBICSA
- set config(matrix_ebicsa_val) [expr ($::AT91_MATRIX_DBPUC | $::AT91_MATRIX_CS1A_SDRAMC)]
+ set config(matrix_ebicsa_val) [expr {$::AT91_MATRIX_DBPUC | $::AT91_MATRIX_CS1A_SDRAMC}]
;# SDRAMC_CR - Configuration register
set val [expr $::AT91_SDRAMC_NC_9]
- set val [expr ($val | $::AT91_SDRAMC_NR_13)]
- set val [expr ($val | $::AT91_SDRAMC_NB_4)]
- set val [expr ($val | $::AT91_SDRAMC_CAS_3)]
- set val [expr ($val | $::AT91_SDRAMC_DBW_32)]
- set val [expr ($val | (2 << 8))] ;# Write Recovery Delay
- set val [expr ($val | (7 << 12))] ;# Row Cycle Delay
- set val [expr ($val | (3 << 16))] ;# Row Precharge Delay
- set val [expr ($val | (2 << 20))] ;# Row to Column Delay
- set val [expr ($val | (5 << 24))] ;# Active to Precharge Delay
- set val [expr ($val | (8 << 28))] ;# Exit Self Refresh to Active Delay
+ set val [expr {$val | $::AT91_SDRAMC_NR_13}]
+ set val [expr {$val | $::AT91_SDRAMC_NB_4}]
+ set val [expr {$val | $::AT91_SDRAMC_CAS_3}]
+ set val [expr {$val | $::AT91_SDRAMC_DBW_32}]
+ set val [expr {$val | (2 << 8)}] ;# Write Recovery Delay
+ set val [expr {$val | (7 << 12)}] ;# Row Cycle Delay
+ set val [expr {$val | (3 << 16)}] ;# Row Precharge Delay
+ set val [expr {$val | (2 << 20)}] ;# Row to Column Delay
+ set val [expr {$val | (5 << 24)}] ;# Active to Precharge Delay
+ set val [expr {$val | (8 << 28)}] ;# Exit Self Refresh to Active Delay
set config(sdram_cr_val) $val
diff --git a/tcl/board/at91sam9263-ek.cfg b/tcl/board/at91sam9263-ek.cfg
index 645b1a7bd..b88efa971 100644
--- a/tcl/board/at91sam9263-ek.cfg
+++ b/tcl/board/at91sam9263-ek.cfg
@@ -25,10 +25,10 @@ proc at91sam9263ek_reset_init { } {
set config(master_pll_mul) 171
set val [expr $::AT91_WDT_WDV] ;# Counter Value
- set val [expr ($val | $::AT91_WDT_WDDIS)] ;# Watchdog Disable
- set val [expr ($val | $::AT91_WDT_WDD)] ;# Delta Value
- set val [expr ($val | $::AT91_WDT_WDDBGHLT)] ;# Debug Halt
- set val [expr ($val | $::AT91_WDT_WDIDLEHLT)] ;# Idle Halt
+ set val [expr {$val | $::AT91_WDT_WDDIS}] ;# Watchdog Disable
+ set val [expr {$val | $::AT91_WDT_WDD}] ;# Delta Value
+ set val [expr {$val | $::AT91_WDT_WDDBGHLT}] ;# Debug Halt
+ set val [expr {$val | $::AT91_WDT_WDIDLEHLT}] ;# Idle Halt
set config(wdt_mr_val) $val
@@ -37,22 +37,22 @@ proc at91sam9263ek_reset_init { } {
set config(matrix_ebicsa_addr) $::AT91_MATRIX_EBI0CSA
set val [expr $::AT91_MATRIX_EBI0_DBPUC]
- set val [expr ($val | $::AT91_MATRIX_EBI0_VDDIOMSEL_3_3V)]
- set val [expr ($val | $::AT91_MATRIX_EBI0_CS1A_SDRAMC)]
+ set val [expr {$val | $::AT91_MATRIX_EBI0_VDDIOMSEL_3_3V}]
+ set val [expr {$val | $::AT91_MATRIX_EBI0_CS1A_SDRAMC}]
set config(matrix_ebicsa_val) $val
;# SDRAMC_CR - Configuration register
set val [expr $::AT91_SDRAMC_NC_9]
- set val [expr ($val | $::AT91_SDRAMC_NR_13)]
- set val [expr ($val | $::AT91_SDRAMC_NB_4)]
- set val [expr ($val | $::AT91_SDRAMC_CAS_3)]
- set val [expr ($val | $::AT91_SDRAMC_DBW_32)]
- set val [expr ($val | (1 << 8))] ;# Write Recovery Delay
- set val [expr ($val | (7 << 12))] ;# Row Cycle Delay
- set val [expr ($val | (2 << 16))] ;# Row Precharge Delay
- set val [expr ($val | (2 << 20))] ;# Row to Column Delay
- set val [expr ($val | (5 << 24))] ;# Active to Precharge Delay
- set val [expr ($val | (1 << 28))] ;# Exit Self Refresh to Active Delay
+ set val [expr {$val | $::AT91_SDRAMC_NR_13}]
+ set val [expr {$val | $::AT91_SDRAMC_NB_4}]
+ set val [expr {$val | $::AT91_SDRAMC_CAS_3}]
+ set val [expr {$val | $::AT91_SDRAMC_DBW_32}]
+ set val [expr {$val | (1 << 8)}] ;# Write Recovery Delay
+ set val [expr {$val | (7 << 12)}] ;# Row Cycle Delay
+ set val [expr {$val | (2 << 16)}] ;# Row Precharge Delay
+ set val [expr {$val | (2 << 20)}] ;# Row to Column Delay
+ set val [expr {$val | (5 << 24)}] ;# Active to Precharge Delay
+ set val [expr {$val | (1 << 28)}] ;# Exit Self Refresh to Active Delay
set config(sdram_cr_val) $val
diff --git a/tcl/board/dm355evm.cfg b/tcl/board/dm355evm.cfg
index 0c971e9a0..1e35b68fa 100644
--- a/tcl/board/dm355evm.cfg
+++ b/tcl/board/dm355evm.cfg
@@ -80,7 +80,7 @@ proc dm355evm_init {} {
# VTPIOCR impedance calibration
set addr [dict get $dm355 sysbase]
- set addr [expr $addr + 0x70]
+ set addr [expr {$addr + 0x70}]
# clear CLR, LOCK, PWRDN; wait a clock; set CLR
mmw $addr 0 0x20c0
@@ -108,24 +108,24 @@ proc dm355evm_init {} {
set addr [dict get $dm355 ddr_emif]
# DDRPHYCR1
- mww [expr $addr + 0xe4] 0x50006404
+ mww [expr {$addr + 0xe4}] 0x50006404
# PBBPR -- burst priority
- mww [expr $addr + 0x20] 0xfe
+ mww [expr {$addr + 0x20}] 0xfe
# SDCR -- unlock boot config; init for DDR2, relock, unlock SDTIM*
- mmw [expr $addr + 0x08] 0x00800000 0
- mmw [expr $addr + 0x08] 0x0013c632 0x03870fff
+ mmw [expr {$addr + 0x08}] 0x00800000 0
+ mmw [expr {$addr + 0x08}] 0x0013c632 0x03870fff
# SDTIMR0, SDTIMR1
- mww [expr $addr + 0x10] 0x2a923249
- mww [expr $addr + 0x14] 0x4c17c763
+ mww [expr {$addr + 0x10}] 0x2a923249
+ mww [expr {$addr + 0x14}] 0x4c17c763
# SDCR -- relock SDTIM*
- mmw [expr $addr + 0x08] 0 0x00008000
+ mmw [expr {$addr + 0x08}] 0 0x00008000
# SDRCR -- refresh rate (171 MHz * 7.8usec)
- mww [expr $addr + 0x0c] 1336
+ mww [expr {$addr + 0x0c}] 1336
########################
# ASYNC EMIF
@@ -138,13 +138,13 @@ proc dm355evm_init {} {
#set nand_timings 0x0400008c
# AWCCR
- mww [expr $addr + 0x04] 0xff
+ mww [expr {$addr + 0x04}] 0xff
# CS0 == socketed NAND (default MT29F16G08FAA, 2GByte)
- mww [expr $addr + 0x10] $nand_timings
+ mww [expr {$addr + 0x10}] $nand_timings
# CS1 == dm9000 Ethernet
- mww [expr $addr + 0x14] 0x00a00505
+ mww [expr {$addr + 0x14}] 0x00a00505
# NANDFCR -- only CS0 has NAND
- mww [expr $addr + 0x60] 0x01
+ mww [expr {$addr + 0x60}] 0x01
# default: both chipselects to the NAND socket are used
nand probe 0
@@ -156,27 +156,27 @@ proc dm355evm_init {} {
set addr [dict get $dm355 uart0]
# PWREMU_MGNT -- rx + tx in reset
- mww [expr $addr + 0x30] 0
+ mww [expr {$addr + 0x30}] 0
# DLL, DLH -- 115200 baud
- mwb [expr $addr + 0x20] 0x0d
- mwb [expr $addr + 0x24] 0x00
+ mwb [expr {$addr + 0x20}] 0x0d
+ mwb [expr {$addr + 0x24}] 0x00
# FCR - clear and disable FIFOs
- mwb [expr $addr + 0x08] 0x07
- mwb [expr $addr + 0x08] 0x00
+ mwb [expr {$addr + 0x08}] 0x07
+ mwb [expr {$addr + 0x08}] 0x00
# IER - disable IRQs
- mwb [expr $addr + 0x04] 0x00
+ mwb [expr {$addr + 0x04}] 0x00
# LCR - 8-N-1
- mwb [expr $addr + 0x0c] 0x03
+ mwb [expr {$addr + 0x0c}] 0x03
# MCR - no flow control or loopback
- mwb [expr $addr + 0x10] 0x00
+ mwb [expr {$addr + 0x10}] 0x00
# PWREMU_MGNT -- rx + tx normal, free running during JTAG halt
- mww [expr $addr + 0x30] 0xe001
+ mww [expr {$addr + 0x30}] 0xe001
########################
diff --git a/tcl/board/dm365evm.cfg b/tcl/board/dm365evm.cfg
index 3b29dd866..8c7f8c0a6 100644
--- a/tcl/board/dm365evm.cfg
+++ b/tcl/board/dm365evm.cfg
@@ -56,10 +56,10 @@ if { $CS0 == "NAND" } {
#set nand_timings 0x0400008c
# CS0 == socketed NAND (default MT29F16G08FAA, 2 GBytes)
- mww [expr $a_emif + 0x10] $nand_timings
+ mww [expr {$a_emif + 0x10}] $nand_timings
# NANDFCR -- CS0 has NAND
- mww [expr $a_emif + 0x60] 0x01
+ mww [expr {$a_emif + 0x60}] 0x01
}
proc flashprobe {} {
nand probe 0
@@ -80,10 +80,10 @@ if { $CS0 == "NAND" } {
davinci_pinmux $dm365 2 0x00000055
# CS0 == OneNAND (KFG1G16U2B-DIB6, 128 KBytes)
- mww [expr $a_emif + 0x10] 0x00000001
+ mww [expr {$a_emif + 0x10}] 0x00000001
# ONENANDCTRL -- CS0 has OneNAND, enable sync reads
- mww [expr $a_emif + 0x5c] 0x0441
+ mww [expr {$a_emif + 0x5c}] 0x0441
}
proc flashprobe {} { }
}
@@ -133,11 +133,11 @@ proc dm365evm_init {} {
set a_emif [dict get $dm365 a_emif]
# AWCCR
- mww [expr $a_emif + 0x04] 0xff
+ mww [expr {$a_emif + 0x04}] 0xff
# CS0 == NAND or OneNAND
cs0_setup $a_emif
# CS1 == CPLD
- mww [expr $a_emif + 0x14] 0x00a00505
+ mww [expr {$a_emif + 0x14}] 0x00a00505
# FIXME setup UART0
diff --git a/tcl/board/embedded-artists_lpc2478-32.cfg b/tcl/board/embedded-artists_lpc2478-32.cfg
index 8ef9179de..abf0a5f22 100644
--- a/tcl/board/embedded-artists_lpc2478-32.cfg
+++ b/tcl/board/embedded-artists_lpc2478-32.cfg
@@ -26,7 +26,7 @@ proc init_board {} {
global _CHIPNAME
# A working area will help speeding the flash programming
- $_TARGETNAME configure -work-area-phys 0x40000200 -work-area-size [expr 0x10000-0x200-0x20] -work-area-backup 0
+ $_TARGETNAME configure -work-area-phys 0x40000200 -work-area-size [expr {0x10000-0x200-0x20}] -work-area-backup 0
# External 16-bit flash at chip select CS0 (SST39VF3201-70, 4 MiB)
flash bank $_CHIPNAME.extflash cfi 0x80000000 0x400000 2 2 $_TARGETNAME jedec_probe
diff --git a/tcl/board/icnova_imx53_sodimm.cfg b/tcl/board/icnova_imx53_sodimm.cfg
index af9818814..0a161f6cd 100644
--- a/tcl/board/icnova_imx53_sodimm.cfg
+++ b/tcl/board/icnova_imx53_sodimm.cfg
@@ -45,7 +45,7 @@ proc sodimm_init { } {
; # ARM errata ID #468414
set tR [arm mrc 15 0 1 0 1]
- arm mcr 15 0 1 0 1 [expr $tR | (1<<5)] ; # enable L1NEON bit
+ arm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}] ; # enable L1NEON bit
init_l2cc
init_aips
@@ -79,7 +79,7 @@ proc init_l2cc { } {
; #orr r0, r0, #(1 << 22) /* disable write allocate */
; #mcr 15, 1, r0, c9, c0, 2
- arm mcr 15 1 9 0 2 [expr 0xC4 | (1<<24) | (1<<23) | (1<<22)]
+ arm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}]
}
@@ -93,10 +93,10 @@ proc init_aips { } {
set VAL 0x77777777
# dap apsel 1
- mww [expr $AIPS1_BASE_ADDR + 0x0] $VAL
- mww [expr $AIPS1_BASE_ADDR + 0x4] $VAL
- mww [expr $AIPS2_BASE_ADDR + 0x0] $VAL
- mww [expr $AIPS2_BASE_ADDR + 0x4] $VAL
+ mww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL
+ mww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL
+ mww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL
+ mww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL
# dap apsel 0
}
@@ -104,22 +104,22 @@ proc init_aips { } {
proc init_clock { } {
global AIPS1_BASE_ADDR
global AIPS2_BASE_ADDR
- set CCM_BASE_ADDR [expr $AIPS1_BASE_ADDR + 0x000D4000]
+ set CCM_BASE_ADDR [expr {$AIPS1_BASE_ADDR + 0x000D4000}]
set CLKCTL_CCSR 0x0C
set CLKCTL_CBCDR 0x14
set CLKCTL_CBCMR 0x18
- set PLL1_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00080000]
- set PLL2_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00084000]
- set PLL3_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00088000]
- set PLL4_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x0008C000]
+ set PLL1_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00080000}]
+ set PLL2_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00084000}]
+ set PLL3_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00088000}]
+ set PLL4_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x0008C000}]
set CLKCTL_CSCMR1 0x1C
set CLKCTL_CDHIPR 0x48
- set PLATFORM_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x000A0000]
+ set PLATFORM_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x000A0000}]
set CLKCTL_CSCDR1 0x24
set CLKCTL_CCDR 0x04
; # Switch ARM to step clock
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x4
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4
return
echo "not returned"
@@ -127,52 +127,52 @@ proc init_clock { } {
setup_pll $PLL3_BASE_ADDR 400
; # Switch peripheral to PLL3
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00015154
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x02888945 | (1<<16)]
- while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 }
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}]
+ while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
setup_pll $PLL2_BASE_ADDR 400
; # Switch peripheral to PLL2
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x00808145 | (2<<10) | (9<<16) | (1<<19)]
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}]
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00016154
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154
; # change uart clk parent to pll2
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1]] & 0xfcffffff | 0x01000000]
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000]
; # make sure change is effective
- while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 }
+ while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
setup_pll $PLL3_BASE_ADDR 216
setup_pll $PLL4_BASE_ADDR 455
; # Set the platform clock dividers
- mww [expr $PLATFORM_BASE_ADDR + 0x14] 0x00000124
+ mww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124
- mww [expr $CCM_BASE_ADDR + 0x10] 0
+ mww [expr {$CCM_BASE_ADDR + 0x10}] 0
; # Switch ARM back to PLL 1.
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x0
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0
; # make uart div=6
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1]] & 0xffffffc0 | 0x0a]
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a]
; # Restore the default values in the Gate registers
- mww [expr $CCM_BASE_ADDR + 0x68] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x6C] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x70] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x74] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x78] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x7C] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x80] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x84] 0xFFFFFFFF
+ mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF
+ mww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF
+ mww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF
+ mww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF
+ mww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF
+ mww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF
+ mww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF
+ mww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CCDR] 0x00000
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000
; # for cko - for ARM div by 8
- mww [expr $CCM_BASE_ADDR + 0x60] [expr 0x000A0000 & 0x00000F0]
+ mww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}]
}
@@ -187,68 +187,68 @@ proc setup_pll { PLL_ADDR CLK } {
set PLL_DP_HFS_MFN 0x24
if {$CLK == 1000} {
- set DP_OP [expr (10 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (12 - 1)]
+ set DP_OP [expr {(10 << 4) + ((1 - 1) << 0)}]
+ set DP_MFD [expr {12 - 1}]
set DP_MFN 5
} elseif {$CLK == 850} {
- set DP_OP [expr (8 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (48 - 1)]
+ set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}]
+ set DP_MFD [expr {48 - 1}]
set DP_MFN 41
} elseif {$CLK == 800} {
- set DP_OP [expr (8 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (3 - 1)]
+ set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}]
+ set DP_MFD [expr {3 - 1}]
set DP_MFN 1
} elseif {$CLK == 700} {
- set DP_OP [expr (7 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (24 - 1)]
+ set DP_OP [expr {(7 << 4) + ((1 - 1) << 0)}]
+ set DP_MFD [expr {24 - 1}]
set DP_MFN 7
} elseif {$CLK == 600} {
- set DP_OP [expr (6 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (4 - 1)]
+ set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}]
+ set DP_MFD [expr {4 - 1}]
set DP_MFN 1
} elseif {$CLK == 665} {
- set DP_OP [expr (6 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (96 - 1)]
+ set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}]
+ set DP_MFD [expr {96 - 1}]
set DP_MFN 89
} elseif {$CLK == 532} {
- set DP_OP [expr (5 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (24 - 1)]
+ set DP_OP [expr {(5 << 4) + ((1 - 1) << 0)}]
+ set DP_MFD [expr {24 - 1}]
set DP_MFN 13
} elseif {$CLK == 455} {
- set DP_OP [expr (8 << 4) + ((2 - 1) << 0)]
- set DP_MFD [expr (48 - 1)]
+ set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}]
+ set DP_MFD [expr {48 - 1}]
set DP_MFN 71
} elseif {$CLK == 400} {
- set DP_OP [expr (8 << 4) + ((2 - 1) << 0)]
- set DP_MFD [expr (3 - 1)]
+ set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}]
+ set DP_MFD [expr {3 - 1}]
set DP_MFN 1
} elseif {$CLK == 216} {
- set DP_OP [expr (6 << 4) + ((3 - 1) << 0)]
- set DP_MFD [expr (4 - 1)]
+ set DP_OP [expr {(6 << 4) + ((3 - 1) << 0)}]
+ set DP_MFD [expr {4 - 1}]
set DP_MFN 3
} else {
error "Error (setup_dll): clock not found!"
}
- mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232
- mww [expr $PLL_ADDR + $PLL_DP_CONFIG] 0x2
+ mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
+ mww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2
- mww [expr $PLL_ADDR + $PLL_DP_OP] $DP_OP
- mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_OP
+ mww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP
+ mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP
- mww [expr $PLL_ADDR + $PLL_DP_MFD] $DP_MFD
- mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_MFD
+ mww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD
+ mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD
- mww [expr $PLL_ADDR + $PLL_DP_MFN] $DP_MFN
- mww [expr $PLL_ADDR + $PLL_DP_HFS_MFN] $DP_MFN
+ mww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN
+ mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN
- mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232
- while {[expr [mrw [expr $PLL_ADDR + $PLL_DP_CTL]] & 0x1] == 0} { sleep 1 }
+ mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
+ while {[expr [mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1] == 0} { sleep 1 }
}
proc CPU_2_BE_32 { L } {
- return [expr (($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)]
+ return [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)}]
}
diff --git a/tcl/board/imx31pdk.cfg b/tcl/board/imx31pdk.cfg
index 2dce157db..6c196543c 100644
--- a/tcl/board/imx31pdk.cfg
+++ b/tcl/board/imx31pdk.cfg
@@ -6,7 +6,7 @@ $_TARGETNAME configure -event reset-init { imx31pdk_init }
proc self_test {} {
echo "Running 100 iterations of test."
dump_image /ram/test 0x80000000 0x40000
- for {set i 0} {$i < 100} {set i [expr $i+1]} {
+ for {set i 0} {$i < 100} {set i [expr {$i+1}]} {
echo "Iteration $i"
reset init
mww 0x80000000 0x12345678 0x10000
diff --git a/tcl/board/imx53-m53evk.cfg b/tcl/board/imx53-m53evk.cfg
index b529c4940..6f4964e3d 100644
--- a/tcl/board/imx53-m53evk.cfg
+++ b/tcl/board/imx53-m53evk.cfg
@@ -44,7 +44,7 @@ proc m53evk_init { } {
; # ARM errata ID #468414
set tR [arm mrc 15 0 1 0 1]
- arm mcr 15 0 1 0 1 [expr $tR | (1<<5)] ; # enable L1NEON bit
+ arm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}] ; # enable L1NEON bit
init_l2cc
init_aips
@@ -75,7 +75,7 @@ proc init_l2cc { } {
; #orr r0, r0, #(1 << 22) /* disable write allocate */
; #mcr 15, 1, r0, c9, c0, 2
- arm mcr 15 1 9 0 2 [expr 0xC4 | (1<<24) | (1<<23) | (1<<22)]
+ arm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}]
}
@@ -89,10 +89,10 @@ proc init_aips { } {
set VAL 0x77777777
# dap apsel 1
- mww [expr $AIPS1_BASE_ADDR + 0x0] $VAL
- mww [expr $AIPS1_BASE_ADDR + 0x4] $VAL
- mww [expr $AIPS2_BASE_ADDR + 0x0] $VAL
- mww [expr $AIPS2_BASE_ADDR + 0x4] $VAL
+ mww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL
+ mww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL
+ mww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL
+ mww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL
# dap apsel 0
}
@@ -100,22 +100,22 @@ proc init_aips { } {
proc init_clock { } {
global AIPS1_BASE_ADDR
global AIPS2_BASE_ADDR
- set CCM_BASE_ADDR [expr $AIPS1_BASE_ADDR + 0x000D4000]
+ set CCM_BASE_ADDR [expr {$AIPS1_BASE_ADDR + 0x000D4000}]
set CLKCTL_CCSR 0x0C
set CLKCTL_CBCDR 0x14
set CLKCTL_CBCMR 0x18
- set PLL1_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00080000]
- set PLL2_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00084000]
- set PLL3_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00088000]
- set PLL4_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x0008C000]
+ set PLL1_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00080000}]
+ set PLL2_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00084000}]
+ set PLL3_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00088000}]
+ set PLL4_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x0008C000}]
set CLKCTL_CSCMR1 0x1C
set CLKCTL_CDHIPR 0x48
- set PLATFORM_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x000A0000]
+ set PLATFORM_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x000A0000}]
set CLKCTL_CSCDR1 0x24
set CLKCTL_CCDR 0x04
; # Switch ARM to step clock
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x4
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4
return
echo "not returned"
@@ -123,52 +123,52 @@ proc init_clock { } {
setup_pll $PLL3_BASE_ADDR 400
; # Switch peripheral to PLL3
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00015154
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x02888945 | (1<<16)]
- while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 }
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}]
+ while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
setup_pll $PLL2_BASE_ADDR 400
; # Switch peripheral to PLL2
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x00808145 | (2<<10) | (9<<16) | (1<<19)]
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}]
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00016154
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154
; # change uart clk parent to pll2
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1]] & 0xfcffffff | 0x01000000]
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000]
; # make sure change is effective
- while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 }
+ while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
setup_pll $PLL3_BASE_ADDR 216
setup_pll $PLL4_BASE_ADDR 455
; # Set the platform clock dividers
- mww [expr $PLATFORM_BASE_ADDR + 0x14] 0x00000124
+ mww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124
- mww [expr $CCM_BASE_ADDR + 0x10] 0
+ mww [expr {$CCM_BASE_ADDR + 0x10}] 0
; # Switch ARM back to PLL 1.
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x0
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0
; # make uart div=6
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1]] & 0xffffffc0 | 0x0a]
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a]
; # Restore the default values in the Gate registers
- mww [expr $CCM_BASE_ADDR + 0x68] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x6C] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x70] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x74] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x78] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x7C] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x80] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x84] 0xFFFFFFFF
+ mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF
+ mww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF
+ mww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF
+ mww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF
+ mww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF
+ mww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF
+ mww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF
+ mww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CCDR] 0x00000
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000
; # for cko - for ARM div by 8
- mww [expr $CCM_BASE_ADDR + 0x60] [expr 0x000A0000 & 0x00000F0]
+ mww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}]
}
@@ -183,68 +183,68 @@ proc setup_pll { PLL_ADDR CLK } {
set PLL_DP_HFS_MFN 0x24
if {$CLK == 1000} {
- set DP_OP [expr (10 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (12 - 1)]
+ set DP_OP [expr {(10 << 4) + ((1 - 1) << 0)}]
+ set DP_MFD [expr {12 - 1}]
set DP_MFN 5
} elseif {$CLK == 850} {
- set DP_OP [expr (8 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (48 - 1)]
+ set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}]
+ set DP_MFD [expr {48 - 1}]
set DP_MFN 41
} elseif {$CLK == 800} {
- set DP_OP [expr (8 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (3 - 1)]
+ set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}]
+ set DP_MFD [expr {3 - 1}]
set DP_MFN 1
} elseif {$CLK == 700} {
- set DP_OP [expr (7 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (24 - 1)]
+ set DP_OP [expr {(7 << 4) + ((1 - 1) << 0)}]
+ set DP_MFD [expr {24 - 1}]
set DP_MFN 7
} elseif {$CLK == 600} {
- set DP_OP [expr (6 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (4 - 1)]
+ set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}]
+ set DP_MFD [expr {4 - 1}]
set DP_MFN 1
} elseif {$CLK == 665} {
- set DP_OP [expr (6 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (96 - 1)]
+ set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}]
+ set DP_MFD [expr {96 - 1}]
set DP_MFN 89
} elseif {$CLK == 532} {
- set DP_OP [expr (5 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (24 - 1)]
+ set DP_OP [expr {(5 << 4) + ((1 - 1) << 0)}]
+ set DP_MFD [expr {24 - 1}]
set DP_MFN 13
} elseif {$CLK == 455} {
- set DP_OP [expr (8 << 4) + ((2 - 1) << 0)]
- set DP_MFD [expr (48 - 1)]
+ set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}]
+ set DP_MFD [expr {48 - 1}]
set DP_MFN 71
} elseif {$CLK == 400} {
- set DP_OP [expr (8 << 4) + ((2 - 1) << 0)]
- set DP_MFD [expr (3 - 1)]
+ set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}]
+ set DP_MFD [expr {3 - 1}]
set DP_MFN 1
} elseif {$CLK == 216} {
- set DP_OP [expr (6 << 4) + ((3 - 1) << 0)]
- set DP_MFD [expr (4 - 1)]
+ set DP_OP [expr {(6 << 4) + ((3 - 1) << 0)}]
+ set DP_MFD [expr {4 - 1}]
set DP_MFN 3
} else {
error "Error (setup_dll): clock not found!"
}
- mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232
- mww [expr $PLL_ADDR + $PLL_DP_CONFIG] 0x2
+ mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
+ mww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2
- mww [expr $PLL_ADDR + $PLL_DP_OP] $DP_OP
- mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_OP
+ mww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP
+ mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP
- mww [expr $PLL_ADDR + $PLL_DP_MFD] $DP_MFD
- mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_MFD
+ mww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD
+ mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD
- mww [expr $PLL_ADDR + $PLL_DP_MFN] $DP_MFN
- mww [expr $PLL_ADDR + $PLL_DP_HFS_MFN] $DP_MFN
+ mww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN
+ mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN
- mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232
- while {[expr [mrw [expr $PLL_ADDR + $PLL_DP_CTL]] & 0x1] == 0} { sleep 1 }
+ mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
+ while {[expr [mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1] == 0} { sleep 1 }
}
proc CPU_2_BE_32 { L } {
- return [expr (($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)]
+ return [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)}]
}
diff --git a/tcl/board/imx53loco.cfg b/tcl/board/imx53loco.cfg
index 91c260138..e1bc44da3 100644
--- a/tcl/board/imx53loco.cfg
+++ b/tcl/board/imx53loco.cfg
@@ -46,7 +46,7 @@ proc loco_init { } {
; # ARM errata ID #468414
set tR [arm mrc 15 0 1 0 1]
- arm mcr 15 0 1 0 1 [expr $tR | (1<<5)] ; # enable L1NEON bit
+ arm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}] ; # enable L1NEON bit
init_l2cc
init_aips
@@ -80,7 +80,7 @@ proc init_l2cc { } {
; #orr r0, r0, #(1 << 22) /* disable write allocate */
; #mcr 15, 1, r0, c9, c0, 2
- arm mcr 15 1 9 0 2 [expr 0xC4 | (1<<24) | (1<<23) | (1<<22)]
+ arm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}]
}
@@ -94,10 +94,10 @@ proc init_aips { } {
set VAL 0x77777777
# dap apsel 1
- mww [expr $AIPS1_BASE_ADDR + 0x0] $VAL
- mww [expr $AIPS1_BASE_ADDR + 0x4] $VAL
- mww [expr $AIPS2_BASE_ADDR + 0x0] $VAL
- mww [expr $AIPS2_BASE_ADDR + 0x4] $VAL
+ mww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL
+ mww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL
+ mww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL
+ mww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL
# dap apsel 0
}
@@ -105,22 +105,22 @@ proc init_aips { } {
proc init_clock { } {
global AIPS1_BASE_ADDR
global AIPS2_BASE_ADDR
- set CCM_BASE_ADDR [expr $AIPS1_BASE_ADDR + 0x000D4000]
+ set CCM_BASE_ADDR [expr {$AIPS1_BASE_ADDR + 0x000D4000}]
set CLKCTL_CCSR 0x0C
set CLKCTL_CBCDR 0x14
set CLKCTL_CBCMR 0x18
- set PLL1_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00080000]
- set PLL2_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00084000]
- set PLL3_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00088000]
- set PLL4_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x0008C000]
+ set PLL1_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00080000}]
+ set PLL2_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00084000}]
+ set PLL3_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00088000}]
+ set PLL4_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x0008C000}]
set CLKCTL_CSCMR1 0x1C
set CLKCTL_CDHIPR 0x48
- set PLATFORM_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x000A0000]
+ set PLATFORM_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x000A0000}]
set CLKCTL_CSCDR1 0x24
set CLKCTL_CCDR 0x04
; # Switch ARM to step clock
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x4
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4
return
echo "not returned"
@@ -128,52 +128,52 @@ proc init_clock { } {
setup_pll $PLL3_BASE_ADDR 400
; # Switch peripheral to PLL3
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00015154
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x02888945 | (1<<16)]
- while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 }
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}]
+ while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
setup_pll $PLL2_BASE_ADDR 400
; # Switch peripheral to PLL2
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x00808145 | (2<<10) | (9<<16) | (1<<19)]
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}]
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00016154
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154
; # change uart clk parent to pll2
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1]] & 0xfcffffff | 0x01000000]
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000]
; # make sure change is effective
- while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 }
+ while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
setup_pll $PLL3_BASE_ADDR 216
setup_pll $PLL4_BASE_ADDR 455
; # Set the platform clock dividers
- mww [expr $PLATFORM_BASE_ADDR + 0x14] 0x00000124
+ mww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124
- mww [expr $CCM_BASE_ADDR + 0x10] 0
+ mww [expr {$CCM_BASE_ADDR + 0x10}] 0
; # Switch ARM back to PLL 1.
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x0
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0
; # make uart div=6
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1]] & 0xffffffc0 | 0x0a]
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a]
; # Restore the default values in the Gate registers
- mww [expr $CCM_BASE_ADDR + 0x68] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x6C] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x70] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x74] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x78] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x7C] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x80] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x84] 0xFFFFFFFF
+ mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF
+ mww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF
+ mww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF
+ mww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF
+ mww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF
+ mww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF
+ mww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF
+ mww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CCDR] 0x00000
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000
; # for cko - for ARM div by 8
- mww [expr $CCM_BASE_ADDR + 0x60] [expr 0x000A0000 & 0x00000F0]
+ mww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}]
}
@@ -188,68 +188,68 @@ proc setup_pll { PLL_ADDR CLK } {
set PLL_DP_HFS_MFN 0x24
if {$CLK == 1000} {
- set DP_OP [expr (10 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (12 - 1)]
+ set DP_OP [expr {(10 << 4) + ((1 - 1) << 0)}]
+ set DP_MFD [expr {12 - 1}]
set DP_MFN 5
} elseif {$CLK == 850} {
- set DP_OP [expr (8 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (48 - 1)]
+ set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}]
+ set DP_MFD [expr {48 - 1}]
set DP_MFN 41
} elseif {$CLK == 800} {
- set DP_OP [expr (8 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (3 - 1)]
+ set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}]
+ set DP_MFD [expr {3 - 1}]
set DP_MFN 1
} elseif {$CLK == 700} {
- set DP_OP [expr (7 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (24 - 1)]
+ set DP_OP [expr {(7 << 4) + ((1 - 1) << 0)}]
+ set DP_MFD [expr {24 - 1}]
set DP_MFN 7
} elseif {$CLK == 600} {
- set DP_OP [expr (6 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (4 - 1)]
+ set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}]
+ set DP_MFD [expr {4 - 1}]
set DP_MFN 1
} elseif {$CLK == 665} {
- set DP_OP [expr (6 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (96 - 1)]
+ set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}]
+ set DP_MFD [expr {96 - 1}]
set DP_MFN 89
} elseif {$CLK == 532} {
- set DP_OP [expr (5 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (24 - 1)]
+ set DP_OP [expr {(5 << 4) + ((1 - 1) << 0)}]
+ set DP_MFD [expr {24 - 1}]
set DP_MFN 13
} elseif {$CLK == 455} {
- set DP_OP [expr (8 << 4) + ((2 - 1) << 0)]
- set DP_MFD [expr (48 - 1)]
+ set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}]
+ set DP_MFD [expr {48 - 1}]
set DP_MFN 71
} elseif {$CLK == 400} {
- set DP_OP [expr (8 << 4) + ((2 - 1) << 0)]
- set DP_MFD [expr (3 - 1)]
+ set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}]
+ set DP_MFD [expr {3 - 1}]
set DP_MFN 1
} elseif {$CLK == 216} {
- set DP_OP [expr (6 << 4) + ((3 - 1) << 0)]
- set DP_MFD [expr (4 - 1)]
+ set DP_OP [expr {(6 << 4) + ((3 - 1) << 0)}]
+ set DP_MFD [expr {4 - 1}]
set DP_MFN 3
} else {
error "Error (setup_dll): clock not found!"
}
- mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232
- mww [expr $PLL_ADDR + $PLL_DP_CONFIG] 0x2
+ mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
+ mww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2
- mww [expr $PLL_ADDR + $PLL_DP_OP] $DP_OP
- mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_OP
+ mww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP
+ mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP
- mww [expr $PLL_ADDR + $PLL_DP_MFD] $DP_MFD
- mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_MFD
+ mww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD
+ mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD
- mww [expr $PLL_ADDR + $PLL_DP_MFN] $DP_MFN
- mww [expr $PLL_ADDR + $PLL_DP_HFS_MFN] $DP_MFN
+ mww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN
+ mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN
- mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232
- while {[expr [mrw [expr $PLL_ADDR + $PLL_DP_CTL]] & 0x1] == 0} { sleep 1 }
+ mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
+ while {[expr [mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1] == 0} { sleep 1 }
}
proc CPU_2_BE_32 { L } {
- return [expr (($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)]
+ return [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)}]
}
diff --git a/tcl/board/mcb1700.cfg b/tcl/board/mcb1700.cfg
index 01080a0b1..a5e19024a 100644
--- a/tcl/board/mcb1700.cfg
+++ b/tcl/board/mcb1700.cfg
@@ -55,7 +55,7 @@ $_TARGETNAME configure -event reset-init {
#
#
global MCB1700_CCLK
- adapter speed [expr $MCB1700_CCLK / 8]
+ adapter speed [expr {$MCB1700_CCLK / 8}]
# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
# "User Flash Mode" where interrupt vectors are _not_ remapped,
diff --git a/tcl/chip/atmel/at91/aic.tcl b/tcl/chip/atmel/at91/aic.tcl
index ba0f2a91b..b0b100270 100644
--- a/tcl/chip/atmel/at91/aic.tcl
+++ b/tcl/chip/atmel/at91/aic.tcl
@@ -1,38 +1,38 @@
-set AIC_SMR [expr $AT91C_BASE_AIC + 0x00000000 ]
+set AIC_SMR [expr {$AT91C_BASE_AIC + 0x00000000} ]
global AIC_SMR
-set AIC_SVR [expr $AT91C_BASE_AIC + 0x00000080 ]
+set AIC_SVR [expr {$AT91C_BASE_AIC + 0x00000080} ]
global AIC_SVR
-set AIC_IVR [expr $AT91C_BASE_AIC + 0x00000100 ]
+set AIC_IVR [expr {$AT91C_BASE_AIC + 0x00000100} ]
global AIC_IVR
-set AIC_FVR [expr $AT91C_BASE_AIC + 0x00000104 ]
+set AIC_FVR [expr {$AT91C_BASE_AIC + 0x00000104} ]
global AIC_FVR
-set AIC_ISR [expr $AT91C_BASE_AIC + 0x00000108 ]
+set AIC_ISR [expr {$AT91C_BASE_AIC + 0x00000108} ]
global AIC_ISR
-set AIC_IPR [expr $AT91C_BASE_AIC + 0x0000010C ]
+set AIC_IPR [expr {$AT91C_BASE_AIC + 0x0000010C} ]
global AIC_IPR
-set AIC_IMR [expr $AT91C_BASE_AIC + 0x00000110 ]
+set AIC_IMR [expr {$AT91C_BASE_AIC + 0x00000110} ]
global AIC_IMR
-set AIC_CISR [expr $AT91C_BASE_AIC + 0x00000114 ]
+set AIC_CISR [expr {$AT91C_BASE_AIC + 0x00000114} ]
global AIC_CISR
-set AIC_IECR [expr $AT91C_BASE_AIC + 0x00000120 ]
+set AIC_IECR [expr {$AT91C_BASE_AIC + 0x00000120} ]
global AIC_IECR
-set AIC_IDCR [expr $AT91C_BASE_AIC + 0x00000124 ]
+set AIC_IDCR [expr {$AT91C_BASE_AIC + 0x00000124} ]
global AIC_IDCR
-set AIC_ICCR [expr $AT91C_BASE_AIC + 0x00000128 ]
+set AIC_ICCR [expr {$AT91C_BASE_AIC + 0x00000128} ]
global AIC_ICCR
-set AIC_ISCR [expr $AT91C_BASE_AIC + 0x0000012C ]
+set AIC_ISCR [expr {$AT91C_BASE_AIC + 0x0000012C} ]
global AIC_ISCR
-set AIC_EOICR [expr $AT91C_BASE_AIC + 0x00000130 ]
+set AIC_EOICR [expr {$AT91C_BASE_AIC + 0x00000130} ]
global AIC_EOICR
-set AIC_SPU [expr $AT91C_BASE_AIC + 0x00000134 ]
+set AIC_SPU [expr {$AT91C_BASE_AIC + 0x00000134} ]
global AIC_SPU
-set AIC_DCR [expr $AT91C_BASE_AIC + 0x00000138 ]
+set AIC_DCR [expr {$AT91C_BASE_AIC + 0x00000138} ]
global AIC_DCR
-set AIC_FFER [expr $AT91C_BASE_AIC + 0x00000140 ]
+set AIC_FFER [expr {$AT91C_BASE_AIC + 0x00000140} ]
global AIC_FFER
-set AIC_FFDR [expr $AT91C_BASE_AIC + 0x00000144 ]
+set AIC_FFDR [expr {$AT91C_BASE_AIC + 0x00000144} ]
global AIC_FFDR
-set AIC_FFSR [expr $AT91C_BASE_AIC + 0x00000148 ]
+set AIC_FFSR [expr {$AT91C_BASE_AIC + 0x00000148} ]
global AIC_FFSR
@@ -54,7 +54,7 @@ proc show_AIC_IMR_helper { NAME ADDR VAL } {
proc show_AIC { } {
global AIC_SMR
- if [catch { mem2array aaa 32 $AIC_SMR [expr 32 * 4] } msg ] {
+ if [catch { mem2array aaa 32 $AIC_SMR [expr {32 * 4}] } msg ] {
error [format "%s (%s)" $msg AIC_SMR]
}
echo "AIC_SMR: Mode & Type"
@@ -71,7 +71,7 @@ proc show_AIC { } {
incr x
}
global AIC_SVR
- if [catch { mem2array aaa 32 $AIC_SVR [expr 32 * 4] } msg ] {
+ if [catch { mem2array aaa 32 $AIC_SVR [expr {32 * 4}] } msg ] {
error [format "%s (%s)" $msg AIC_SVR]
}
echo "AIC_SVR: Vectors"
diff --git a/tcl/chip/atmel/at91/at91_pmc.cfg b/tcl/chip/atmel/at91/at91_pmc.cfg
index 88b137024..0233cb4c1 100644
--- a/tcl/chip/atmel/at91/at91_pmc.cfg
+++ b/tcl/chip/atmel/at91/at91_pmc.cfg
@@ -1,113 +1,113 @@
-set AT91_PMC_SCER [expr ($AT91_PMC + 0x00)] ;# System Clock Enable Register
-set AT91_PMC_SCDR [expr ($AT91_PMC + 0x04)] ;# System Clock Disable Register
+set AT91_PMC_SCER [expr {$AT91_PMC + 0x00}] ;# System Clock Enable Register
+set AT91_PMC_SCDR [expr {$AT91_PMC + 0x04}] ;# System Clock Disable Register
-set AT91_PMC_SCSR [expr ($AT91_PMC + 0x08)] ;# System Clock Status Register
-set AT91_PMC_PCK [expr (1 << 0)] ;# Processor Clock
-set AT91RM9200_PMC_UDP [expr (1 << 1)] ;# USB Devcice Port Clock [AT91RM9200 only]
-set AT91RM9200_PMC_MCKUDP [expr (1 << 2)] ;# USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only]
-set AT91CAP9_PMC_DDR [expr (1 << 2)] ;# DDR Clock [CAP9 revC & some SAM9 only]
-set AT91RM9200_PMC_UHP [expr (1 << 4)] ;# USB Host Port Clock [AT91RM9200 only]
-set AT91SAM926x_PMC_UHP [expr (1 << 6)] ;# USB Host Port Clock [AT91SAM926x only]
-set AT91CAP9_PMC_UHP [expr (1 << 6)] ;# USB Host Port Clock [AT91CAP9 only]
-set AT91SAM926x_PMC_UDP [expr (1 << 7)] ;# USB Devcice Port Clock [AT91SAM926x only]
-set AT91_PMC_PCK0 [expr (1 << 8)] ;# Programmable Clock 0
-set AT91_PMC_PCK1 [expr (1 << 9)] ;# Programmable Clock 1
-set AT91_PMC_PCK2 [expr (1 << 10)] ;# Programmable Clock 2
-set AT91_PMC_PCK3 [expr (1 << 11)] ;# Programmable Clock 3
-set AT91_PMC_HCK0 [expr (1 << 16)] ;# AHB Clock (USB host) [AT91SAM9261 only]
-set AT91_PMC_HCK1 [expr (1 << 17)] ;# AHB Clock (LCD) [AT91SAM9261 only]
+set AT91_PMC_SCSR [expr {$AT91_PMC + 0x08}] ;# System Clock Status Register
+set AT91_PMC_PCK [expr {1 << 0}] ;# Processor Clock
+set AT91RM9200_PMC_UDP [expr {1 << 1}] ;# USB Devcice Port Clock [AT91RM9200 only]
+set AT91RM9200_PMC_MCKUDP [expr {1 << 2}] ;# USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only]
+set AT91CAP9_PMC_DDR [expr {1 << 2}] ;# DDR Clock [CAP9 revC & some SAM9 only]
+set AT91RM9200_PMC_UHP [expr {1 << 4}] ;# USB Host Port Clock [AT91RM9200 only]
+set AT91SAM926x_PMC_UHP [expr {1 << 6}] ;# USB Host Port Clock [AT91SAM926x only]
+set AT91CAP9_PMC_UHP [expr {1 << 6}] ;# USB Host Port Clock [AT91CAP9 only]
+set AT91SAM926x_PMC_UDP [expr {1 << 7}] ;# USB Devcice Port Clock [AT91SAM926x only]
+set AT91_PMC_PCK0 [expr {1 << 8}] ;# Programmable Clock 0
+set AT91_PMC_PCK1 [expr {1 << 9}] ;# Programmable Clock 1
+set AT91_PMC_PCK2 [expr {1 << 10}] ;# Programmable Clock 2
+set AT91_PMC_PCK3 [expr {1 << 11}] ;# Programmable Clock 3
+set AT91_PMC_HCK0 [expr {1 << 16}] ;# AHB Clock (USB host) [AT91SAM9261 only]
+set AT91_PMC_HCK1 [expr {1 << 17}] ;# AHB Clock (LCD) [AT91SAM9261 only]
-set AT91_PMC_PCER [expr ($AT91_PMC + 0x10)] ;# Peripheral Clock Enable Register
-set AT91_PMC_PCDR [expr ($AT91_PMC + 0x14)] ;# Peripheral Clock Disable Register
-set AT91_PMC_PCSR [expr ($AT91_PMC + 0x18)] ;# Peripheral Clock Status Register
+set AT91_PMC_PCER [expr {$AT91_PMC + 0x10}] ;# Peripheral Clock Enable Register
+set AT91_PMC_PCDR [expr {$AT91_PMC + 0x14}] ;# Peripheral Clock Disable Register
+set AT91_PMC_PCSR [expr {$AT91_PMC + 0x18}] ;# Peripheral Clock Status Register
-set AT91_CKGR_UCKR [expr ($AT91_PMC + 0x1C)] ;# UTMI Clock Register [some SAM9, CAP9]
-set AT91_PMC_UPLLEN [expr (1 << 16)] ;# UTMI PLL Enable
-set AT91_PMC_UPLLCOUNT [expr (0xf << 20)] ;# UTMI PLL Start-up Time
-set AT91_PMC_BIASEN [expr (1 << 24)] ;# UTMI BIAS Enable
-set AT91_PMC_BIASCOUNT [expr (0xf << 28)] ;# UTMI BIAS Start-up Time
+set AT91_CKGR_UCKR [expr {$AT91_PMC + 0x1C}] ;# UTMI Clock Register [some SAM9, CAP9]
+set AT91_PMC_UPLLEN [expr {1 << 16}] ;# UTMI PLL Enable
+set AT91_PMC_UPLLCOUNT [expr {0xf << 20}] ;# UTMI PLL Start-up Time
+set AT91_PMC_BIASEN [expr {1 << 24}] ;# UTMI BIAS Enable
+set AT91_PMC_BIASCOUNT [expr {0xf << 28}] ;# UTMI BIAS Start-up Time
-set AT91_CKGR_MOR [expr ($AT91_PMC + 0x20)] ;# Main Oscillator Register [not on SAM9RL]
-set AT91_PMC_MOSCEN [expr (1 << 0)] ;# Main Oscillator Enable
-set AT91_PMC_OSCBYPASS [expr (1 << 1)] ;# Oscillator Bypass [SAM9x, CAP9]
-set AT91_PMC_OSCOUNT [expr (0xff << 8)] ;# Main Oscillator Start-up Time
+set AT91_CKGR_MOR [expr {$AT91_PMC + 0x20}] ;# Main Oscillator Register [not on SAM9RL]
+set AT91_PMC_MOSCEN [expr {1 << 0}] ;# Main Oscillator Enable
+set AT91_PMC_OSCBYPASS [expr {1 << 1}] ;# Oscillator Bypass [SAM9x, CAP9]
+set AT91_PMC_OSCOUNT [expr {0xff << 8}] ;# Main Oscillator Start-up Time
-set AT91_CKGR_MCFR [expr ($AT91_PMC + 0x24)] ;# Main Clock Frequency Register
-set AT91_PMC_MAINF [expr (0xffff << 0)] ;# Main Clock Frequency
-set AT91_PMC_MAINRDY [expr (1 << 16)] ;# Main Clock Ready
+set AT91_CKGR_MCFR [expr {$AT91_PMC + 0x24}] ;# Main Clock Frequency Register
+set AT91_PMC_MAINF [expr {0xffff << 0}] ;# Main Clock Frequency
+set AT91_PMC_MAINRDY [expr {1 << 16}] ;# Main Clock Ready
-set AT91_CKGR_PLLAR [expr ($AT91_PMC + 0x28)] ;# PLL A Register
-set AT91_CKGR_PLLBR [expr ($AT91_PMC + 0x2c)] ;# PLL B Register
-set AT91_PMC_DIV [expr (0xff << 0)] ;# Divider
-set AT91_PMC_PLLCOUNT [expr (0x3f << 8)] ;# PLL Counter
-set AT91_PMC_OUT [expr (3 << 14)] ;# PLL Clock Frequency Range
-set AT91_PMC_MUL [expr (0x7ff << 16)] ;# PLL Multiplier
-set AT91_PMC_USBDIV [expr (3 << 28)] ;# USB Divisor (PLLB only)
-set AT91_PMC_USBDIV_1 [expr (0 << 28)]
-set AT91_PMC_USBDIV_2 [expr (1 << 28)]
-set AT91_PMC_USBDIV_4 [expr (2 << 28)]
-set AT91_PMC_USB96M [expr (1 << 28)] ;# Divider by 2 Enable (PLLB only)
-set AT91_PMC_PLLA_WR_ERRATA [expr (1 << 29)] ;# Bit 29 must always be set to 1 when programming the CKGR_PLLAR register
+set AT91_CKGR_PLLAR [expr {$AT91_PMC + 0x28}] ;# PLL A Register
+set AT91_CKGR_PLLBR [expr {$AT91_PMC + 0x2c}] ;# PLL B Register
+set AT91_PMC_DIV [expr {0xff << 0}] ;# Divider
+set AT91_PMC_PLLCOUNT [expr {0x3f << 8}] ;# PLL Counter
+set AT91_PMC_OUT [expr {3 << 14}] ;# PLL Clock Frequency Range
+set AT91_PMC_MUL [expr {0x7ff << 16}] ;# PLL Multiplier
+set AT91_PMC_USBDIV [expr {3 << 28}] ;# USB Divisor (PLLB only)
+set AT91_PMC_USBDIV_1 [expr {0 << 28}]
+set AT91_PMC_USBDIV_2 [expr {1 << 28}]
+set AT91_PMC_USBDIV_4 [expr {2 << 28}]
+set AT91_PMC_USB96M [expr {1 << 28}] ;# Divider by 2 Enable (PLLB only)
+set AT91_PMC_PLLA_WR_ERRATA [expr {1 << 29}] ;# Bit 29 must always be set to 1 when programming the CKGR_PLLAR register
-set AT91_PMC_MCKR [expr ($AT91_PMC + 0x30)] ;# Master Clock Register
-set AT91_PMC_CSS [expr (3 << 0)] ;# Master Clock Selection
-set AT91_PMC_CSS_SLOW [expr (0 << 0)]
-set AT91_PMC_CSS_MAIN [expr (1 << 0)]
-set AT91_PMC_CSS_PLLA [expr (2 << 0)]
-set AT91_PMC_CSS_PLLB [expr (3 << 0)]
-set AT91_PMC_CSS_UPLL [expr (3 << 0)] ;# [some SAM9 only]
-set AT91_PMC_PRES [expr (7 << 2)] ;# Master Clock Prescaler
-set AT91_PMC_PRES_1 [expr (0 << 2)]
-set AT91_PMC_PRES_2 [expr (1 << 2)]
-set AT91_PMC_PRES_4 [expr (2 << 2)]
-set AT91_PMC_PRES_8 [expr (3 << 2)]
-set AT91_PMC_PRES_16 [expr (4 << 2)]
-set AT91_PMC_PRES_32 [expr (5 << 2)]
-set AT91_PMC_PRES_64 [expr (6 << 2)]
-set AT91_PMC_MDIV [expr (3 << 8)] ;# Master Clock Division
-set AT91RM9200_PMC_MDIV_1 [expr (0 << 8)] ;# [AT91RM9200 only]
-set AT91RM9200_PMC_MDIV_2 [expr (1 << 8)]
-set AT91RM9200_PMC_MDIV_3 [expr (2 << 8)]
-set AT91RM9200_PMC_MDIV_4 [expr (3 << 8)]
-set AT91SAM9_PMC_MDIV_1 [expr (0 << 8)] ;# [SAM9,CAP9 only]
-set AT91SAM9_PMC_MDIV_2 [expr (1 << 8)]
-set AT91SAM9_PMC_MDIV_4 [expr (2 << 8)]
-set AT91SAM9_PMC_MDIV_6 [expr (3 << 8)] ;# [some SAM9 only]
-set AT91SAM9_PMC_MDIV_3 [expr (3 << 8)] ;# [some SAM9 only]
-set AT91_PMC_PDIV [expr (1 << 12)] ;# Processor Clock Division [some SAM9 only]
-set AT91_PMC_PDIV_1 [expr (0 << 12)]
-set AT91_PMC_PDIV_2 [expr (1 << 12)]
-set AT91_PMC_PLLADIV2 [expr (1 << 12)] ;# PLLA divisor by 2 [some SAM9 only]
-set AT91_PMC_PLLADIV2_OFF [expr (0 << 12)]
-set AT91_PMC_PLLADIV2_ON [expr (1 << 12)]
+set AT91_PMC_MCKR [expr {$AT91_PMC + 0x30}] ;# Master Clock Register
+set AT91_PMC_CSS [expr {3 << 0}] ;# Master Clock Selection
+set AT91_PMC_CSS_SLOW [expr {0 << 0}]
+set AT91_PMC_CSS_MAIN [expr {1 << 0}]
+set AT91_PMC_CSS_PLLA [expr {2 << 0}]
+set AT91_PMC_CSS_PLLB [expr {3 << 0}]
+set AT91_PMC_CSS_UPLL [expr {3 << 0}] ;# [some SAM9 only]
+set AT91_PMC_PRES [expr {7 << 2}] ;# Master Clock Prescaler
+set AT91_PMC_PRES_1 [expr {0 << 2}]
+set AT91_PMC_PRES_2 [expr {1 << 2}]
+set AT91_PMC_PRES_4 [expr {2 << 2}]
+set AT91_PMC_PRES_8 [expr {3 << 2}]
+set AT91_PMC_PRES_16 [expr {4 << 2}]
+set AT91_PMC_PRES_32 [expr {5 << 2}]
+set AT91_PMC_PRES_64 [expr {6 << 2}]
+set AT91_PMC_MDIV [expr {3 << 8}] ;# Master Clock Division
+set AT91RM9200_PMC_MDIV_1 [expr {0 << 8}] ;# [AT91RM9200 only]
+set AT91RM9200_PMC_MDIV_2 [expr {1 << 8}]
+set AT91RM9200_PMC_MDIV_3 [expr {2 << 8}]
+set AT91RM9200_PMC_MDIV_4 [expr {3 << 8}]
+set AT91SAM9_PMC_MDIV_1 [expr {0 << 8}] ;# [SAM9,CAP9 only]
+set AT91SAM9_PMC_MDIV_2 [expr {1 << 8}]
+set AT91SAM9_PMC_MDIV_4 [expr {2 << 8}]
+set AT91SAM9_PMC_MDIV_6 [expr {3 << 8}] ;# [some SAM9 only]
+set AT91SAM9_PMC_MDIV_3 [expr {3 << 8}] ;# [some SAM9 only]
+set AT91_PMC_PDIV [expr {1 << 12}] ;# Processor Clock Division [some SAM9 only]
+set AT91_PMC_PDIV_1 [expr {0 << 12}]
+set AT91_PMC_PDIV_2 [expr {1 << 12}]
+set AT91_PMC_PLLADIV2 [expr {1 << 12}] ;# PLLA divisor by 2 [some SAM9 only]
+set AT91_PMC_PLLADIV2_OFF [expr {0 << 12}]
+set AT91_PMC_PLLADIV2_ON [expr {1 << 12}]
-set AT91_PMC_USB [expr ($AT91_PMC + 0x38)] ;# USB Clock Register [some SAM9 only]
-set AT91_PMC_USBS [expr (0x1 << 0)] ;# USB OHCI Input clock selection
-set AT91_PMC_USBS_PLLA [expr (0 << 0)]
-set AT91_PMC_USBS_UPLL [expr (1 << 0)]
-set AT91_PMC_OHCIUSBDIV [expr (0xF << 8)] ;# Divider for USB OHCI Clock
+set AT91_PMC_USB [expr {$AT91_PMC + 0x38}] ;# USB Clock Register [some SAM9 only]
+set AT91_PMC_USBS [expr {0x1 << 0}] ;# USB OHCI Input clock selection
+set AT91_PMC_USBS_PLLA [expr {0 << 0}]
+set AT91_PMC_USBS_UPLL [expr {1 << 0}]
+set AT91_PMC_OHCIUSBDIV [expr {0xF << 8}] ;# Divider for USB OHCI Clock
;# set AT91_PMC_PCKR(n) [expr ($AT91_PMC + 0x40 + ((n) * 4))] ;# Programmable Clock 0-N Registers
-set AT91_PMC_CSSMCK [expr (0x1 << 8)] ;# CSS or Master Clock Selection
-set AT91_PMC_CSSMCK_CSS [expr (0 << 8)]
-set AT91_PMC_CSSMCK_MCK [expr (1 << 8)]
+set AT91_PMC_CSSMCK [expr {0x1 << 8}] ;# CSS or Master Clock Selection
+set AT91_PMC_CSSMCK_CSS [expr {0 << 8}]
+set AT91_PMC_CSSMCK_MCK [expr {1 << 8}]
-set AT91_PMC_IER [expr ($AT91_PMC + 0x60)] ;# Interrupt Enable Register
-set AT91_PMC_IDR [expr ($AT91_PMC + 0x64)] ;# Interrupt Disable Register
-set AT91_PMC_SR [expr ($AT91_PMC + 0x68)] ;# Status Register
-set AT91_PMC_MOSCS [expr (1 << 0)] ;# MOSCS Flag
-set AT...
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