[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.11.0-86-gfa94a42a0

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- Log -----------------------------------------------------------------
commit fa94a42a09aadc3851015bbaedecd0300732a8b1
Author: Antonio Borneo <bor...@gm...>
Date:   Tue Apr 6 23:44:37 2021 +0200

    doc: [3/3] uniform the texinfo syntax for commands definition
    
    To avoid errors in the documentation, like the one fixed by change
    http://openocd.zylin.com/6134/ , use a uniform notation across the
    file so simple copy-paste will work.
    
    Enclose every command within curly-brackets '{...}', even single
    word commands.
    Patch generated through:
            sed -i 's/^\(@deffn {[^{]*} \)\([^{][^ ]*\)/\1{\2}/' doc/openocd.texi
            sed -i 's/^\(@deffnx {[^{]*} \)\([^{][^ ]*\)/\1{\2}/' doc/openocd.texi
    
    Change-Id: I41a8447d487ec8f6f32c2babcbc73ac21c769344
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/6152
    Tested-by: jenkins

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 8b4113aac..fdef3309d 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -2063,7 +2063,7 @@ a target has been successfully instantiated.
 If you want to use those commands, you may need to force
 entry to the run stage.
 
-@deffn {Config Command} init
+@deffn {Config Command} {init}
 This command terminates the configuration stage and
 enters the run stage. This helps when you need to have
 the startup scripts manage tasks such as resetting the target,
@@ -2082,7 +2082,7 @@ read/write memory on your target, @command{init} must occur before
 the memory read/write commands. This includes @command{nand probe}.
 @end deffn
 
-@deffn {Overridable Procedure} jtag_init
+@deffn {Overridable Procedure} {jtag_init}
 This is invoked at server startup to verify that it can talk
 to the scan chain (list of TAPs) which has been configured.
 
@@ -2186,13 +2186,13 @@ breakpoints if the memory map has been set up for flash regions.
 @end deffn
 
 @anchor{gdbflashprogram}
-@deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
+@deffn {Config Command} {gdb_flash_program} (@option{enable}|@option{disable})
 Set to @option{enable} to cause OpenOCD to program the flash memory when a
 vFlash packet is received.
 The default behaviour is @option{enable}.
 @end deffn
 
-@deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
+@deffn {Config Command} {gdb_memory_map} (@option{enable}|@option{disable})
 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
 requested. GDB will then know when to set hardware breakpoints, and program flash
 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
@@ -2201,21 +2201,21 @@ Default behaviour is @option{enable}.
 @xref{gdbflashprogram,,gdb_flash_program}.
 @end deffn
 
-@deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
+@deffn {Config Command} {gdb_report_data_abort} (@option{enable}|@option{disable})
 Specifies whether data aborts cause an error to be reported
 by GDB memory read packets.
 The default behaviour is @option{disable};
 use @option{enable} see these errors reported.
 @end deffn
 
-@deffn {Config Command} gdb_report_register_access_error (@option{enable}|@option{disable})
+@deffn {Config Command} {gdb_report_register_access_error} (@option{enable}|@option{disable})
 Specifies whether register accesses requested by GDB register read/write
 packets report errors or not.
 The default behaviour is @option{disable};
 use @option{enable} see these errors reported.
 @end deffn
 
-@deffn {Config Command} gdb_target_description (@option{enable}|@option{disable})
+@deffn {Config Command} {gdb_target_description} (@option{enable}|@option{disable})
 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
 The default behaviour is @option{enable}.
 @end deffn
@@ -2383,7 +2383,7 @@ Specifies either the address of the I/O port (default: 0x378 for LPT1) or
 the number of the @file{/dev/parport} device.
 @end deffn
 
-@deffn {Config Command} rtck [@option{enable}|@option{disable}]
+@deffn {Config Command} {rtck} [@option{enable}|@option{disable}]
 Displays status of RTCK option.
 Optionally sets that option first.
 @end deffn
@@ -3745,7 +3745,7 @@ schemes. For example, on a multi-target board the standard
 may need the ability to reset only one target at time and
 thus want to avoid using the board-wide SRST signal.
 
-@deffn {Overridable Procedure} init_reset mode
+@deffn {Overridable Procedure} {init_reset} mode
 This is invoked near the beginning of the @command{reset} command,
 usually to provide as much of a cold (power-up) reset as practical.
 By default it is also invoked from @command{jtag_init} if
@@ -5354,7 +5354,7 @@ As noted above, the @command{flash bank} command requires a driver name,
 and allows driver-specific options and behaviors.
 Some drivers also activate driver-specific commands.
 
-@deffn {Flash Driver} virtual
+@deffn {Flash Driver} {virtual}
 This is a special driver that maps a previously defined bank to another
 address. All bank settings will be copied from the master physical bank.
 
@@ -5378,7 +5378,7 @@ flash bank vbank1 virtual 0x9fc00000 0 0 0 \
 
 @subsection External Flash
 
-@deffn {Flash Driver} cfi
+@deffn {Flash Driver} {cfi}
 @cindex Common Flash Interface
 @cindex CFI
 The ``Common Flash Interface'' (CFI) is the main standard for
@@ -5423,7 +5423,7 @@ flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
 @c "cfi part_id" disabled
 @end deffn
 
-@deffn {Flash Driver} jtagspi
+@deffn {Flash Driver} {jtagspi}
 @cindex Generic JTAG2SPI driver
 @cindex SPI
 @cindex jtagspi
@@ -5464,7 +5464,7 @@ flash bank $_FLASHNAME spi 0x0 0 0 0 \
 @end example
 @end deffn
 
-@deffn {Flash Driver} xcf
+@deffn {Flash Driver} {xcf}
 @cindex Xilinx Platform flash driver
 @cindex xcf
 Xilinx FPGAs can be configured from specialized flash ICs named Platform Flash.
@@ -5510,7 +5510,7 @@ only "bin" (raw binary, do not confuse it with "bit") and "mcs"
 @end itemize
 @end deffn
 
-@deffn {Flash Driver} lpcspifi
+@deffn {Flash Driver} {lpcspifi}
 @cindex NXP SPI Flash Interface
 @cindex SPIFI
 @cindex lpcspifi
@@ -5534,7 +5534,7 @@ flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
 
 @end deffn
 
-@deffn {Flash Driver} stmsmi
+@deffn {Flash Driver} {stmsmi}
 @cindex STMicroelectronics Serial Memory Interface
 @cindex SMI
 @cindex stmsmi
@@ -5562,7 +5562,7 @@ flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
 
 @end deffn
 
-@deffn {Flash Driver} stmqspi
+@deffn {Flash Driver} {stmqspi}
 @cindex STMicroelectronics QuadSPI/OctoSPI Interface
 @cindex QuadSPI
 @cindex OctoSPI
@@ -5677,7 +5677,7 @@ should return the status register contents.
 
 @end deffn
 
-@deffn {Flash Driver} mrvlqspi
+@deffn {Flash Driver} {mrvlqspi}
 This driver supports QSPI flash controller of Marvell's Wireless
 Microcontroller platform.
 
@@ -5690,7 +5690,7 @@ flash bank $_FLASHNAME mrvlqspi 0x0 0 0 0 $_TARGETNAME 0x46010000
 
 @end deffn
 
-@deffn {Flash Driver} ath79
+@deffn {Flash Driver} {ath79}
 @cindex Atheros ath79 SPI driver
 @cindex ath79
 Members of ATH79 SoC family from Atheros include a SPI interface with 3
@@ -5729,7 +5729,7 @@ flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2
 
 @end deffn
 
-@deffn {Flash Driver} fespi
+@deffn {Flash Driver} {fespi}
 @cindex Freedom E SPI
 @cindex fespi
 
@@ -5742,7 +5742,7 @@ flash bank $_FLASHNAME fespi 0x20000000 0 0 0 $_TARGETNAME
 
 @subsection Internal Flash (Microcontrollers)
 
-@deffn {Flash Driver} aduc702x
+@deffn {Flash Driver} {aduc702x}
 The ADUC702x analog microcontrollers from Analog Devices
 include internal flash and use ARM7TDMI cores.
 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
@@ -5754,7 +5754,7 @@ flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
 @end example
 @end deffn
 
-@deffn {Flash Driver} ambiqmicro
+@deffn {Flash Driver} {ambiqmicro}
 @cindex ambiqmicro
 @cindex apollo
 All members of the Apollo microcontroller family from
@@ -5802,7 +5802,7 @@ the flash.
 @end deffn
 
 @anchor{at91samd}
-@deffn {Flash Driver} at91samd
+@deffn {Flash Driver} {at91samd}
 @cindex at91samd
 All members of the ATSAM D2x, D1x, D0x, ATSAMR, ATSAML and ATSAMC microcontroller
 families from Atmel include internal flash and use ARM's Cortex-M0+ core.
@@ -5891,7 +5891,7 @@ NVMUSERROW: 0xFFFFFC5DD8E0C788
 @end deffn
 
 @anchor{at91sam3}
-@deffn {Flash Driver} at91sam3
+@deffn {Flash Driver} {at91sam3}
 @cindex at91sam3
 All members of the AT91SAM3 microcontroller family from
 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
@@ -5955,14 +5955,14 @@ This command shows/sets the slow clock frequency used in the
 @end deffn
 @end deffn
 
-@deffn {Flash Driver} at91sam4
+@deffn {Flash Driver} {at91sam4}
 @cindex at91sam4
 All members of the AT91SAM4 microcontroller family from
 Atmel include internal flash and use ARM's Cortex-M4 core.
 This driver uses the same command names/syntax as @xref{at91sam3}.
 @end deffn
 
-@deffn {Flash Driver} at91sam4l
+@deffn {Flash Driver} {at91sam4l}
 @cindex at91sam4l
 All members of the AT91SAM4L microcontroller family from
 Atmel include internal flash and use ARM's Cortex-M4 core.
@@ -5977,7 +5977,7 @@ Command is used internally in event reset-deassert-post.
 @end deffn
 
 @anchor{atsame5}
-@deffn {Flash Driver} atsame5
+@deffn {Flash Driver} {atsame5}
 @cindex atsame5
 All members of the SAM E54, E53, E51 and D51 microcontroller
 families from Microchip (former Atmel) include internal flash
@@ -6040,14 +6040,14 @@ USER PAGE: 0xAEECFF80FE9A9239
 
 @end deffn
 
-@deffn {Flash Driver} atsamv
+@deffn {Flash Driver} {atsamv}
 @cindex atsamv
 All members of the ATSAMV7x, ATSAMS70, and ATSAME70 families from
 Atmel include internal flash and use ARM's Cortex-M7 core.
 This driver uses the same command names/syntax as @xref{at91sam3}.
 @end deffn
 
-@deffn {Flash Driver} at91sam7
+@deffn {Flash Driver} {at91sam7}
 All members of the AT91SAM7 microcontroller family from Atmel include
 internal flash and use ARM7TDMI cores. The driver automatically
 recognizes a number of these chips using the chip identification
@@ -6094,13 +6094,13 @@ the appropriate at91sam7 target.
 @end deffn
 @end deffn
 
-@deffn {Flash Driver} avr
+@deffn {Flash Driver} {avr}
 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
 @emph{The current implementation is incomplete.}
 @comment - defines mass_erase ... pointless given flash_erase_address
 @end deffn
 
-@deffn {Flash Driver} bluenrg-x
+@deffn {Flash Driver} {bluenrg-x}
 STMicroelectronics BlueNRG-1, BlueNRG-2 and BlueNRG-LP Bluetooth low energy wireless system-on-chip. They include ARM Cortex-M0/M0+ core and internal flash memory.
 The driver automatically recognizes these chips using
 the chip identification registers, and autoconfigures itself.
@@ -6119,7 +6119,7 @@ flash erase_sector 0 0 last # It will perform a mass erase
 Triggering a mass erase is also useful when users want to disable readout protection.
 @end deffn
 
-@deffn {Flash Driver} cc26xx
+@deffn {Flash Driver} {cc26xx}
 All versions of the SimpleLink CC13xx and CC26xx microcontrollers from Texas
 Instruments include internal flash. The cc26xx flash driver supports both the
 CC13xx and CC26xx family of devices. The driver automatically recognizes the
@@ -6131,7 +6131,7 @@ flash bank $_FLASHNAME cc26xx 0 0 0 0 $_TARGETNAME
 @end example
 @end deffn
 
-@deffn {Flash Driver} cc3220sf
+@deffn {Flash Driver} {cc3220sf}
 The CC3220SF version of the SimpleLink CC32xx microcontrollers from Texas
 Instruments includes 1MB of internal flash. The cc3220sf flash driver only
 supports the internal flash. The serial flash on SimpleLink boards is
@@ -6145,7 +6145,7 @@ flash bank $_FLASHNAME cc3220sf 0 0 0 0 $_TARGETNAME
 @end example
 @end deffn
 
-@deffn {Flash Driver} efm32
+@deffn {Flash Driver} {efm32}
 All members of the EFM32 microcontroller family from Energy Micro include
 internal flash and use ARM Cortex-M3 cores. The driver automatically recognizes
 a number of these chips using the chip identification register, and
@@ -6165,7 +6165,7 @@ Note that in order for this command to take effect, the target needs to be reset
 supported.}
 @end deffn
 
-@deffn {Flash Driver} esirisc
+@deffn {Flash Driver} {esirisc}
 Members of the eSi-RISC family may optionally include internal flash programmed
 via the eSi-TSMC Flash interface. Additional parameters are required to
 configure the driver: @option{cfg_address} is the base address of the
@@ -6187,7 +6187,7 @@ is an uncommon operation.}
 @end deffn
 @end deffn
 
-@deffn {Flash Driver} fm3
+@deffn {Flash Driver} {fm3}
 All members of the FM3 microcontroller family from Fujitsu
 include internal flash and use ARM Cortex-M3 cores.
 The @var{fm3} driver uses the @var{target} parameter to select the
@@ -6200,7 +6200,7 @@ flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
 @end example
 @end deffn
 
-@deffn {Flash Driver} fm4
+@deffn {Flash Driver} {fm4}
 All members of the FM4 microcontroller family from Spansion (formerly Fujitsu)
 include internal flash and use ARM Cortex-M4 cores.
 The @var{fm4} driver uses a @var{family} parameter to select the
@@ -6220,7 +6220,7 @@ flash bank $@{_FLASHNAME@}1 fm4 0x00100000 0 0 0 \
 nor is Chip Erase (only Sector Erase is implemented).}
 @end deffn
 
-@deffn {Flash Driver} kinetis
+@deffn {Flash Driver} {kinetis}
 @cindex kinetis
 Kx, KLx, KVx and KE1x members of the Kinetis microcontroller family
 from NXP (former Freescale) include
@@ -6319,7 +6319,7 @@ Command disables watchdog timer.
 @end deffn
 @end deffn
 
-@deffn {Flash Driver} kinetis_ke
+@deffn {Flash Driver} {kinetis_ke}
 @cindex kinetis_ke
 KE0x and KEAx members of the Kinetis microcontroller family from NXP include
 internal flash and use ARM Cortex-M0+. The driver automatically recognizes
@@ -6347,7 +6347,7 @@ Command disables watchdog timer.
 @end deffn
 @end deffn
 
-@deffn {Flash Driver} lpc2000
+@deffn {Flash Driver} {lpc2000}
 This is the driver to support internal flash of all members of the
 LPC11(x)00 and LPC1300 microcontroller families and most members of
 the LPC800, LPC1500, LPC1700, LPC1800, LPC2000, LPC4000, LPC54100,
@@ -6404,7 +6404,7 @@ the specified flash @var{bank}.
 @end deffn
 @end deffn
 
-@deffn {Flash Driver} lpc288x
+@deffn {Flash Driver} {lpc288x}
 The LPC2888 microcontroller from NXP needs slightly different flash
 support from its lpc2000 siblings.
 The @var{lpc288x} driver defines one mandatory parameter,
@@ -6416,7 +6416,7 @@ flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
 @end example
 @end deffn
 
-@deffn {Flash Driver} lpc2900
+@deffn {Flash Driver} {lpc2900}
 This driver supports the LPC29xx ARM968E based microcontroller family
 from NXP.
 
@@ -6539,7 +6539,7 @@ lpc2900 secure_jtag 0
 @end deffn
 @end deffn
 
-@deffn {Flash Driver} mdr
+@deffn {Flash Driver} {mdr}
 This drivers handles the integrated NOR flash on Milandr Cortex-M
 based controllers. A known limitation is that the Info memory can't be
 read or verified as it's not memory mapped.
@@ -6567,7 +6567,7 @@ if @{ [info exists IMEMORY] && [string equal $IMEMORY true] @} @{
 @end example
 @end deffn
 
-@deffn {Flash Driver} msp432
+@deffn {Flash Driver} {msp432}
 All versions of the SimpleLink MSP432 microcontrollers from Texas
 Instruments include internal flash. The msp432 flash driver automatically
 recognizes the specific version's flash parameters and autoconfigures itself.
@@ -6602,7 +6602,7 @@ msp432 bsl lock
 @end deffn
 @end deffn
 
-@deffn {Flash Driver} niietcm4
+@deffn {Flash Driver} {niietcm4}
 This drivers handles the integrated NOR flash on NIIET Cortex-M4
 based controllers. Flash size and sector layout are auto-configured by the driver.
 Main flash memory is called "Bootflash" and has main region and info region.
@@ -6662,7 +6662,7 @@ Show information about flash driver.
 
 @end deffn
 
-@deffn {Flash Driver} nrf5
+@deffn {Flash Driver} {nrf5}
 All members of the nRF51 microcontroller families from Nordic Semiconductor
 include internal flash and use ARM Cortex-M0 core.
 Also, the nRF52832 microcontroller from Nordic Semiconductor, which include
@@ -6687,7 +6687,7 @@ Decodes and shows information from FICR and UICR registers.
 
 @end deffn
 
-@deffn {Flash Driver} ocl
+@deffn {Flash Driver} {ocl}
 This driver is an implementation of the ``on chip flash loader''
 protocol proposed by Pavel Chromy.
 
@@ -6701,7 +6701,7 @@ flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
 @end example
 @end deffn
 
-@deffn {Flash Driver} pic32mx
+@deffn {Flash Driver} {pic32mx}
 The PIC32MX microcontrollers are based on the MIPS 4K cores,
 and integrate flash memory.
 
@@ -6725,7 +6725,7 @@ This will remove any Code Protection.
 @end deffn
 @end deffn
 
-@deffn {Flash Driver} psoc4
+@deffn {Flash Driver} {psoc4}
 All members of the PSoC 41xx/42xx microcontroller family from Cypress
 include internal flash and use ARM Cortex-M0 cores.
 The driver automatically recognizes a number of these chips using
@@ -6759,7 +6759,7 @@ The @var{num} parameter is a value shown by @command{flash banks}.
 @end deffn
 @end deffn
 
-@deffn {Flash Driver} psoc5lp
+@deffn {Flash Driver} {psoc5lp}
 All members of the PSoC 5LP microcontroller family from Cypress
 include internal program flash and use ARM Cortex-M3 cores.
 The driver probes for a number of these chips and autoconfigures itself,
@@ -6785,7 +6785,7 @@ and all row latches in all flash arrays on the device.
 @end deffn
 @end deffn
 
-@deffn {Flash Driver} psoc5lp_eeprom
+@deffn {Flash Driver} {psoc5lp_eeprom}
 All members of the PSoC 5LP microcontroller family from Cypress
 include internal EEPROM and use ARM Cortex-M3 cores.
 The driver probes for a number of these chips and autoconfigures itself,
@@ -6797,7 +6797,7 @@ flash bank $_CHIPNAME.eeprom psoc5lp_eeprom 0x40008000 0 0 0 \
 @end example
 @end deffn
 
-@deffn {Flash Driver} psoc5lp_nvl
+@deffn {Flash Driver} {psoc5lp_nvl}
 All members of the PSoC 5LP microcontroller family from Cypress
 include internal Nonvolatile Latches and use ARM Cortex-M3 cores.
 The driver probes for a number of these chips and autoconfigures itself.
@@ -6822,7 +6822,7 @@ after successful write.
 @end quotation
 @end deffn
 
-@deffn {Flash Driver} psoc6
+@deffn {Flash Driver} {psoc6}
 Supports PSoC6 (CY8C6xxx) family of Cypress microcontrollers.
 PSoC6 is a dual-core device with CM0+ and CM4 cores. Both cores share
 the same Flash/RAM/MMIO address space.
@@ -6890,7 +6890,7 @@ Note: only Main and Work flash regions support Erase operation.
 @end deffn
 @end deffn
 
-@deffn {Flash Driver} sim3x
+@deffn {Flash Driver} {sim3x}
 All members of the SiM3 microcontroller family from Silicon Laboratories
 include internal flash and use ARM Cortex-M3 cores. It supports both JTAG
 and SWD interface.
@@ -6913,7 +6913,7 @@ Lock the flash. To unlock use the @command{sim3x mass_erase} command.
 @end deffn
 @end deffn
 
-@deffn {Flash Driver} stellaris
+@deffn {Flash Driver} {stellaris}
 All members of the Stellaris LM3Sxxx, LM4x and Tiva C microcontroller
 families from Texas Instruments include internal flash. The driver
 automatically recognizes a number of these chips using the chip
@@ -6939,7 +6939,7 @@ applied to all of them.
 @end deffn
 @end deffn
 
-@deffn {Flash Driver} stm32f1x
+@deffn {Flash Driver} {stm32f1x}
 All members of the STM32F0, STM32F1 and STM32F3 microcontroller families
 from STMicroelectronics include internal flash and use ARM Cortex-M0/M3/M4 cores.
 The driver automatically recognizes a number of these chips using
@@ -7001,7 +7001,7 @@ The @var{num} parameter is a value shown by @command{flash banks}.
 @end deffn
 @end deffn
 
-@deffn {Flash Driver} stm32f2x
+@deffn {Flash Driver} {stm32f2x}
 All members of the STM32F2, STM32F4 and STM32F7 microcontroller families from STMicroelectronics
 include internal flash and use ARM Cortex-M3/M4/M7 cores.
 The driver automatically recognizes a number of these chips using
@@ -7066,7 +7066,7 @@ The @var{num} parameter is a value shown by @command{flash banks}, @var{optcr2}
 @end deffn
 @end deffn
 
-@deffn {Flash Driver} stm32h7x
+@deffn {Flash Driver} {stm32h7x}
 All members of the STM32H7 microcontroller families from STMicroelectronics
 include internal flash and use ARM Cortex-M7 core.
 The driver automatically recognizes a number of these chips using
@@ -7134,7 +7134,7 @@ stm32h7x option_write 0 0x20 0x8000000 0x8000000
 @end deffn
 @end deffn
 
-@deffn {Flash Driver} stm32lx
+@deffn {Flash Driver} {stm32lx}
 All members of the STM32L0 and STM32L1 microcontroller families from STMicroelectronics
 include internal flash and use ARM Cortex-M3 and Cortex-M0+ cores.
 The driver automatically recognizes a number of these chips using
@@ -7174,7 +7174,7 @@ The @var{num} parameter is a value shown by @command{flash banks}.
 @end deffn
 @end deffn
 
-@deffn {Flash Driver} stm32l4x
+@deffn {Flash Driver} {stm32l4x}
 All members of the STM32 G0, G4, L4, L4+, L5, WB and WL
 microcontroller families from STMicroelectronics include internal flash
 and use ARM Cortex-M0+, M4 and M33 cores.
@@ -7275,7 +7275,7 @@ The @var{num} parameter is a value shown by @command{flash banks}.
 @end deffn
 @end deffn
 
-@deffn {Flash Driver} str7x
+@deffn {Flash Driver} {str7x}
 All members of the STR7 microcontroller family from STMicroelectronics
 include internal flash and use ARM7TDMI cores.
 The @var{str7x} driver defines one mandatory parameter, @var{variant},
@@ -7292,7 +7292,7 @@ for the specified flash bank.
 @end deffn
 @end deffn
 
-@deffn {Flash Driver} str9x
+@deffn {Flash Driver} {str9x}
 Most members of the STR9 microcontroller family from STMicroelectronics
 include internal flash and use ARM966E cores.
 The str9 needs the flash controller to be configured using
@@ -7317,7 +7317,7 @@ The @var{num} parameter is a value shown by @command{flash banks}.
 
 @end deffn
 
-@deffn {Flash Driver} str9xpec
+@deffn {Flash Driver} {str9xpec}
 @cindex str9xpec
 
 Only use this driver for locking/unlocking the device or configuring the option bytes.
@@ -7412,7 +7412,7 @@ unlock str9 device.
 
 @end deffn
 
-@deffn {Flash Driver} swm050
+@deffn {Flash Driver} {swm050}
 @cindex swm050
 All members of the swm050 microcontroller family from Foshan Synwit Tech.
 
@@ -7429,7 +7429,7 @@ Erases the entire flash bank.
 @end deffn
 
 
-@deffn {Flash Driver} tms470
+@deffn {Flash Driver} {tms470}
 Most members of the TMS470 microcontroller family from Texas Instruments
 include internal flash and use ARM7TDMI cores.
 This driver doesn't require the chip and bus width to be specified.
@@ -7450,7 +7450,7 @@ the flash clock.
 @end deffn
 @end deffn
 
-@deffn {Flash Driver} w600
+@deffn {Flash Driver} {w600}
 W60x series Wi-Fi SoC from WinnerMicro
 are designed with ARM Cortex-M3 and have 1M Byte QFLASH inside.
 The @var{w600} driver uses the @var{target} parameter to select the
@@ -7461,12 +7461,12 @@ flash bank $_FLASHNAME w600 0x08000000 0 0 0 $_TARGETNAMEs
 @end example
 @end deffn
 
-@deffn {Flash Driver} xmc1xxx
+@deffn {Flash Driver} {xmc1xxx}
 All members of the XMC1xxx microcontroller family from Infineon.
 This driver does not require the chip and bus width to be specified.
 @end deffn
 
-@deffn {Flash Driver} xmc4xxx
+@deffn {Flash Driver} {xmc4xxx}
 All members of the XMC4xxx microcontroller family from Infineon.
 This driver does not require the chip and bus width to be specified.
 
@@ -7794,7 +7794,7 @@ As noted above, the @command{nand device} command allows
 driver-specific options and behaviors.
 Some controllers also activate controller-specific commands.
 
-@deffn {NAND Driver} at91sam9
+@deffn {NAND Driver} {at91sam9}
 This driver handles the NAND controllers found on AT91SAM9 family chips from
 Atmel. It takes two extra parameters: address of the NAND chip;
 address of the ECC controller.
@@ -7829,7 +7829,7 @@ is the base address of the PIO controller and @var{pin} is the pin number.
 @end deffn
 @end deffn
 
-@deffn {NAND Driver} davinci
+@deffn {NAND Driver} {davinci}
 This driver handles the NAND controllers found on DaVinci family
 chips from Texas Instruments.
 It takes three extra parameters:
@@ -7847,7 +7847,7 @@ to implement those ECC modes, unless they are disabled using
 the @command{nand raw_access} command.
 @end deffn
 
-@deffn {NAND Driver} lpc3180
+@deffn {NAND Driver} {lpc3180}
 These controllers require an extra @command{nand device}
 parameter: the clock rate used by the controller.
 @deffn {Command} {lpc3180 select} num [mlc|slc]
@@ -7863,12 +7863,12 @@ in the MLC controller mode, but won't change SLC behavior.
 @end deffn
 @comment current lpc3180 code won't issue 5-byte address cycles
 
-@deffn {NAND Driver} mx3
+@deffn {NAND Driver} {mx3}
 This driver handles the NAND controller in i.MX31. The mxc driver
 should work for this chip as well.
 @end deffn
 
-@deffn {NAND Driver} mxc
+@deffn {NAND Driver} {mxc}
 This driver handles the NAND controller found in Freescale i.MX
 chips. It has support for v1 (i.MX27 and i.MX31) and v2 (i.MX35).
 The driver takes 3 extra arguments, chip (@option{mx27},
@@ -7884,7 +7884,7 @@ without parameter query status.
 @end deffn
 @end deffn
 
-@deffn {NAND Driver} orion
+@deffn {NAND Driver} {orion}
 These controllers require an extra @command{nand device}
 parameter: the address of the controller.
 @example
@@ -7896,11 +7896,11 @@ or @code{read_page} methods, so @command{nand raw_access} won't
 change any behavior.
 @end deffn
 
-@deffn {NAND Driver} s3c2410
-@deffnx {NAND Driver} s3c2412
-@deffnx {NAND Driver} s3c2440
-@deffnx {NAND Driver} s3c2443
-@deffnx {NAND Driver} s3c6400
+@deffn {NAND Driver} {s3c2410}
+@deffnx {NAND Driver} {s3c2412}
+@deffnx {NAND Driver} {s3c2440}
+@deffnx {NAND Driver} {s3c2443}
+@deffnx {NAND Driver} {s3c6400}
 These S3C family controllers don't have any special
 @command{nand device} options, and don't define any
 specialized commands.
@@ -7987,7 +7987,7 @@ Drivers may support PLD-specific options to the @command{pld device}
 definition command, and may also define commands usable only with
 that particular type of PLD.
 
-@deffn {FPGA Driver} virtex2 [no_jstart]
+@deffn {FPGA Driver} {virtex2} [no_jstart]
 Virtex-II is a family of FPGAs sold by Xilinx.
 It supports the IEEE 1532 standard for In-System Configuration (ISC).
 
@@ -8756,7 +8756,7 @@ Stops trace data collection.
 
 To use an ETM trace port it must be associated with a driver.
 
-@deffn {Trace Port Driver} dummy
+@deffn {Trace Port Driver} {dummy}
 Use the @option{dummy} driver if you are configuring an ETM that's
 not connected to anything (on-chip ETB or off-chip trace connector).
 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
@@ -8766,7 +8766,7 @@ Associates the ETM for @var{target} with a dummy driver.
 @end deffn
 @end deffn
 
-@deffn {Trace Port Driver} etb
+@deffn {Trace Port Driver} {etb}
 Use the @option{etb} driver if you are configuring an ETM
 to use on-chip ETB memory.
 @deffn {Config Command} {etb config} target etb_tap

commit d4eecfaab57db2a3dbbd4ecdc713ffe61a07d6d8
Author: Antonio Borneo <bor...@gm...>
Date:   Tue Apr 6 23:31:32 2021 +0200

    doc: [2/3] uniform the texinfo syntax for commands definition
    
    To avoid errors in the documentation, like the one fixed by change
    http://openocd.zylin.com/6134/ , use a uniform notation across the
    file so simple copy-paste will work.
    
    Enclose every Command within curly-brackets '{...}', even single
    word commands.
    Patch generated through:
            sed -i 's/^\(@deffn {Command} \)\([^{][^ ]*\)/\1{\2}/' doc/openocd.texi
            sed -i 's/^\(@deffnx {Command} \)\([^{][^ ]*\)/\1{\2}/' doc/openocd.texi
    
    Change-Id: I797e8d9f5ab0aa1936f350b340d3bdd52373f5aa
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/6151
    Tested-by: jenkins

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 247938fae..8b4113aac 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -2115,7 +2115,7 @@ If you disable all access through TCP/IP, you will need to
 use the command line @option{-pipe} option.
 
 @anchor{gdb_port}
-@deffn {Command} gdb_port [number]
+@deffn {Command} {gdb_port} [number]
 @cindex GDB server
 Normally gdb listens to a TCP/IP port, but GDB can also
 communicate via pipes(stdin/out or named pipes). The name
@@ -2148,7 +2148,7 @@ gdb (with 'set remotetimeout') is recommended. An insufficient timeout may
 cause initialization to fail with "Unknown remote qXfer reply: OK".
 @end deffn
 
-@deffn {Command} tcl_port [number]
+@deffn {Command} {tcl_port} [number]
 Specify or query the port used for a simplified RPC
 connection that can be used by clients to issue TCL commands and get the
 output from the Tcl engine.
@@ -2158,7 +2158,7 @@ the port @var{number} defaults to 6666.
 When specified as "disabled", this service is not activated.
 @end deffn
 
-@deffn {Command} telnet_port [number]
+@deffn {Command} {telnet_port} [number]
 Specify or query the
 port on which to listen for incoming telnet connections.
 This port is intended for interaction with one human through TCL commands.
@@ -2177,7 +2177,7 @@ The ones listed here are static and global.
 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
 
 @anchor{gdbbreakpointoverride}
-@deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
+@deffn {Command} {gdb_breakpoint_override} [@option{hard}|@option{soft}|@option{disable}]
 Force breakpoint type for gdb @command{break} commands.
 This option supports GDB GUIs which don't
 distinguish hard versus soft breakpoints, if the default OpenOCD and
@@ -2220,7 +2220,7 @@ Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb v
 The default behaviour is @option{enable}.
 @end deffn
 
-@deffn {Command} gdb_save_tdesc
+@deffn {Command} {gdb_save_tdesc}
 Saves the target description file to the local file system.
 
 The file name is @i{target_name}.xml.
@@ -2265,7 +2265,7 @@ to the various active targets.
 There is a command to manage and monitor that polling,
 which is normally done in the background.
 
-@deffn {Command} poll [@option{on}|@option{off}]
+@deffn {Command} {poll} [@option{on}|@option{off}]
 Poll the current target for its current state.
 (Also, @pxref{targetcurstate,,target curstate}.)
 If that target is in debug mode, architecture
@@ -3598,19 +3598,19 @@ When a board has a reset button connected to SRST line it will
 probably have hardware debouncing, implying you should use this.
 @end deffn
 
-@deffn {Command} jtag_ntrst_assert_width milliseconds
+@deffn {Command} {jtag_ntrst_assert_width} milliseconds
 Minimum amount of time (in milliseconds) OpenOCD should wait
 after asserting nTRST (active-low JTAG TAP reset) before
 allowing it to be deasserted.
 @end deffn
 
-@deffn {Command} jtag_ntrst_delay milliseconds
+@deffn {Command} {jtag_ntrst_delay} milliseconds
 How long (in milliseconds) OpenOCD should wait after deasserting
 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
 @end deffn
 
 @anchor{reset_config}
-@deffn {Command} reset_config mode_flag ...
+@deffn {Command} {reset_config} mode_flag ...
 This command displays or modifies the reset configuration
 of your combination of JTAG board and target in target
 configuration scripts.
@@ -4446,7 +4446,7 @@ foreach t [target names] @{
 @c yep, "target list" would have been better.
 @c plus maybe "target setdefault".
 
-@deffn {Command} targets [name]
+@deffn {Command} {targets} [name]
 @emph{Note: the name of this command is plural. Other target
 command names are singular.}
 
@@ -8032,11 +8032,11 @@ port is 5555.
 
 @section Server Commands
 
-@deffn {Command} exit
+@deffn {Command} {exit}
 Exits the current telnet session.
 @end deffn
 
-@deffn {Command} help [string]
+@deffn {Command} {help} [string]
 With no parameters, prints help text for all commands.
 Otherwise, prints each helptext containing @var{string}.
 Not every command provides helptext.
@@ -8047,7 +8047,7 @@ In most cases, no such restriction is listed; this indicates commands
 which are only available after the configuration stage has completed.
 @end deffn
 
-@deffn {Command} sleep msec [@option{busy}]
+@deffn {Command} {sleep} msec [@option{busy}]
 Wait for at least @var{msec} milliseconds before resuming.
 If @option{busy} is passed, busy-wait instead of sleeping.
 (This option is strongly discouraged.)
@@ -8055,7 +8055,7 @@ Useful in connection with script files
 (@command{script} command and @command{target_name} configuration).
 @end deffn
 
-@deffn {Command} shutdown [@option{error}]
+@deffn {Command} {shutdown} [@option{error}]
 Close the OpenOCD server, disconnecting all clients (GDB, telnet,
 other). If option @option{error} is used, OpenOCD will return a
 non-zero exit code to the parent process.
@@ -8075,7 +8075,7 @@ or its replacement will be automatically executed before OpenOCD exits.
 @end deffn
 
 @anchor{debuglevel}
-@deffn {Command} debug_level [n]
+@deffn {Command} {debug_level} [n]
 @cindex message level
 Display debug level.
 If @var{n} (from 0..4) is provided, then set it to that level.
@@ -8091,7 +8091,7 @@ file (which is normally the server's standard output).
 @xref{Running}.
 @end deffn
 
-@deffn {Command} echo [-n] message
+@deffn {Command} {echo} [-n] message
 Logs a message at "user" priority.
 Output @var{message} to stdout.
 Option "-n" suppresses trailing newline.
@@ -8100,16 +8100,16 @@ echo "Downloading kernel -- please wait"
 @end example
 @end deffn
 
-@deffn {Command} log_output [filename | "default"]
+@deffn {Command} {log_output} [filename | "default"]
 Redirect logging to @var{filename} or set it back to default output;
 the default log output channel is stderr.
 @end deffn
 
-@deffn {Command} add_script_search_dir [directory]
+@deffn {Command} {add_script_search_dir} [directory]
 Add @var{directory} to the file/script search path.
 @end deffn
 
-@deffn {Command} bindto [@var{name}]
+@deffn {Command} {bindto} [@var{name}]
 Specify hostname or IPv4 address on which to listen for incoming
 TCP/IP connections. By default, OpenOCD will listen on the loopback
 interface only. If your network environment is safe, @code{bindto
@@ -8130,7 +8130,7 @@ various operations. The current target may be changed
 by using @command{targets} command with the name of the
 target which should become current.
 
-@deffn {Command} reg [(number|name) [(value|'force')]]
+@deffn {Command} {reg} [(number|name) [(value|'force')]]
 Access a single register by @var{number} or by its @var{name}.
 The target must generally be halted before access to CPU core
 registers is allowed. Depending on the hardware, some other
@@ -8169,8 +8169,8 @@ Debug and trace infrastructure:
 @end example
 @end deffn
 
-@deffn {Command} halt [ms]
-@deffnx {Command} wait_halt [ms]
+@deffn {Command} {halt} [ms]
+@deffnx {Command} {wait_halt} [ms]
 The @command{halt} command first sends a halt request to the target,
 which @command{wait_halt} doesn't.
 Otherwise these behave the same: wait up to @var{ms} milliseconds,
@@ -8204,19 +8204,19 @@ power consumption (because the CPU is needlessly clocked).
 
 @end deffn
 
-@deffn {Command} resume [address]
+@deffn {Command} {resume} [address]
 Resume the target at its current code position,
 or the optional @var{address} if it is provided.
 OpenOCD will wait 5 seconds for the target to resume.
 @end deffn
 
-@deffn {Command} step [address]
+@deffn {Command} {step} [address]
 Single-step the target at its current code position,
 or the optional @var{address} if it is provided.
 @end deffn
 
 @anchor{resetcommand}
-@deffn {Command} reset
+@deffn {Command} {reset}
 @deffnx {Command} {reset run}
 @deffnx {Command} {reset halt}
 @deffnx {Command} {reset init}
@@ -8237,7 +8237,7 @@ The other options will not work on all systems.
 @end itemize
 @end deffn
 
-@deffn {Command} soft_reset_halt
+@deffn {Command} {soft_reset_halt}
 Requesting target halt and executing a soft reset. This is often used
 when a target cannot be reset and halted. The target, after reset is
 released begins to execute code. OpenOCD attempts to stop the CPU and
@@ -8293,10 +8293,10 @@ Please use their TARGET object siblings to avoid making assumptions
 about what TAP is the current target, or about MMU configuration.
 @end enumerate
 
-@deffn {Command} mdd [phys] addr [count]
-@deffnx {Command} mdw [phys] addr [count]
-@deffnx {Command} mdh [phys] addr [count]
-@deffnx {Command} mdb [phys] addr [count]
+@deffn {Command} {mdd} [phys] addr [count]
+@deffnx {Command} {mdw} [phys] addr [count]
+@deffnx {Command} {mdh} [phys] addr [count]
+@deffnx {Command} {mdb} [phys] addr [count]
 Display contents of address @var{addr}, as
 64-bit doublewords (@command{mdd}),
 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
@@ -8310,10 +8310,10 @@ If @var{count} is specified, displays that many units.
 see the @code{mem2array} primitives.)
 @end deffn
 
-@deffn {Command} mwd [phys] addr doubleword [count]
-@deffnx {Command} mww [phys] addr word [count]
-@deffnx {Command} mwh [phys] addr halfword [count]
-@deffnx {Command} mwb [phys] addr byte [count]
+@deffn {Command} {mwd} [phys] addr doubleword [count]
+@deffnx {Command} {mww} [phys] addr word [count]
+@deffnx {Command} {mwh} [phys] addr halfword [count]
+@deffnx {Command} {mwb} [phys] addr byte [count]
 Writes the specified @var{doubleword} (64 bits), @var{word} (32 bits),
 @var{halfword} (16 bits), or @var{byte} (8-bit) value,
 at the specified address @var{addr}.
@@ -11162,7 +11162,7 @@ type target_state state [state-name]
 type target_reset mode [reset-mode]
 @end verbatim
 
-@deffn {Command} tcl_notifications [on/off]
+@deffn {Command} {tcl_notifications} [on/off]
 Toggle output of target notifications to the current Tcl RPC server.
 Only available from the Tcl RPC server.
 Defaults to off.
@@ -11181,7 +11181,7 @@ Target trace data is emitted as a Tcl associative array in the following format.
 type target_trace data [trace-data-hex-encoded]
 @end verbatim
 
-@deffn {Command} tcl_trace [on/off]
+@deffn {Command} {tcl_trace} [on/off]
 Toggle output of target trace data to the current Tcl RPC server.
 Only available from the Tcl RPC server.
 Defaults to off.

commit 7c4458fe283bf01fb6bb7042c00d63ea781d6d15
Author: Antonio Borneo <bor...@gm...>
Date:   Tue Apr 6 23:24:49 2021 +0200

    doc: [1/3] uniform the texinfo syntax for commands definition
    
    To avoid errors in the documentation, like the one fixed by change
    http://openocd.zylin.com/6134/ , use a uniform notation across the
    file so simple copy-paste will work.
    
    Both 'Command' and '{Command}' are in use, with the following
    statistics:
              0 @deffnx {Command}
             45 @deffn {Command}
             31 @deffnx Command
            382 @deffn Command
    
    While 'Command' is the most popular, prefer the version within
    curly-brackets that has to be used for multi-word definition like
    '{NAND Driver}', '{Config Command}', '{FPGA Driver}', ...
    
    Patch generated through:
            sed -i 's/^\(@deffn \)\(Command\)/\1{\2}/' doc/openocd.texi
            sed -i 's/^\(@deffnx \)\(Command\)/\1{\2}/' doc/openocd.texi
    
    Change-Id: If692bbf7e546c5287f466a6aa6940d42b3d4655d
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/6150
    Reviewed-by: Yasushi SHOJI <ya...@sp...>
    Tested-by: jenkins

diff --git a/doc/openocd.texi b/doc/openocd.texi
index e39ff86f3..247938fae 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -2265,7 +2265,7 @@ to the various active targets.
 There is a command to manage and monitor that polling,
 which is normally done in the background.
 
-@deffn Command poll [@option{on}|@option{off}]
+@deffn {Command} poll [@option{on}|@option{off}]
 Poll the current target for its current state.
 (Also, @pxref{targetcurstate,,target curstate}.)
 If that target is in debug mode, architecture
@@ -2339,11 +2339,11 @@ Use the adapter driver @var{name} to connect to the
 target.
 @end deffn
 
-@deffn Command {adapter list}
+@deffn {Command} {adapter list}
 List the debug adapter drivers that have been built into
 the running copy of OpenOCD.
 @end deffn
-@deffn Command {adapter transports} transport_name+
+@deffn {Command} {adapter transports} transport_name+
 Specifies the transports supported by this debug adapter.
 The adapter driver builds-in similar knowledge; use this only
 when external configuration (such as jumpering) changes what
@@ -2352,12 +2352,12 @@ the hardware can support.
 
 
 
-@deffn Command {adapter name}
+@deffn {Command} {adapter name}
 Returns the name of the debug adapter driver being used.
 @end deffn
 
 @anchor{adapter_usb_location}
-@deffn Command {adapter usb location} [<bus>-<port>[.<port>]...]
+@deffn {Command} {adapter usb location} [<bus>-<port>[.<port>]...]
 Displays or specifies the physical USB port of the adapter to use. The path
 roots at @var{bus} and walks down the physical ports, with each
 @var{port} option specifying a deeper level in the bus topology, the last
@@ -2393,7 +2393,7 @@ Optionally sets that option first.
 Olimex ARM-JTAG-EW USB adapter
 This has one driver-specific command:
 
-@deffn Command {armjtagew_info}
+@deffn {Command} {armjtagew_info}
 Logs some status
 @end deffn
 @end deffn
@@ -2992,7 +2992,7 @@ When using PPDEV to access the parallel port, use the number of the parallel por
 you may encounter a problem.
 @end deffn
 
-@deffn Command {parport_toggling_time} [nanoseconds]
+@deffn {Command} {parport_toggling_time} [nanoseconds]
 Displays how many nanoseconds the hardware needs to toggle TCK;
 the parport driver uses this value to obey the
 @command{adapter speed} configuration.
@@ -3283,12 +3283,12 @@ As noted earlier, depending on the version of OpenOCD you use,
 and the debug adapter you are using,
 several transports may be available to
 communicate with debug targets (or perhaps to program flash memory).
-@deffn Command {transport list}
+@deffn {Command} {transport list}
 displays the names of the transports supported by this
 version of OpenOCD.
 @end deffn
 
-@deffn Command {transport select} @option{transport_name}
+@deffn {Command} {transport select} @option{transport_name}
 Select which of the supported transports to use in this OpenOCD session.
 
 When invoked with @option{transport_name}, attempts to select the named
@@ -3335,12 +3335,12 @@ driver} (in which case the command is @command{transport select hla_swd})
 or @ref{st_link_dap_interface,the st-link interface driver} (in which case
 the command is @command{transport select dapdirect_swd}).
 
-@deffn Command {swd newdap} ...
+@deffn {Command} {swd newdap} ...
 Declares a single DAP which uses SWD transport.
 Parameters are currently the same as "jtag newtap" but this is
 expected to change.
 @end deffn
-@deffn Command {swd wcr trn prescale}
+@deffn {Command} {swd wcr trn prescale}
 Updates TRN (turnaround delay) and prescaling.fields of the
 Wire Control Register (WCR).
 No parameters: displays current settings.
@@ -3415,7 +3415,7 @@ may not be the fastest solution.
 instead of @command{adapter speed}, but only for (ARM) cores and boards
 which support adaptive clocking.
 
-@deffn Command {adapter speed} max_speed_kHz
+@deffn {Command} {adapter speed} max_speed_kHz
 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
 JTAG interfaces usually support a limited number of
 speeds. The speed actually used won't be faster
@@ -3585,13 +3585,13 @@ needing to cope with both architecture and board specific constraints.
 
 @section Commands for Handling Resets
 
-@deffn Command {adapter srst pulse_width} milliseconds
+@deffn {Command} {adapter srst pulse_width} milliseconds
 Minimum amount of time (in milliseconds) OpenOCD should wait
 after asserting nSRST (active-low system reset) before
 allowing it to be deasserted.
 @end deffn
 
-@deffn Command {adapter srst delay} milliseconds
+@deffn {Command} {adapter srst delay} milliseconds
 How long (in milliseconds) OpenOCD should wait after deasserting
 nSRST (active-low system reset) before starting new JTAG operations.
 When a board has a reset button connected to SRST line it will
@@ -3768,7 +3768,7 @@ This is done by calling @command{jtag arp_init}
 (or @command{jtag arp_init-reset}).
 @end deffn
 
-@deffn Command {jtag arp_init}
+@deffn {Command} {jtag arp_init}
 This validates the scan chain using just the four
 standard JTAG signals (TMS, TCK, TDI, TDO).
 It starts by issuing a JTAG-only reset.
@@ -3781,7 +3781,7 @@ If these tests all pass, TAP @code{setup} events are
 issued to all TAPs with handlers for that event.
 @end deffn
 
-@deffn Command {jtag arp_init-reset}
+@deffn {Command} {jtag arp_init-reset}
 This uses TRST and SRST to try resetting
 everything on the JTAG scan chain
 (and anything else connected to SRST).
@@ -3889,7 +3889,7 @@ Actual config files typically use a variable such as @code{$_CHIPNAME}
 instead of literals like @option{str912}, to support more than one chip
 of each type.  @xref{Config File Guidelines}.
 
-@deffn Command {jtag names}
+@deffn {Command} {jtag names}
 Returns the names of all current TAPs in the scan chain.
 Use @command{jtag cget} or @command{jtag tapisenabled}
 to examine attributes and state of each TAP.
@@ -3900,7 +3900,7 @@ foreach t [jtag names] @{
 @end example
 @end deffn
 
-@deffn Command {scan_chain}
+@deffn {Command} {scan_chain}
 Displays the TAPs in the scan chain configuration,
 and their status.
 The set of TAPs listed by this command is fixed by
@@ -3934,7 +3934,7 @@ and underscores are OK; while others (including dots!) are not.
 @section TAP Declaration Commands
 
 @c shouldn't this be(come) a {Config Command}?
-@deffn Command {jtag newtap} chipname tapname configparams...
+@deffn {Command} {jtag newtap} chipname tapname configparams...
 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
 and configured according to the various @var{configparams}.
 
@@ -4026,12 +4026,12 @@ devices do not set the ack bit until sometime later.
 
 @section Other TAP commands
 
-@deffn Command {jtag cget} dotted.name @option{-idcode}
+@deffn {Command} {jtag cget} dotted.name @option{-idcode}
 Get the value of the IDCODE found in hardware.
 @end deffn
 
-@deffn Command {jtag cget} dotted.name @option{-event} event_name
-@deffnx Command {jtag configure} dotted.name @option{-event} event_name handler
+@deffn {Command} {jtag cget} dotted.name @option{-event} event_name
+@deffnx {Command} {jtag configure} dotted.name @option{-event} event_name handler
 At this writing this TAP attribute
 mechanism is limited and used mostly for event handling.
 (It is not a direct analogue of the @code{cget}/@code{configure}
@@ -4152,7 +4152,7 @@ uses quotes to evaluate @code{$CHIP} when the event is configured.
 Using brackets @{ @} would cause it to be evaluated later,
 at runtime, when it might have a different value.
 
-@deffn Command {jtag tapdisable} dotted.name
+@deffn {Command} {jtag tapdisable} dotted.name
 If necessary, disables the tap
 by sending it a @option{tap-disable} event.
 Returns the string "1" if the tap
@@ -4160,7 +4160,7 @@ specified by @var{dotted.name} is enabled,
 and "0" if it is disabled.
 @end deffn
 
-@deffn Command {jtag tapenable} dotted.name
+@deffn {Command} {jtag tapenable} dotted.name
 If necessary, enables the tap
 by sending it a @option{tap-enable} event.
 Returns the string "1" if the tap
@@ -4168,7 +4168,7 @@ specified by @var{dotted.name} is enabled,
 and "0" if it is disabled.
 @end deffn
 
-@deffn Command {jtag tapisenabled} dotted.name
+@deffn {Command} {jtag tapisenabled} dotted.name
 Returns the string "1" if the tap
 specified by @var{dotted.name} is enabled,
 and "0" if it is disabled.
@@ -4260,7 +4260,7 @@ instead of "@option{-chain-position} @var{dotted.name}" when the target is creat
 
 The @command{dap} command group supports the following sub-commands:
 
-@deffn Command {dap create} dap_name @option{-chain-position} dotted.name configparams...
+@deffn {Command} {dap create} dap_name @option{-chain-position} dotted.name configparams...
 Declare a DAP instance named @var{dap_name} linked to the JTAG tap
 @var{dotted.name}. This also creates a new command (@command{dap_name})
 which is used for various purposes including additional configuration.
@@ -4277,17 +4277,17 @@ devices do not set the ack bit until sometime later.
 @end itemize
 @end deffn
 
-@deffn Command {dap names}
+@deffn {Command} {dap names}
 This command returns a list of all registered DAP objects. It it useful mainly
 for TCL scripting.
 @end deffn
 
-@deffn Command {dap info} [num]
+@deffn {Command} {dap info} [num]
 Displays the ROM table for MEM-AP @var{num},
 defaulting to the currently selected AP of the currently selected target.
 @end deffn
 
-@deffn Command {dap init}
+@deffn {Command} {dap init}
 Initialize all registered DAPs. This command is used internally
 during initialization. It can be issued at any time after the
 initialization, too.
@@ -4295,27 +4295,27 @@ initialization, too.
 
 The following commands exist as subcommands of DAP instances:
 
-@deffn Command {$dap_name info} [num]
+@deffn {Command} {$dap_name info} [num]
 Displays the ROM table for MEM-AP @var{num},
 defaulting to the currently selected AP.
 @end deffn
 
-@deffn Command {$dap_name apid} [num]
+@deffn {Command} {$dap_name apid} [num]
 Displays ID register from AP @var{num}, defaulting to the currently selected AP.
 @end deffn
 
 @anchor{DAP subcommand apreg}
-@deffn Command {$dap_name apreg} ap_num reg [value]
+@deffn {Command} {$dap_name apreg} ap_num reg [value]
 Displays content of a register @var{reg} from AP @var{ap_num}
 or set a new value @var{value}.
 @var{reg} is byte address of a word register, 0, 4, 8 ... 0xfc.
 @end deffn
 
-@deffn Command {$dap_name apsel} [num]
+@deffn {Command} {$dap_name apsel} [num]
 Select AP @var{num}, defaulting to 0.
 @end deffn
 
-@deffn Command {$dap_name dpreg} reg [value]
+@deffn {Command} {$dap_name dpreg} reg [value]
 Displays the content of DP register at address @var{reg}, or set it to a new
 value @var{value}.
 
@@ -4327,18 +4327,18 @@ In case of JTAG it only assumes values 0, 4, 8 and 0xc.
 background activity by OpenOCD while you are operating at such low-level.
 @end deffn
 
-@deffn Command {$dap_name baseaddr} [num]
+@deffn {Command} {$dap_name baseaddr} [num]
 Displays debug base address from MEM-AP @var{num},
 defaulting to the currently selected AP.
 @end deffn
 
-@deffn Command {$dap_name memaccess} [value]
+@deffn {Command} {$dap_name memaccess} [value]
 Displays the number of extra tck cycles in the JTAG idle to use for MEM-AP
 memory bus access [0-255], giving additional time to respond to reads.
 If @var{value} is defined, first assigns that.
 @end deffn
 
-@deffn Command {$dap_name apcsw} [value [mask]]
+@deffn {Command} {$dap_name apcsw} [value [mask]]
 Displays or changes CSW bit pattern for MEM-AP transfers.
 
 At the begin of each memory access the CSW pattern is extended (bitwise or-ed)
@@ -4381,7 +4381,7 @@ xxx.dap apcsw default
 @end example
 @end deffn
 
-@deffn Command {$dap_name ti_be_32_quirks} [@option{enable}]
+@deffn {Command} {$dap_name ti_be_32_quirks} [@option{enable}]
 Set/get quirks mode for TI TMS450/TMS570 processors
 Disabled by default
 @end deffn
@@ -4430,11 +4430,11 @@ are examples; and there are many more.
 
 Several commands let you examine the list of targets:
 
-@deffn Command {target current}
+@deffn {Command} {target current}
 Returns the name of the current target.
 @end deffn
 
-@deffn Command {target names}
+@deffn {Command} {target names}
 Lists the names of all current targets in the list.
 @example
 foreach t [target names] @{
@@ -4446,7 +4446,7 @@ foreach t [target names] @{
 @c yep, "target list" would have been better.
 @c plus maybe "target setdefault".
 
-@deffn Command targets [name]
+@deffn {Command} targets [name]
 @emph{Note: the name of this command is plural. Other target
 command names are singular.}
 
@@ -4477,7 +4477,7 @@ It's easy to see what target types are supported,
 since there's a command to list them.
 
 @anchor{targettypes}
-@deffn Command {target types}
+@deffn {Command} {target types}
 Lists all supported target types.
 At this writing, the supported CPU types are:
 
@@ -4612,7 +4612,7 @@ That may be needed to let you write the boot loader into flash,
 in order to ``de-brick'' your board; or to load programs into
 external DDR memory without having run the boot loader.
 
-@deffn Command {target create} target_name type configparams...
+@deffn {Command} {target create} target_name type configparams...
 This command creates a GDB debug target that refers to a specific JTAG tap.
 It enters that target into a list, and creates a new
 command (@command{@var{target_name}}) which is used for various
@@ -4637,7 +4637,7 @@ You @emph{must} set the @code{-chain-position @var{dotted.name}} or
 @end itemize
 @end deffn
 
-@deffn Command {$target_name configure} configparams...
+@deffn {Command} {$target_name configure} configparams...
 The options accepted by this command may also be
 specified as parameters to @command{target create}.
 Their values can later be queried one at a time by
@@ -4760,18 +4760,18 @@ omap3530.cpu  mww 0x5555 123
 
 The commands supported by OpenOCD target objects are:
 
-@deffn Command {$target_name arp_examine} @option{allow-defer}
-@deffnx Command {$target_name arp_halt}
-@deffnx Command {$target_name arp_poll}
-@deffnx Command {$target_name arp_reset}
-@deffnx Command {$target_name arp_waitstate}
+@deffn {Command} {$target_name arp_examine} @option{allow-defer}
+@deffnx {Command} {$target_name arp_halt}
+@deffnx {Command} {$target_name arp_poll}
+@deffnx {Command} {$target_name arp_reset}
+@deffnx {Command} {$target_name arp_waitstate}
 Internal OpenOCD scripts (most notably @file{startup.tcl})
 use these to deal with specific reset cases.
 They are not otherwise documented here.
 @end deffn
 
-@deffn Command {$target_name array2mem} arrayname width address count
-@deffnx Command {$target_name mem2array} arrayname width address count
+@deffn {Command} {$target_name array2mem} arrayname width address count
+@deffnx {Command} {$target_name mem2array} arrayname width address count
 These provide an efficient script-oriented interface to memory.
 The @code{array2mem} primitive writes bytes, halfwords, or words;
 while @code{mem2array} reads them.
@@ -4793,7 +4793,7 @@ and neither store nor return those values.
 @end itemize
 @end deffn
 
-@deffn Command {$target_name cget} queryparm
+@deffn {Command} {$target_name cget} queryparm
 Each configuration parameter accepted by
 @command{$target_name configure}
 can be individually queried, to return its current value.
@@ -4826,7 +4826,7 @@ foreach name [target names] @{
 @end deffn
 
 @anchor{targetcurstate}
-@deffn Command {$target_name curstate}
+@deffn {Command} {$target_name curstate}
 Displays the current target state:
 @code{debug-running},
 @code{halted},
@@ -4835,22 +4835,22 @@ Displays the current target state:
 (Also, @pxref{eventpolling,,Event Polling}.)
 @end deffn
 
-@deffn Command {$target_name eventlist}
+@deffn {Command} {$target_name eventlist}
 Displays a table listing all event handlers
 currently associated with this target.
 @xref{targetevents,,Target Events}.
 @end deffn
 
-@deffn Command {$target_name invoke-event} event_name
+@deffn {Command} {$target_name invoke-event} event_name
 Invokes the handler for the event named @var{event_name}.
 (This is primarily intended for use by OpenOCD framework
 code, for example by the reset code in @file{startup.tcl}.)
 @end deffn
 
-@deffn Command {$target_name mdd} [phys] addr [count]
-@deffnx Command {$target_name mdw} [phys] addr [count]
-@deffnx Command {$target_name mdh} [phys] addr [count]
-@deffnx Command {$target_name mdb} [phys] addr [count]
+@deffn {Command} {$target_name mdd} [phys] addr [count]
+@deffnx {Command} {$target_name mdw} [phys] addr [count]
+@deffnx {Command} {$target_name mdh} [phys] addr [count]
+@deffnx {Command} {$target_name mdb} [phys] addr [count]
 Display contents of address @var{addr}, as
 64-bit doublewords (@command{mdd}),
 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
@@ -4864,10 +4864,10 @@ If @var{count} is specified, displays that many units.
 see the @code{mem2array} primitives.)
 @end deffn
 
-@deffn Command {$target_name mwd} [phys] addr doubleword [count]
-@deffnx Command {$target_name mww} [phys] addr word [count]
-@deffnx Command {$target_name mwh} [phys] addr halfword [count]
-@deffnx Command {$target_name mwb} [phys] addr byte [count]
+@deffn {Command} {$target_name mwd} [phys] addr doubleword [count]
+@deffnx {Command} {$target_name mww} [phys] addr word [count]
+@deffnx {Command} {$target_name mwh} [phys] addr halfword [count]
+@deffnx {Command} {$target_name mwb} [phys] addr byte [count]
 Writes the specified @var{doubleword} (64 bits), @var{word} (32 bits),
 @var{halfword} (16 bits), or @var{byte} (8-bit) value,
 at the specified address @var{addr}.
@@ -5105,20 +5105,20 @@ Use it in board specific configuration files, not interactively.
 @end deffn
 
 @comment less confusing would be: "flash list" (like "nand list")
-@deffn Command {flash banks}
+@deffn {Command} {flash banks}
 Prints a one-line summary of each device that was
 declared using @command{flash bank}, numbered from zero.
 Note that this is the @emph{plural} form;
 the @emph{singular} form is a very different command.
 @end deffn
 
-@deffn Command {flash list}
+@deffn {Command} {flash list}
 Retrieves a list of associative arrays for each device that was
 declared using @command{flash bank}, numbered from zero.
 This returned list can be manipulated easily from within scripts.
 @end deffn
 
-@deffn Command {flash probe} num
+@deffn {Command} {flash probe} num
 Identify the flash, or validate the parameters of the configured flash. Operation
 depends on the flash type.
 The @var{num} parameter is a value shown by @command{flash banks}.
@@ -5180,7 +5180,7 @@ Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
 and AT91SAM7 on-chip flash.
 @xref{flashprotect,,flash protect}.
 
-@deffn Command {flash erase_sector} num first last
+@deffn {Command} {flash erase_sector} num first last
 Erase sectors in bank @var{num}, starting at sector @var{first}
 up to and including @var{last}.
 Sector numbering starts at 0.
@@ -5189,7 +5189,7 @@ specifies "to the end of the flash bank".
 The @var{num} parameter is a value shown by @command{flash banks}.
 @end deffn
 
-@deffn Command {flash erase_address} [@option{pad}] [@option{unlock}] address length
+@deffn {Command} {flash erase_address} [@option{pad}] [@option{unlock}] address length
 Erase sectors starting at @var{address} for @var{length} bytes.
 Unless @option{pad} is specified, @math{address} must begin a
 flash sector, and @math{address + length - 1} must end a sector.
@@ -5203,10 +5203,10 @@ If @option{unlock} is specified, then the flash is unprotected
 before erase starts.
 @end deffn
 
-@deffn Command {flash filld} address double-word length
-@deffnx Command {flash fillw} address word length
-@deffnx Command {flash fillh} address halfword length
-@deffnx Command {flash fillb} address byte length
+@deffn {Command} {flash filld} address double-word length
+@deffnx {Command} {flash fillw} address word length
+@deffnx {Command} {flash fillh} address halfword length
+@deffnx {Command} {flash fillb} address byte length
 Fills flash memory with the specified @var{double-word} (64 bits), @var{word} (32 bits),
 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
 starting at @var{address} and continuing
@@ -5220,9 +5220,9 @@ each block, and the specified length must stay within that bank.
 @end deffn
 @comment no current checks for errors if fill blocks touch multiple banks!
 
-@deffn Command {flash mdw} addr [count]
-@deffnx...
 
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