[OpenOCD-user] Configuration for atsama5d27-som1

[Con P. <co...@kp...>]

Hi all,

I'm trying to debug a Microchip atsam5d27-som1 SoM using jtag.
https://www.microchip.com/wwwproducts/en/ATSAMA5D27-SOM1

For the story, in case someone had the same problem, the jtag interface
is NOT enabled by default if you buy a plain SoM (it is if you use the
Eval. Kit). For the jtag to be enabled on a custom board, one has to
power the SoM, connect the USB-A interface and select the JTAG_IOSET3
using Microchip's sam-ba tool.


Anyway, I have now a "working" JTAG, that I connect to using OpenOCD
and attach a gdb debugger.
The internal ROM runs, loads the 2nd stage bootloader (at91bootstrap)
and I can attach to it.
I can also issue "monitor init" and "load" to load the bootloader again
and restart it.

So far so good. I can inspect the code, set breakpoints, step, run ok,
untill I hit a specific instruction, which attempts to write to an
internal register and set the main clock source.
It sets the SLOW_CLOCK value to the CSS field of the PMC_MCKR register.

At this point I get the error
	Info : DAP transaction stalled (WAIT) - slowing down

And the debugger is useless. If I try to use GDB I get:
	Info : The target is not running when halt was requested,
stopping GDB.
And then OpenOCD gets into a loop, printing every second or so:
	Error: timeout waiting for DSCR bit change
	Error: Error waiting for read dcc
Then, the error persists and I may have to power cycle the board in
order for OpenOCD to work again.

I also get the same error if I just run/continue the program (without
stepping until the "bad" instruction first)
Also, the program being run is ok (at least for this part) because the
bootloader proceeds if there is no debugger attached.


I have tried this and got the same behaviour using different setups:
   1. BusBlaster-v3 (kt-link flashed) using
interface/ftdi/dp_busblaster_kt-link.cfg on a custom atsama5d27-som1
board
   2. BusBlaster-v3 (kt-link flashed) using
interface/ftdi/dp_busblaster_kt-link.cfg on atsama5d27-som1-ev1
development kit (using external debugger)
   3. Using the embedded JLink debugger of atsama5d27-som1-ev1
development kit, using configuration interface/jlink.cfg


I do not see any official target configuration for atsama5d2.
What I am using is a patch that I have found here
https://sourceforge.net/p/openocd/mailman/message/36738590/
which seems to not have been merged yet.

The board (if not using jlink) does not support adaptive speed, so the
only thing that I have changed in the above configuration is to set the
clock to 3kHz



Comparing my configuration to other board configurations, I see that it
is too simple, or that there are no specific initialisations etc.

I suppose that I need to define all the details of the board, right?
This SoM includes separate to the processor, flash, eeprom etc... 
But how do I overcome the problem of broken jtag when setting the clock
for start?


Thanks in advance,
Con


PS: is this a discussion for the devel-list instead?