[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.10.0-1524-g861e75f54

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commit 861e75f54efbcc1e0717192c6ddb120478d6c226
Author: Antonio Borneo <bor...@gm...>
Date:   Thu Nov 5 23:02:55 2020 +0100

    jimtcl: switch to github
    
    The 'historically' main repository of jimtcl in repo.or.cz has
    lost sync with the github current main repository since July 2020.
    The new tag 0.80 is not present in repo.or.cz.
    The developer of jimtcl has been in contact with the admins of
    repo.or.cz to fix the not better described sync issues and has now
    decided to stop any further tentative. A new README has been added
    on 2020-11-19 in the old repository to inform that it is abandoned
    in favour of github. The old content in repo.or.cz will remain due
    to forks that still exists in the same server.
    
    Switch OpenOCD git submodules to fetch jimtcl code from the main
    development repository in github.
    
    Change-Id: Ia2d59f1347ccfe374538b38131badfd46054eb91
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5948
    Tested-by: jenkins
    Reviewed-by: Andreas Fritiofson <and...@gm...>

diff --git a/.gitmodules b/.gitmodules
index 958c5d901..23ffa2543 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -3,7 +3,7 @@
 	url = https://repo.or.cz/git2cl.git
 [submodule "jimtcl"]
 	path = jimtcl
-	url = https://repo.or.cz/jimtcl.git
+	url = https://github.com/msteveb/jimtcl.git
 [submodule "src/jtag/drivers/libjaylink"]
 	path = src/jtag/drivers/libjaylink
 	url = https://repo.or.cz/libjaylink.git

commit 1d3d87695c62be88d4a87c7d57de6084d654396b
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Nov 15 22:10:58 2020 +0100

    target/register: use an array of uint8_t for register's value
    
    The use of 'void *' makes the pointer arithmetic incompatible with
    standard C, even if this is allowed by GCC extensions.
    The use of 'void *' can also hide incorrect pointer assignments.
    
    Switch to 'uint8_t *' and add GCC warning flag to track any use of
    pointer arithmetic extension.
    
    Change-Id: Ic4d15a232834cd6b374330f70e2473a359b1607f
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5937
    Tested-by: jenkins
    Reviewed-by: Andreas Fritiofson <and...@gm...>

diff --git a/configure.ac b/configure.ac
index 9cb20ad89..c8978b94d 100644
--- a/configure.ac
+++ b/configure.ac
@@ -833,6 +833,7 @@ AS_IF([test "x${gcc_wextra}" = "xyes"], [
   GCC_WARNINGS="${GCC_WARNINGS} -Wbad-function-cast"
   GCC_WARNINGS="${GCC_WARNINGS} -Wcast-align"
   GCC_WARNINGS="${GCC_WARNINGS} -Wredundant-decls"
+  GCC_WARNINGS="${GCC_WARNINGS} -Wpointer-arith"
 ])
 AS_IF([test "x${gcc_werror}" = "xyes"], [
   GCC_WARNINGS="${GCC_WARNINGS} -Werror"
diff --git a/src/target/arc.c b/src/target/arc.c
index cec6441a5..ffe974532 100644
--- a/src/target/arc.c
+++ b/src/target/arc.c
@@ -305,7 +305,7 @@ static int arc_init_reg(struct target *target, struct reg *reg,
 	/* Initialize struct reg */
 	reg->name = reg_desc->name;
 	reg->size = 32; /* All register in ARC are 32-bit */
-	reg->value = &reg_desc->reg_value;
+	reg->value = reg_desc->reg_value;
 	reg->type = &arc_reg_type;
 	reg->arch_info = reg_desc;
 	reg->caller_save = true; /* @todo should be configurable. */
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index d992aa78b..797f61c93 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -1393,7 +1393,7 @@ static int arm7_9_full_context(struct target *target)
 	struct arm *arm = &arm7_9->arm;
 	struct {
 		uint32_t value;
-		void *reg_p;
+		uint8_t *reg_p;
 	} read_cache[6 * (16 + 1)];
 	int read_cache_idx = 0;
 
diff --git a/src/target/etm.c b/src/target/etm.c
index 93dbd2948..faa941fed 100644
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -279,7 +279,7 @@ static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info,
 
 		reg->name = r->name;
 		reg->size = r->size;
-		reg->value = &ereg->value;
+		reg->value = ereg->value;
 		reg->arch_info = ereg;
 		reg->type = &etm_scan6_type;
 		reg++;
diff --git a/src/target/register.h b/src/target/register.h
index 1bae81183..5f1c25fb4 100644
--- a/src/target/register.h
+++ b/src/target/register.h
@@ -127,7 +127,7 @@ struct reg {
 	bool caller_save;
 	/* Pointer to place where the value is stored, in the format understood by
 	 * the binarybuffer.h functions. */
-	void *value;
+	uint8_t *value;
 	/* The stored value needs to be written to the target. */
 	bool dirty;
 	/* When true, value is valid. */
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index 53af07ec3..0d1cee1bf 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -4128,7 +4128,7 @@ int riscv_init_registers(struct target *target)
 		reg_name += strlen(reg_name) + 1;
 		assert(reg_name < info->reg_names + target->reg_cache->num_regs *
 				max_reg_name_len);
-		r->value = &info->reg_cache_values[number];
+		r->value = info->reg_cache_values[number];
 	}
 
 	return ERROR_OK;
diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h
index 7e74cf730..d943134e2 100644
--- a/src/target/riscv/riscv.h
+++ b/src/target/riscv/riscv.h
@@ -68,8 +68,8 @@ typedef struct {
 
 	/* OpenOCD's register cache points into here. This is not per-hart because
 	 * we just invalidate the entire cache when we change which hart is
-	 * selected. */
-	uint64_t reg_cache_values[RISCV_MAX_REGISTERS];
+	 * selected. Use an array of 8 uint8_t per register. */
+	uint8_t reg_cache_values[RISCV_MAX_REGISTERS][8];
 
 	/* Single buffer that contains all register names, instead of calling
 	 * malloc for each register. Needs to be freed when reg_list is freed. */

commit b5e015357ad4ae1fbb286f9bf6c22a563ab93eb7
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Nov 22 13:02:32 2020 +0100

    mips_mips64: fix minor host endianness bug
    
    Commit 80f1a92bd798 ("mips64: Add generic mips64 target support")
    adds a log of the target's program counter in function
    mips_mips64_debug_entry() by directly casting the little-endian
    buffer in pc->value.
    This is going to print an incorrect value on big-endian hosts.
    
    Use the function buf_get_u64() to return the register value.
    
    Not tested on real HW. Issue identified with GCC compiler flag
    '-Wcast-align=strict' after change http://openocd.zylin.com/5937/
    ("target/register: use an array of uint8_t for register's value").
    
    Change-Id: Icbda2b54a03fdec287c804e623f5db4252f9cd2a
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Fixes: 80f1a92bd798 ("mips64: Add generic mips64 target support")
    Reviewed-on: http://openocd.zylin.com/5944
    Tested-by: jenkins
    Reviewed-by: Andreas Fritiofson <and...@gm...>

diff --git a/src/target/mips_mips64.c b/src/target/mips_mips64.c
index f941af517..0fc089726 100644
--- a/src/target/mips_mips64.c
+++ b/src/target/mips_mips64.c
@@ -62,7 +62,7 @@ static int mips_mips64_debug_entry(struct target *target)
 	mips_mips64_examine_debug_reason(target);
 
 	LOG_DEBUG("entered debug state at PC 0x%" PRIx64 ", target->state: %s",
-		  *(uint64_t *)pc->value, target_state_name(target));
+		  buf_get_u64(pc->value, 0, 64), target_state_name(target));
 
 	return ERROR_OK;
 }

commit a56b7291911b4f42718d406dd2de857db4c11e0f
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Nov 22 12:29:04 2020 +0100

    arm7_9_common: fix host endianness bug in arm7_9_full_context()
    
    The original code passes to ->read_core_regs() and to
    ->read_xpsr() the pointer to the little-endian buffer reg.value.
    This is incorrect because the two functions above require a
    pointer to uint32_t, since they already run the conversion with
    arm_le_to_h_u32() in the jtag callback.
    This causes a mismatch on big-endian host and the registers get
    read with the incorrect endianness.
    
    Use an intermediate buffer to read the registers as uint32_t and
    to track the destination reg.value pointer, then copy the value in
    reg.value after the call to jtag_execute_queue().
    
    Tested with qemu-armeb and an OpenOCD built through buildroot
    configured for cortex-a7 big-endian.
    
    Note that if jtag_execute_queue() fails, the openocd register
    cache is not updated, so the already modified flags 'valid' and
    'dirty' are incorrect. This part should be moved after the call to
    jtag_execute_queue() too.
    
    Change-Id: Iba70d964ffbb74bf0860bfd9d299f218e3bc65bf
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5943
    Tested-by: jenkins
    Reviewed-by: Andreas Fritiofson <and...@gm...>

diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index d70d27377..d992aa78b 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -1391,6 +1391,11 @@ static int arm7_9_full_context(struct target *target)
 	int retval;
 	struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 	struct arm *arm = &arm7_9->arm;
+	struct {
+		uint32_t value;
+		void *reg_p;
+	} read_cache[6 * (16 + 1)];
+	int read_cache_idx = 0;
 
 	LOG_DEBUG("-");
 
@@ -1433,10 +1438,12 @@ static int arm7_9_full_context(struct target *target)
 			for (j = 0; j < 15; j++) {
 				if (!ARMV4_5_CORE_REG_MODE(arm->core_cache,
 						armv4_5_number_to_mode(i), j).valid) {
-					reg_p[j] = (uint32_t *)ARMV4_5_CORE_REG_MODE(
+					read_cache[read_cache_idx].reg_p = ARMV4_5_CORE_REG_MODE(
 							arm->core_cache,
 							armv4_5_number_to_mode(i),
 							j).value;
+					reg_p[j] = &read_cache[read_cache_idx].value;
+					read_cache_idx++;
 					mask |= 1 << j;
 					ARMV4_5_CORE_REG_MODE(arm->core_cache,
 						armv4_5_number_to_mode(i),
@@ -1454,9 +1461,10 @@ static int arm7_9_full_context(struct target *target)
 			/* check if the PSR has to be read */
 			if (!ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i),
 					16).valid) {
-				arm7_9->read_xpsr(target,
-					(uint32_t *)ARMV4_5_CORE_REG_MODE(arm->core_cache,
-						armv4_5_number_to_mode(i), 16).value, 1);
+				read_cache[read_cache_idx].reg_p = ARMV4_5_CORE_REG_MODE(arm->core_cache,
+					armv4_5_number_to_mode(i), 16).value;
+				arm7_9->read_xpsr(target, &read_cache[read_cache_idx].value, 1);
+				read_cache_idx++;
 				ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i),
 					16).valid = true;
 				ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i),
@@ -1472,6 +1480,14 @@ static int arm7_9_full_context(struct target *target)
 	retval = jtag_execute_queue();
 	if (retval != ERROR_OK)
 		return retval;
+	/*
+	 * FIXME: regs in cache should be tagged as 'valid' only now,
+	 * not before the jtag_execute_queue()
+	 */
+	while (read_cache_idx) {
+		read_cache_idx--;
+		buf_set_u32(read_cache[read_cache_idx].reg_p, 0, 32, read_cache[read_cache_idx].value);
+	}
 	return ERROR_OK;
 }
 

commit 62686ab161e9c46a620dd592b2767634e9483c20
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Nov 22 00:33:59 2020 +0100

    armv4_5: fix output of command 'arm reg'
    
    Commit fc2abe63fd3c ("armv7m: use generic arm::core_mode") adds
    two special modes for ARMv6M and ARMv7M in struct arm_mode_data[].
    While these modes do not have any additional register to be dumped
    by command 'arm reg', the command still prints an header for these
    modes but not followed by any register.
    
    Detect the special modes for ARMv6M and ARMv7M and skip them to
    avoid printing the useless header.
    
    Change-Id: I04145769e5742624f143c910eebf9a6f6d8e3cdc
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Fixes: fc2abe63fd3c ("armv7m: use generic arm::core_mode")
    Reviewed-on: http://openocd.zylin.com/5942
    Tested-by: jenkins

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 8ac482504..b725853fe 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -856,6 +856,9 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
 		char *sep = "\n";
 		char *shadow = "";
 
+		if (!arm_mode_data[mode].n_indices)
+			continue;
+
 		/* label this bank of registers (or shadows) */
 		switch (arm_mode_data[mode].psr) {
 			case ARM_MODE_SYS:

commit 693b8501e5b1233b87420b1c9d5cbbb3b943b285
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Nov 22 00:15:44 2020 +0100

    armv4_5: fix segmentation fault in command 'arm reg'
    
    Commit fed713104904 ("armv4_5: support weirdo ARMv6 secure monitor
    mode") introduces the secure mode 28 of ARMv6 as a synonymous of
    mode 22 (MON), but does not add it in the switch/case in command
    'arm reg'.
    When command 'arm reg' scans the array arm_mode_data[] on targets
    without secure modes, it does not detect the new secure mode as
    not supported by the architecture, thus triggers a segmentation
    fault when it try to read the register's value from unallocated
    memory.
    Issue detected with target arm926ejs.
    
    Add the new mode in the switch/case and treat it as the mode MON.
    
    Change-Id: I2b72cc558e097879a7ee6ea601200bfda6b60270
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Fixes: fed713104904 ("armv4_5: support weirdo ARMv6 secure monitor mode")
    Reviewed-on: http://openocd.zylin.com/5941
    Tested-by: jenkins
    Reviewed-by: Tarek BOCHKATI <tar...@gm...>

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 7da28e349..8ac482504 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -869,6 +869,7 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
 					continue;
 			/* FALLTHROUGH */
 			case ARM_MODE_MON:
+			case ARM_MODE_1176_MON:
 				if (arm->core_type != ARM_CORE_TYPE_SEC_EXT
 					&& arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
 					continue;

-----------------------------------------------------------------------

Summary of changes:
 .gitmodules                |  2 +-
 configure.ac               |  1 +
 src/target/arc.c           |  2 +-
 src/target/arm7_9_common.c | 24 ++++++++++++++++++++----
 src/target/armv4_5.c       |  4 ++++
 src/target/etm.c           |  2 +-
 src/target/mips_mips64.c   |  2 +-
 src/target/register.h      |  2 +-
 src/target/riscv/riscv.c   |  2 +-
 src/target/riscv/riscv.h   |  4 ++--
 10 files changed, 33 insertions(+), 12 deletions(-)


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