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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.10.0-1516-gd459a2d27
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From: OpenOCD-Gerrit <ope...@us...> - 2020-12-02 23:17:07
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The branch, master has been updated
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via 646c3c99020f8fdf7ee0adf821582238aac4a80c (commit)
from a8edbd0200560bfd412c5c563908d860ed2c96a6 (commit)
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- Log -----------------------------------------------------------------
commit d459a2d27df52643dc8932827a63467a14f7c162
Author: Tomas Vanek <va...@fb...>
Date: Fri Mar 1 21:44:27 2019 +0100
adi_v5_swd: wait for readable DPIDR, ABORT if stalled
Reading of DPIDR is the very first operation after JTAG to SWD sequence.
Without this change if DPIDR read fails then swd connect fails.
Keep trying JTAG to SWD sequence and DPIDR read until success
or timeout 0.5 sec. It makes setting of adapter srst delay on SWD transport
mostly unnecessary.
Also test for ERROR_WAIT (which should not occur according to
IHI 0031E B4.3.2 but a quirk is known) and if bus is kept stalled
then issue abort to make the next connect possible.
Change-Id: Id8fe6618605bbeb4fed5061e987ed55de90a35f2
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: http://openocd.zylin.com/5730
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
Reviewed-by: Andreas Fritiofson <and...@gm...>
diff --git a/src/target/adi_v5_swd.c b/src/target/adi_v5_swd.c
index ee30ff7ba..b25181e21 100644
--- a/src/target/adi_v5_swd.c
+++ b/src/target/adi_v5_swd.c
@@ -118,26 +118,69 @@ static int swd_connect(struct adiv5_dap *dap)
}
}
- /* Note, debugport_init() does setup too */
- swd->switch_seq(JTAG_TO_SWD);
- /* Clear link state, including the SELECT cache. */
- dap->do_reconnect = false;
- dap_invalidate_cache(dap);
+ int64_t timeout = timeval_ms() + 500;
- swd_queue_dp_read(dap, DP_DPIDR, &dpidr);
+ do {
+ /* Note, debugport_init() does setup too */
+ swd->switch_seq(JTAG_TO_SWD);
- /* force clear all sticky faults */
- swd_clear_sticky_errors(dap);
+ /* Clear link state, including the SELECT cache. */
+ dap->do_reconnect = false;
+ dap_invalidate_cache(dap);
+
+ status = swd_queue_dp_read(dap, DP_DPIDR, &dpidr);
+ if (status == ERROR_OK) {
+ status = swd_run_inner(dap);
+ if (status == ERROR_OK)
+ break;
+ }
+
+ alive_sleep(1);
+
+ } while (timeval_ms() < timeout);
+
+ if (status != ERROR_OK) {
+ LOG_ERROR("Error connecting DP: cannot read IDR");
+ return status;
+ }
+
+ LOG_INFO("SWD DPIDR %#8.8" PRIx32, dpidr);
+
+ do {
+ dap->do_reconnect = false;
- status = swd_run_inner(dap);
+ /* force clear all sticky faults */
+ swd_clear_sticky_errors(dap);
+
+ status = swd_run_inner(dap);
+ if (status != ERROR_WAIT)
+ break;
+
+ alive_sleep(10);
+
+ } while (timeval_ms() < timeout);
+
+ /* IHI 0031E B4.3.2:
+ * "A WAIT response must not be issued to the ...
+ * ... writes to the ABORT register"
+ * swd_clear_sticky_errors() writes to the ABORT register only.
+ *
+ * Unfortunately at least Microchip SAMD51/E53/E54 returns WAIT
+ * in a corner case. Just try if ABORT resolves the problem.
+ */
+ if (status == ERROR_WAIT) {
+ LOG_WARNING("Connecting DP: stalled AP operation, issuing ABORT");
- if (status == ERROR_OK) {
- LOG_INFO("SWD DPIDR %#8.8" PRIx32, dpidr);
dap->do_reconnect = false;
+
+ swd->write_reg(swd_cmd(false, false, DP_ABORT),
+ DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
+ status = swd_run_inner(dap);
+ }
+
+ if (status == ERROR_OK)
status = dap_dp_init(dap);
- } else
- dap->do_reconnect = true;
return status;
}
commit 646c3c99020f8fdf7ee0adf821582238aac4a80c
Author: Tomas Vanek <va...@fb...>
Date: Mon Jun 29 13:34:07 2020 +0200
arm_adi_v5: prevent possibly endless recursion in dap_dp_init()
If dap_dp_read_atomic() in 30 trials loop fails, dap->do_reconnect is set.
Following dap_dp_read_atomic() calls dap_queue_dp_read() which in case
of SWD transport calls swd_queue_dp_read(). It starts
with swd_check_reconnect() and it calls swd_connect() because
dap->do_reconnect is set. swd_connect() does some initialization,
reads DPIDR and calls dap_dp_init() again!
Moreover if dap_dp_init() is called from cortex_m_reset_(de)assert()
one level of recursion is necessary to reconnect the target.
Introduce dap_dp_init_or_reconnect() for use in cortex_m reset
and similar.
Remove loop of 30 atomic reads of DP_STAT to prevent unwanted recursion.
Change-Id: I54052fdefe50bf5f7c7b59fe751fe2063d5710c9
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: http://openocd.zylin.com/5729
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
Reviewed-by: Andreas Fritiofson <and...@gm...>
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 31c14597b..59bb186c6 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -652,35 +652,22 @@ int dap_dp_init(struct adiv5_dap *dap)
LOG_DEBUG("%s", adiv5_dap_name(dap));
+ dap->do_reconnect = false;
dap_invalidate_cache(dap);
/*
* Early initialize dap->dp_ctrl_stat.
- * In jtag mode only, if the following atomic reads fail and set the
- * sticky error, it will trigger the clearing of the sticky. Without this
- * initialization system and debug power would be disabled while clearing
- * the sticky error bit.
+ * In jtag mode only, if the following queue run (in dap_dp_poll_register)
+ * fails and sets the sticky error, it will trigger the clearing
+ * of the sticky. Without this initialization system and debug power
+ * would be disabled while clearing the sticky error bit.
*/
dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
- for (size_t i = 0; i < 30; i++) {
- /* DP initialization */
-
- retval = dap_dp_read_atomic(dap, DP_CTRL_STAT, NULL);
- if (retval == ERROR_OK)
- break;
- }
-
/*
* This write operation clears the sticky error bit in jtag mode only and
* is ignored in swd mode. It also powers-up system and debug domains in
* both jtag and swd modes, if not done before.
- * Actually we do not need to clear the sticky error here because it has
- * been already cleared (if it was set) in the previous atomic read. This
- * write could be removed, but this initial part of dap_dp_init() is the
- * result of years of fine tuning and there are strong concerns about any
- * unnecessary code change. It doesn't harm, so let's keep it here and
- * preserve the historical sequence of read/write operations!
*/
retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat | SSTICKYERR);
if (retval != ERROR_OK)
@@ -731,6 +718,35 @@ int dap_dp_init(struct adiv5_dap *dap)
return retval;
}
+/**
+ * Initialize a DAP or do reconnect if DAP is not accessible.
+ *
+ * @param dap The DAP being initialized.
+ */
+int dap_dp_init_or_reconnect(struct adiv5_dap *dap)
+{
+ LOG_DEBUG("%s", adiv5_dap_name(dap));
+
+ /*
+ * Early initialize dap->dp_ctrl_stat.
+ * In jtag mode only, if the following atomic reads fail and set the
+ * sticky error, it will trigger the clearing of the sticky. Without this
+ * initialization system and debug power would be disabled while clearing
+ * the sticky error bit.
+ */
+ dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
+
+ dap->do_reconnect = false;
+
+ dap_dp_read_atomic(dap, DP_CTRL_STAT, NULL);
+ if (dap->do_reconnect) {
+ /* dap connect calls dap_dp_init() after transport dependent initialization */
+ return dap->ops->connect(dap);
+ } else {
+ return dap_dp_init(dap);
+ }
+}
+
/**
* Initialize a DAP. This sets up the power domains, prepares the DP
* for further use, and arranges to use AP #0 for all AP operations
diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index f319a062d..8edfaa816 100644
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -550,6 +550,7 @@ int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
/* Initialisation of the debug system, power domains and registers */
int dap_dp_init(struct adiv5_dap *dap);
+int dap_dp_init_or_reconnect(struct adiv5_dap *dap);
int mem_ap_init(struct adiv5_ap *ap);
/* Invalidate cached DP select and cached TAR and CSW of all APs */
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 94cf82489..fae2aac5d 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -1202,11 +1202,13 @@ static int cortex_m_assert_reset(struct target *target)
if (retval3 != ERROR_OK)
LOG_DEBUG("Ignoring AP write error right after reset");
- retval3 = dap_dp_init(armv7m->debug_ap->dap);
- if (retval3 != ERROR_OK)
+ retval3 = dap_dp_init_or_reconnect(armv7m->debug_ap->dap);
+ if (retval3 != ERROR_OK) {
LOG_ERROR("DP initialisation failed");
-
- else {
+ /* The error return value must not be propagated in this case.
+ * SYSRESETREQ or VECTRESET have been possibly triggered
+ * so reset processing should continue */
+ } else {
/* I do not know why this is necessary, but it
* fixes strange effects (step/resume cause NMI
* after reset) on LM3S6918 -- Michael Schwingen
@@ -1249,7 +1251,8 @@ static int cortex_m_deassert_reset(struct target *target)
if ((jtag_reset_config & RESET_HAS_SRST) &&
!(jtag_reset_config & RESET_SRST_NO_GATING) &&
target_was_examined(target)) {
- int retval = dap_dp_init(armv7m->debug_ap->dap);
+
+ int retval = dap_dp_init_or_reconnect(armv7m->debug_ap->dap);
if (retval != ERROR_OK) {
LOG_ERROR("DP initialisation failed");
return retval;
-----------------------------------------------------------------------
Summary of changes:
src/target/adi_v5_swd.c | 69 +++++++++++++++++++++++++++++++++++++++----------
src/target/arm_adi_v5.c | 52 ++++++++++++++++++++++++-------------
src/target/arm_adi_v5.h | 1 +
src/target/cortex_m.c | 13 ++++++----
4 files changed, 99 insertions(+), 36 deletions(-)
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