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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.10.0-1503-gb1f488ec1
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From: OpenOCD-Gerrit <ope...@us...> - 2020-11-15 21:10:24
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via 608299484d52a60082bb7ff5bcde5249f9a3a1de (commit)
via f32ca2d25dae5526bf0bd70b1143aa34412fc7ec (commit)
from fc91936be7bac7a84636d6b907ac545876263f3e (commit)
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- Log -----------------------------------------------------------------
commit b1f488ec1ea4c8b5410026610c621f85b5ff17f3
Author: Tomas Vanek <va...@fb...>
Date: Thu Oct 22 20:36:30 2020 +0200
target/armv7m, cortex_m: fix misleading comments
Change-Id: I4fea29f07f4d3b8b2578b538ef0eef5f1eea285f
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: http://openocd.zylin.com/5876
Tested-by: jenkins
Reviewed-by: Christopher Head <ch...@za...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index 13370b54b..f14ce0d88 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -493,8 +493,7 @@ int armv7m_start_algorithm(struct target *target,
return ERROR_TARGET_NOT_HALTED;
}
- /* refresh core register cache
- * Not needed if core register cache is always consistent with target process state */
+ /* Store all non-debug execution registers to armv7m_algorithm_info context */
for (unsigned i = 0; i < armv7m->arm.core_cache->num_regs; i++) {
armv7m_algorithm_info->context[i] = buf_get_u32(
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index fc72c0ed0..94cf82489 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -817,15 +817,19 @@ static int cortex_m_resume(struct target *target, int current,
* in parallel with disabled interrupts can cause local faults
* to not be taken.
*
- * REVISIT this clearly breaks non-debug execution, since the
- * PRIMASK register state isn't saved/restored... workaround
- * by never resuming app code after debug execution.
+ * This breaks non-debug (application) execution if not
+ * called from armv7m_start_algorithm() which saves registers.
*/
buf_set_u32(r->value, 0, 1, 1);
r->dirty = true;
r->valid = true;
- /* Make sure we are in Thumb mode */
+ /* Make sure we are in Thumb mode, set xPSR.T bit */
+ /* armv7m_start_algorithm() initializes entire xPSR register.
+ * This duplicity handles the case when cortex_m_resume()
+ * is used with the debug_execution flag directly,
+ * not called through armv7m_start_algorithm().
+ */
r = armv7m->arm.cpsr;
buf_set_u32(r->value, 24, 1, 1);
r->dirty = true;
commit 608299484d52a60082bb7ff5bcde5249f9a3a1de
Author: Tomas Vanek <va...@fb...>
Date: Thu Oct 22 13:18:40 2020 +0200
flash/nor/psoc6: remove setting of xPSR.T bit from sromalgo_prepare()
PSoC6 erases flash to 0x00 not more common 0xff, so a device
with erased flash loads xPSR.T=0 from the zeroed reset vector.
Wrong thumb bit value caused a target algorithm failed with HardFault.
The low level write to xPSR solved the problem only if xPSR cached
copy was not marked dirty.
Later commit 49bd64347a21f5e12b33c256171b3035126d1260 fixed T setting
for all Cortex-M target algorithms.
Since 49bd64 this part of code is useless as xPSR target_start_algorithm()
sets always xPSR dirty so the effect of the low level write is eliminated
(and proper setting of thumb bit is ensured in target_start_algorithm())
Change-Id: I68aea5e921fbc6203f2fe91a45f10d22869327de
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: http://openocd.zylin.com/5875
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/psoc6.c b/src/flash/nor/psoc6.c
index 19d483bab..931404e3e 100644
--- a/src/flash/nor/psoc6.c
+++ b/src/flash/nor/psoc6.c
@@ -151,12 +151,6 @@ static int sromalgo_prepare(struct target *target)
if (hr != ERROR_OK)
return hr;
- /* Restore THUMB bit in xPSR register */
- const struct armv7m_common *cm = target_to_armv7m(target);
- hr = cm->store_core_reg_u32(target, ARMV7M_REGSEL_xPSR, 0x01000000);
- if (hr != ERROR_OK)
- return hr;
-
/* Allocate Working Area for Stack and Flash algorithm */
hr = target_alloc_working_area(target, RAM_STACK_WA_SIZE, &g_stack_area);
if (hr != ERROR_OK)
commit f32ca2d25dae5526bf0bd70b1143aa34412fc7ec
Author: Tomas Vanek <va...@fb...>
Date: Thu Oct 22 12:50:24 2020 +0200
target/cortex_m: remove wrong xPSR.ICI/IT bits handling
If a Cortex-M (not M0, M0+) target was stopped in the middle of
a conditional IT block or in the load/store multiple instruction,
cortex_m_debug_entry() used wrong xPSR bits to detect it and then
cleared 8 bits of the exception number from xPSR
- probably wrong bit mask again.
I believe clearing of the ICI/IT bits in cortex_m_debug_entry() has no
reason as Cortex-M does not use instruction injecting.
Remove the wrong code.
The change was originally a part of http://openocd.zylin.com/4862
It is now re-submitted as #4862 is not ready.
Change-Id: If91cd91d1b81b2684f7d5f10cf20452cde1a7f56
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: http://openocd.zylin.com/5874
Tested-by: jenkins
Reviewed-by: Christopher Head <ch...@za...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 7b3f3c70e..fc72c0ed0 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -527,12 +527,6 @@ static int cortex_m_debug_entry(struct target *target)
r = arm->cpsr;
xPSR = buf_get_u32(r->value, 0, 32);
- /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
- if (xPSR & 0xf00) {
- r->dirty = r->valid;
- cortex_m_store_core_reg_u32(target, ARMV7M_REGSEL_xPSR, xPSR & ~0xff);
- }
-
/* Are we in an exception handler */
if (xPSR & 0x1FF) {
armv7m->exception_number = (xPSR & 0x1FF);
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/psoc6.c | 6 ------
src/target/armv7m.c | 3 +--
src/target/cortex_m.c | 18 ++++++++----------
3 files changed, 9 insertions(+), 18 deletions(-)
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