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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.10.0-1407-gf2c83fade
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From: OpenOCD-Gerrit <ope...@us...> - 2020-09-20 13:36:27
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via 6e339478999bab6ae029a3b24fa79ddc698e1a4f (commit)
from c20f65b63202bcf2735dbf1e8085fa978b6104c5 (commit)
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- Log -----------------------------------------------------------------
commit f2c83fade3ea7e51e5c9283aa3ff94632a41cc55
Author: Tarek BOCHKATI <tar...@gm...>
Date: Tue Aug 11 14:06:04 2020 +0100
cortex_m: read and display core security state
Change-Id: I0fce3c66af7e98df2dc2258daf0d6af661e29ae7
Signed-off-by: Laurent LEMELE <lau...@st...>
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: http://openocd.zylin.com/5798
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/arm.h b/src/target/arm.h
index 3450260f0..d97a95edf 100644
--- a/src/target/arm.h
+++ b/src/target/arm.h
@@ -197,6 +197,9 @@ struct arm {
/** Flag reporting armv6m based core. */
bool is_armv6m;
+ /** Flag reporting armv8m based core. */
+ bool is_armv8m;
+
/** Floating point or VFP version, 0 if disabled. */
int arm_vfp_version;
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 62e08468d..4b0ea50cc 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -502,6 +502,18 @@ static int cortex_m_debug_entry(struct target *target)
if (retval != ERROR_OK)
return retval;
+ /* examine PE security state */
+ bool secure_state = false;
+ if (armv7m->arm.is_armv8m) {
+ uint32_t dscsr;
+
+ retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DSCSR, &dscsr);
+ if (retval != ERROR_OK)
+ return retval;
+
+ secure_state = (dscsr & DSCSR_CDS) == DSCSR_CDS;
+ }
+
/* Examine target state and mode
* First load register accessible through core debug port */
int num_regs = arm->core_cache->num_regs;
@@ -548,9 +560,10 @@ static int cortex_m_debug_entry(struct target *target)
if (armv7m->exception_number)
cortex_m_examine_exception_reason(target);
- LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
+ LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", cpu in %s state, target->state: %s",
arm_mode_name(arm->core_mode),
buf_get_u32(arm->pc->value, 0, 32),
+ secure_state ? "Secure" : "Non-Secure",
target_state_name(target));
if (armv7m->post_debug_entry) {
@@ -2156,6 +2169,9 @@ int cortex_m_examine(struct target *target)
/* Get CPU Type */
i = (cpuid >> 4) & 0xf;
+ /* Check if it is an ARMv8-M core */
+ armv7m->arm.is_armv8m = true;
+
switch (cpuid & ARM_CPUID_PARTNO_MASK) {
case CORTEX_M23_PARTNO:
i = 23;
@@ -2166,6 +2182,7 @@ int cortex_m_examine(struct target *target)
break;
default:
+ armv7m->arm.is_armv8m = false;
break;
}
diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h
index 794eda4c7..354532823 100644
--- a/src/target/cortex_m.h
+++ b/src/target/cortex_m.h
@@ -50,6 +50,7 @@
#define DCB_DCRSR 0xE000EDF4
#define DCB_DCRDR 0xE000EDF8
#define DCB_DEMCR 0xE000EDFC
+#define DCB_DSCSR 0xE000EE08
#define DCRSR_WnR BIT(16)
@@ -114,6 +115,9 @@
#define VC_MMERR BIT(4)
#define VC_CORERESET BIT(0)
+/* DCB_DSCSR bit and field definitions */
+#define DSCSR_CDS BIT(16)
+
/* NVIC registers */
#define NVIC_ICTR 0xE000E004
#define NVIC_ISE0 0xE000E100
commit 6e339478999bab6ae029a3b24fa79ddc698e1a4f
Author: Tarek BOCHKATI <tar...@gm...>
Date: Tue Aug 11 12:56:36 2020 +0100
armv8-m: add SecureFault exception
Change-Id: I4e1963631e834b6334bc917e956c2db4464b7b08
Signed-off-by: Laurent LEMELE <lau...@st...>
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: http://openocd.zylin.com/5797
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index 017d693ce..ea6ee6117 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -48,7 +48,7 @@
static const char * const armv7m_exception_strings[] = {
"", "Reset", "NMI", "HardFault",
- "MemManage", "BusFault", "UsageFault", "RESERVED",
+ "MemManage", "BusFault", "UsageFault", "SecureFault",
"RESERVED", "RESERVED", "RESERVED", "SVCall",
"DebugMonitor", "RESERVED", "PendSV", "SysTick"
};
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 5ea928a32..62e08468d 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -445,6 +445,14 @@ static int cortex_m_examine_exception_reason(struct target *target)
if (retval != ERROR_OK)
return retval;
break;
+ case 7: /* Secure Fault */
+ retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFSR, &except_sr);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFAR, &except_ar);
+ if (retval != ERROR_OK)
+ return retval;
+ break;
case 11: /* SVCall */
break;
case 12: /* Debug Monitor */
diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h
index a767f93c5..794eda4c7 100644
--- a/src/target/cortex_m.h
+++ b/src/target/cortex_m.h
@@ -114,6 +114,7 @@
#define VC_MMERR BIT(4)
#define VC_CORERESET BIT(0)
+/* NVIC registers */
#define NVIC_ICTR 0xE000E004
#define NVIC_ISE0 0xE000E100
#define NVIC_ICSR 0xE000ED04
@@ -127,6 +128,8 @@
#define NVIC_DFSR 0xE000ED30
#define NVIC_MMFAR 0xE000ED34
#define NVIC_BFAR 0xE000ED38
+#define NVIC_SFSR 0xE000EDE4
+#define NVIC_SFAR 0xE000EDE8
/* NVIC_AIRCR bits */
#define AIRCR_VECTKEY (0x5FAul << 16)
-----------------------------------------------------------------------
Summary of changes:
src/target/arm.h | 3 +++
src/target/armv7m.c | 2 +-
src/target/cortex_m.c | 27 ++++++++++++++++++++++++++-
src/target/cortex_m.h | 7 +++++++
4 files changed, 37 insertions(+), 2 deletions(-)
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