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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.10.0-1344-ga80650ac3
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From: OpenOCD-Gerrit <ope...@us...> - 2020-07-26 19:11:34
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- Log -----------------------------------------------------------------
commit a80650ac3c7f0f1de3b5d1e45ce03d0ccc3d288e
Author: Jiri Kastner <cz1...@gm...>
Date: Wed Jul 15 11:31:51 2020 +0200
tcl/target: add Rockchip RK3308 target
Change-Id: Ia8c2cec0761c37623fa8a416bcfc405f2af6a6b3
Signed-off-by: Jiri Kastner <cz1...@gm...>
Reviewed-on: http://openocd.zylin.com/5774
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/tcl/target/rk3308.cfg b/tcl/target/rk3308.cfg
new file mode 100644
index 000000000..d3d409eaf
--- /dev/null
+++ b/tcl/target/rk3308.cfg
@@ -0,0 +1,69 @@
+# Rockchip RK3308 Target
+# https://rockchip.fr/RK3308%20datasheet%20V1.5.pdf
+# https://dl.radxa.com/rockpis/docs/hw/datasheets/Rockchip%20RK3308TRM%20V1.1%20Part1-20180810.pdf
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME rk3308
+}
+
+#
+# Main DAP
+#
+if { [info exists DAP_TAPID] } {
+ set _DAP_TAPID $DAP_TAPID
+} else {
+ set _DAP_TAPID 0x2ba01477
+}
+
+adapter speed 12000
+
+transport select swd
+
+# declare the one SWD tap to access the DAP
+swd newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID -ignore-version
+
+# create the DAP
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0
+
+# declare the 8 main application cores
+set _TARGETNAME $_CHIPNAME.core
+set _smp_command ""
+
+set $_TARGETNAME.base(0) 0x81010000
+set $_TARGETNAME.base(1) 0x81012000
+set $_TARGETNAME.base(2) 0x81014000
+set $_TARGETNAME.base(3) 0x81016000
+
+set $_TARGETNAME.cti(0) 0x81018000
+set $_TARGETNAME.cti(1) 0x81019000
+set $_TARGETNAME.cti(2) 0x8101a000
+set $_TARGETNAME.cti(3) 0x8101b000
+
+set _cores 4
+for { set _core 0 } { $_core < $_cores } { incr _core 1 } {
+
+ cti create cti$_core -dap $_CHIPNAME.dap -ctibase [set $_TARGETNAME.cti($_core)] -ap-num 0
+
+ set _command "target create ${_TARGETNAME}$_core aarch64 \
+ -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core \
+ -dbgbase [set $_TARGETNAME.base($_core)]"
+
+ if { $_core != 0 } {
+ set _smp_command "$_smp_command ${_TARGETNAME}$_core"
+ } else {
+ # uncomment to use hardware threads pseudo rtos
+ # set _command "$_command -rtos hwthread"
+ set _command "$_command -work-area-size 0x40000 -work-area-phys 0xfff80000 \
+ -work-area-backup 0"
+ set _smp_command "target smp ${_TARGETNAME}$_core"
+ }
+
+ eval $_command
+}
+
+eval $_smp_command
+
+targets ${_TARGETNAME}0
commit 2f40d069a16ec6c87cbce76c6d1ac20921d47919
Author: Jiri Kastner <cz1...@gm...>
Date: Wed Jul 15 11:30:34 2020 +0200
src/target/arm_adi_v5.c: add Cortex-A35 related entries
ROM Table registers:
https://developer.arm.com/documentation/100236/0100/debug/rom-table/rom-table-peripheral-identification-registers
Debug reisters:
https://developer.arm.com/documentation/100236/0100/debug/memory-mapped-debug-registers/external-debug-peripheral-identification-registers
PMU registers:
https://developer.arm.com/documentation/100236/0100/debug/pmu-registers/performance-monitors-peripheral-identification-registers
CTI registers:
https://developer.arm.com/documentation/100236/0100/debug/cti-registers/cti-peripheral-identification-registers
Change-Id: Ibd57d91fb9b66bc46929f4e93d0bf23c2a32f11a
Signed-off-by: Jiri Kastner <cz1...@gm...>
Reviewed-on: http://openocd.zylin.com/5773
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 241c00b04..11bf18549 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -1080,6 +1080,7 @@ static const struct {
{ ARM_ID, 0x4a3, "Cortex-A53 ROM", "(v7 Memory Map ROM Table)", },
{ ARM_ID, 0x4a4, "Cortex-A72 ROM", "(ROM Table)", },
{ ARM_ID, 0x4a9, "Cortex-A9 ROM", "(ROM Table)", },
+ { ARM_ID, 0x4aa, "Cortex-A35 ROM", "(v8 Memory Map ROM Table)", },
{ ARM_ID, 0x4af, "Cortex-A15 ROM", "(ROM Table)", },
{ ARM_ID, 0x4b5, "Cortex-R5 ROM", "(ROM Table)", },
{ ARM_ID, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", },
@@ -1087,6 +1088,7 @@ static const struct {
{ ARM_ID, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", },
{ ARM_ID, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", },
{ ARM_ID, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", },
+ { ARM_ID, 0x4e0, "Cortex-A35 ROM", "(v7 Memory Map ROM Table)", },
{ ARM_ID, 0x906, "CoreSight CTI", "(Cross Trigger)", },
{ ARM_ID, 0x907, "CoreSight ETB", "(Trace Buffer)", },
{ ARM_ID, 0x908, "CoreSight CSTF", "(Trace Funnel)", },
@@ -1129,6 +1131,7 @@ static const struct {
{ ARM_ID, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", },
{ ARM_ID, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", },
{ ARM_ID, 0x9d8, "Cortex-A72 PMU", "(Performance Monitor Unit)", },
+ { ARM_ID, 0x9da, "Cortex-A35 PMU/CTI/ETM", "(Performance Monitor Unit/Cross Trigger/ETM)", },
{ ARM_ID, 0xc05, "Cortex-A5 Debug", "(Debug Unit)", },
{ ARM_ID, 0xc07, "Cortex-A7 Debug", "(Debug Unit)", },
{ ARM_ID, 0xc08, "Cortex-A8 Debug", "(Debug Unit)", },
@@ -1139,6 +1142,7 @@ static const struct {
{ ARM_ID, 0xc15, "Cortex-R5 Debug", "(Debug Unit)", },
{ ARM_ID, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", },
{ ARM_ID, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", },
+ { ARM_ID, 0xd04, "Cortex-A35 Debug", "(Debug Unit)", },
{ ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", },
{ ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", },
{ 0x097, 0x9af, "MSP432 ROM", "(ROM Table)" },
-----------------------------------------------------------------------
Summary of changes:
src/target/arm_adi_v5.c | 4 +++
tcl/target/rk3308.cfg | 69 +++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 73 insertions(+)
create mode 100644 tcl/target/rk3308.cfg
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