[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.10.0-1290-g2e6904eef

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- Log -----------------------------------------------------------------
commit 2e6904eef5e81e71453168ed8c6f649e3a5c0f6c
Author: Lucas <pu...@x3...>
Date:   Sun May 17 16:42:39 2020 +0100

    aarch64: Add support for debugging in HYP mode on ARMv8-A cores
    
    When debugging an ARMv8-A/AArch32 target running HYP mode, OpenOCD would
    throw the following error to GDB on most operations (step, set breakpoint):
    
            cannot read system control register in this mode
    
    The mode in question is 0x1A, a privilege level 2 mode available on cores
    that have the virtualization extensions (such as the Raspi 3).
    
    Note: this mode is only used when running in AArch32 compatibility mode.
    
    Signed-off-by: Lucas Jenss <pu...@x3...>
    Signed-off-by: Tarek BOCHKATI <tar...@gm...>
    Change-Id: Ia8673ff34c5b3eed60e24d8da57c3ca8197a60c2
    Reviewed-on: http://openocd.zylin.com/5255
    Tested-by: jenkins
    Reviewed-by: Lucas Jenß <luc...@gm...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 87176f638..01d0e9462 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -99,12 +99,14 @@ static int aarch64_restore_system_control_reg(struct target *target)
 		case ARM_MODE_ABT:
 		case ARM_MODE_FIQ:
 		case ARM_MODE_IRQ:
+		case ARM_MODE_HYP:
 		case ARM_MODE_SYS:
 			instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0);
 			break;
 
 		default:
-			LOG_INFO("cannot read system control register in this mode");
+			LOG_ERROR("cannot read system control register in this mode: (%s : 0x%" PRIx32 ")",
+					armv8_mode_name(armv8->arm.core_mode), armv8->arm.core_mode);
 			return ERROR_FAIL;
 		}
 
@@ -172,6 +174,7 @@ static int aarch64_mmu_modify(struct target *target, int enable)
 	case ARM_MODE_ABT:
 	case ARM_MODE_FIQ:
 	case ARM_MODE_IRQ:
+	case ARM_MODE_HYP:
 	case ARM_MODE_SYS:
 		instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0);
 		break;
@@ -1033,12 +1036,14 @@ static int aarch64_post_debug_entry(struct target *target)
 	case ARM_MODE_ABT:
 	case ARM_MODE_FIQ:
 	case ARM_MODE_IRQ:
+	case ARM_MODE_HYP:
 	case ARM_MODE_SYS:
 		instr = ARMV4_5_MRC(15, 0, 0, 1, 0, 0);
 		break;
 
 	default:
-		LOG_INFO("cannot read system control register in this mode");
+		LOG_ERROR("cannot read system control register in this mode: (%s : 0x%" PRIx32 ")",
+				armv8_mode_name(armv8->arm.core_mode), armv8->arm.core_mode);
 		return ERROR_FAIL;
 	}
 
diff --git a/src/target/armv8.c b/src/target/armv8.c
index 61f11f24a..0c8508661 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -73,6 +73,10 @@ static const struct {
 		.name = "ABT",
 		.psr = ARM_MODE_ABT,
 	},
+	{
+		.name = "HYP",
+		.psr = ARM_MODE_HYP,
+	},
 	{
 		.name = "SYS",
 		.psr = ARM_MODE_SYS,
diff --git a/src/target/armv8.h b/src/target/armv8.h
index 1a611455d..c5ee5fd87 100644
--- a/src/target/armv8.h
+++ b/src/target/armv8.h
@@ -330,6 +330,7 @@ static inline unsigned int armv8_curel_from_core_mode(enum arm_mode core_mode)
 	}
 }
 
+const char *armv8_mode_name(unsigned psr_mode);
 void armv8_select_reg_access(struct armv8_common *armv8, bool is_aarch64);
 int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value);
 

-----------------------------------------------------------------------

Summary of changes:
 src/target/aarch64.c | 9 +++++++--
 src/target/armv8.c   | 4 ++++
 src/target/armv8.h   | 1 +
 3 files changed, 12 insertions(+), 2 deletions(-)


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