[OpenOCD-devel] [PATCH]: dd7a883 flash/stm32l4x: add support of STM32WLEx devices

[<ge...@op...>]

This is an automated email from Gerrit.

Tarek BOCHKATI (tar...@gm...) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/5450

-- gerrit

commit dd7a8833b02413ef8cbac0c3a883053b8ae4aada
Author: Tarek BOCHKATI <tar...@gm...>
Date:   Tue Feb 11 09:13:26 2020 +0100

    flash/stm32l4x: add support of STM32WLEx devices
    
    STM32WLEx devices are based on arm Cortex-M4 running at 48MHz,
    contains a single bank of maximum 256 Kbytes of flash memory.
    
    there is 3 variants with different Flash/RAM sizes:
      STM32WLE5JC : 256K/64K
      STM32WLE5JB : 128K/48K
      STM32WLE5J8 :  64K/20K
    
    the work-area size is set to 20 kb to fit in STM32WLE5J8
    
    Change-Id: Ie8e186fe4be97cbc25c53ef0ade4b4dbbcee6f66
    Signed-off-by: Tarek BOCHKATI <tar...@gm...>

diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index c8055cd..09cebf5 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -182,6 +182,10 @@ static const struct stm32l4_rev stm32_495_revs[] = {
 	{ 0x2001, "2.1" },
 };
 
+static const struct stm32l4_rev stm32_497_revs[] = {
+	{ 0x1000, "1.0" },
+};
+
 static const struct stm32l4_part_info stm32l4_parts[] = {
 	{
 	  .id                    = 0x415,
@@ -263,6 +267,16 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
 	  .flash_regs_base       = 0x58004000,
 	  .fsize_addr            = 0x1FFF75E0,
 	},
+	{
+	  .id                    = 0x497,
+	  .revs                  = stm32_497_revs,
+	  .num_revs              = ARRAY_SIZE(stm32_497_revs),
+	  .device_str            = "STM32WLEx",
+	  .max_flash_size_kb     = 256,
+	  .has_dual_bank         = false,
+	  .flash_regs_base       = 0x58004000,
+	  .fsize_addr            = 0x1FFF75E0,
+	},
 };
 
 /* flash bank stm32l4x <base> <size> 0 0 <target#> */
@@ -804,6 +818,7 @@ static int stm32l4_probe(struct flash_bank *bank)
 	case 0x435:
 	case 0x462:
 	case 0x464:
+	case 0x497:
 		/* single bank flash */
 		page_size = 2048;
 		num_pages = flash_size_in_kb / 2;
diff --git a/tcl/target/stm32wlx.cfg b/tcl/target/stm32wlx.cfg
new file mode 100644
index 0000000..b7b49b6
--- /dev/null
+++ b/tcl/target/stm32wlx.cfg
@@ -0,0 +1,100 @@
+# script for stm32wlx family
+
+#
+# stm32wl devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32wbx
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 20kB
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x5000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	if { [using_jtag] } {
+		set _CPUTAPID 0x6ba00477
+	} else {
+		# SWD IDCODE (single drop, arm)
+		set _CPUTAPID 0x6ba02477
+	}
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+	jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
+
+# Common knowledges tells JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
+# the safe side.
+#
+# Note that there is a pretty wide band where things are
+# more or less stable, see http://openocd.zylin.com/#/c/3366/
+adapter speed 500
+
+adapter srst delay 100
+if {[using_jtag]} {
+	jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+	# if srst is not fitted use SYSRESETREQ to
+	# perform a soft reset
+	cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event reset-init {
+	# CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz.
+	# Configure system to use MSI 24 MHz clock, compliant with VOS default Range1.
+	# 2 WS compliant with VOS=Range1 and 24 MHz.
+	mmw 0x58004000 0x00000102 0  ;# FLASH_ACR |= PRFTEN | 2(Latency)
+	mmw 0x58000000 0x00000091 0  ;# RCC_CR = MSI_ON | MSI Range 24 MHz
+	# Boost JTAG frequency
+	adapter speed 4000
+}
+
+$_TARGETNAME configure -event reset-start {
+	# Reset clock is MSI (4 MHz)
+	adapter speed 500
+}
+
+$_TARGETNAME configure -event examine-end {
+	# Enable debug during low power modes (uses more power)
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0xE0042004 0x00000007 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0xE004203C 0x00001800 0
+}
+
+$_TARGETNAME configure -event trace-config {
+	# nothing to do
+}

--