[OpenOCD-devel] [PATCH]: 5b6e9c9 target/openrisc/x86_32_common: Use 'bool' data type

[<ge...@op...>]

This is an automated email from Gerrit.

Marc Schink (ope...@ma...) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/4972

-- gerrit

commit 5b6e9c9e3ac3e12b7dcaac7206dcca92b1fe37c2
Author: Marc Schink <ope...@ma...>
Date:   Tue Feb 26 14:11:46 2019 +0100

    target/openrisc/x86_32_common: Use 'bool' data type
    
    Change-Id: I395a36ddd7ac7e85bc54f6bb073a93b0c6f24db0
    Signed-off-by: Marc Schink <ope...@ma...>

diff --git a/src/target/x86_32_common.c b/src/target/x86_32_common.c
index ef4f806..011e7d8 100644
--- a/src/target/x86_32_common.c
+++ b/src/target/x86_32_common.c
@@ -939,14 +939,14 @@ static int set_debug_regs(struct target *t, uint32_t address,
 	 * when we exit PM
 	*/
 	buf_set_u32(x86_32->cache->reg_list[bp_num+DR0].value, 0, 32, address);
-	x86_32->cache->reg_list[bp_num+DR0].dirty = 1;
-	x86_32->cache->reg_list[bp_num+DR0].valid = 1;
+	x86_32->cache->reg_list[bp_num+DR0].dirty = true;
+	x86_32->cache->reg_list[bp_num+DR0].valid = true;
 	buf_set_u32(x86_32->cache->reg_list[DR6].value, 0, 32, PM_DR6);
-	x86_32->cache->reg_list[DR6].dirty = 1;
-	x86_32->cache->reg_list[DR6].valid = 1;
+	x86_32->cache->reg_list[DR6].dirty = true;
+	x86_32->cache->reg_list[DR6].valid = true;
 	buf_set_u32(x86_32->cache->reg_list[DR7].value, 0, 32, dr7);
-	x86_32->cache->reg_list[DR7].dirty = 1;
-	x86_32->cache->reg_list[DR7].valid = 1;
+	x86_32->cache->reg_list[DR7].dirty = true;
+	x86_32->cache->reg_list[DR7].valid = true;
 	return ERROR_OK;
 }
 
@@ -970,14 +970,14 @@ static int unset_debug_regs(struct target *t, uint8_t bp_num)
 	 * when we exit PM
 	*/
 	buf_set_u32(x86_32->cache->reg_list[bp_num+DR0].value, 0, 32, 0);
-	x86_32->cache->reg_list[bp_num+DR0].dirty = 1;
-	x86_32->cache->reg_list[bp_num+DR0].valid = 1;
+	x86_32->cache->reg_list[bp_num+DR0].dirty = true;
+	x86_32->cache->reg_list[bp_num+DR0].valid = true;
 	buf_set_u32(x86_32->cache->reg_list[DR6].value, 0, 32, PM_DR6);
-	x86_32->cache->reg_list[DR6].dirty = 1;
-	x86_32->cache->reg_list[DR6].valid = 1;
+	x86_32->cache->reg_list[DR6].dirty = true;
+	x86_32->cache->reg_list[DR6].valid = true;
 	buf_set_u32(x86_32->cache->reg_list[DR7].value, 0, 32, dr7);
-	x86_32->cache->reg_list[DR7].dirty = 1;
-	x86_32->cache->reg_list[DR7].valid = 1;
+	x86_32->cache->reg_list[DR7].dirty = true;
+	x86_32->cache->reg_list[DR7].valid = true;
 	return ERROR_OK;
 }
 

--