From: tosiara <to...@gm...> - 2018-11-09 11:53:52
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Just a follow up I found an OpenWRT page saying that "At the moment it is *NOT* possible to *UNBRICK* the router by *JTAG* (no write access to flashrom)"- https://openwrt.org/toh/tp-link/tl-wr1043nd So that may explain why I could not write anything into SPI flash through my jtag setup. However, it remained a mistery to me, why jtag may not have write access to the spi flash Ended up by un-soldering the spi chip physically and flashing it separately using a bus pirate device. Now the router is functional Thanks a lot for helping On Wed, Nov 7, 2018 at 5:00 PM tosiara <to...@gm...> wrote: > Sorry, typo, the first line should have been flashing CFE did NOT bring > the router up > > On Wed, Nov 7, 2018 at 4:59 PM tosiara <to...@gm...> wrote: > >> Well, flashing CFE did bring the router up. So I tried to flash just 256 >> bytes at offset 0x0 and immediately dumped few addresses, like 0x0, >> 0x9f000000, 0x9f3f0000, 0xbf000000. None of them changed. Curious where is >> it writing when I specify offset 0x0 (if it writes anything at all). >> >> Tried using upstream atheros_ar9331.cfg, but write command, as well as >> flash info, are not working: >> >> ./src/openocd -f tcl/interface/ftdi/um232h.cfg -f >> tcl/target/atheros_ar9331.cfg -c "adapter_khz 6000" >> Open On-Chip Debugger 0.10.0+dev-00571-g29c81a8 (2018-11-07-16:34) >> Licensed under GNU GPL v2 >> For bug reports, read >> http://openocd.org/doc/doxygen/bugs.html >> none srst_pulls_trst >> adapter_nsrst_assert_width: 100 >> adapter_nsrst_delay: 8 >> Info : auto-selecting first available session transport "jtag". To >> override use 'transport select <transport>'. >> ar9331_ddr2_init >> adapter speed: 6000 kHz >> Info : Listening on port 6666 for tcl connections >> Info : Listening on port 4444 for telnet connections >> Info : clock speed 6000 kHz >> Info : JTAG tap: ar9331.cpu tap/device found: 0x00000001 (mfg: 0x000 >> (<invalid>), part: 0x0000, ver: 0x0) >> MIPS32 with MIPS16 support implemented >> Error: The 'mww' command must be used after 'init'. >> in procedure 'init' >> in procedure 'ocd_bouncer' >> in procedure 'flash' >> in procedure 'ocd_bouncer' >> >> >> Open On-Chip Debugger >> > targets >> TargetName Type Endian TapName State >> -- ------------------ ---------- ------ ------------------ ------------ >> 0* ar9331.cpu mips_m4k big ar9331.cpu halted >> > reset >> JTAG tap: ar9331.cpu tap/device found: 0x00000001 (mfg: 0x000 >> (<invalid>), part: 0x0000, ver: 0x0) >> target not halted >> in procedure 'reset' >> in procedure 'ocd_bouncer' >> in procedure 'ocd_process_reset' >> in procedure 'ocd_process_reset_inner' called at file >> "embedded:startup.tcl", line 248 >> in procedure 'ar9331.cpu' called at file "embedded:startup.tcl", line 388 >> in procedure 'ocd_bouncer' >> >> > targets >> TargetName Type Endian TapName State >> -- ------------------ ---------- ------ ------------------ ------------ >> 0* ar9331.cpu mips_m4k big ar9331.cpu running >> > halt >> target halted in MIPS32 mode due to debug-request, pc: 0xbfc00380 >> > targets >> TargetName Type Endian TapName State >> -- ------------------ ---------- ------ ------------------ ------------ >> 0* ar9331.cpu mips_m4k big ar9331.cpu halted >> > flash 0 info >> invalid subcommand "0 info" >> in procedure 'flash' >> > dump_image test1.bin 0x00000000 0x00000100 >> dumped 256 bytes in 0.864613s (0.289 KiB/s) >> > flash write_image unlock ath79.flash 0x00 >> invalid subcommand "write_image unlock ath79.flash 0x00" >> in procedure 'flash' >> >> >> >> >> On Wed, Nov 7, 2018 at 1:50 PM tosiara <to...@gm...> wrote: >> >>> To confirm, my router board is using Atheros AR9132 chipset. Which of >>> the upstream configs are compatible with it? >>> >>> tcl/target/atheros_ar2313.cfg >>> tcl/target/atheros_ar2315.cfg >>> tcl/target/atheros_ar9331.cfg >>> tcl/target/atheros_ar9344.cfg >>> >>> On Wed, Nov 7, 2018 at 1:14 PM Paul Fertser <fer...@gm...> wrote: >>> >>>> On Wed, Nov 07, 2018 at 01:08:39PM +0200, tosiara wrote: >>>> > Is it just instability of JTAG device or the router? Is there a way >>>> to stabilize >>>> > it? >>>> >>>> Can it be the watchdog? >>>> >>>> You should be using target/atheros_ar9331.cfg from upstream OpenOCD, >>>> it handles the watchdog properly. An example of a proper board config >>>> would be board/tp-link_tl-mr3020.cfg but you do not need to init DDR >>>> RAM controller and working area if you're just after flashing. >>>> >>>> -- >>>> Be free, use free (http://www.gnu.org/philosophy/free-sw.html) >>>> software! >>>> mailto:fer...@gm... >>>> >>> |