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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-479-g07e0bd4
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From: Øyvind H. <go...@us...> - 2010-08-12 09:00:48
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 07e0bd46859439426084e2612d3fe1c3281564a9 (commit)
via 14a25cd6de1fa7d72bae466375cdef3081f7f339 (commit)
via 4ed89e4e42e1f2f62fdf6d0c660b2ea64479d136 (commit)
via 98d2579c61aea1cfc4c1e4bd391b9acf1b1ff5db (commit)
from a8c8c238f2dd1abe102f83bfa392ac40f313dd73 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 07e0bd46859439426084e2612d3fe1c3281564a9
Author: Thomas Koeller <tho...@ba...>
Date: Tue Aug 10 14:56:45 2010 +0200
jtag: fix handling of 'tap enable' error
if a tap could not be _enabled_, the error message was
'failed to disable tap'. Fixed that. Also, display the failing
tap's name.
Signed-off-by: Thomas Koeller <tho...@ba...>
diff --git a/src/jtag/tcl.c b/src/jtag/tcl.c
index 69045c6..4df3ccb 100644
--- a/src/jtag/tcl.c
+++ b/src/jtag/tcl.c
@@ -768,10 +768,10 @@ static int jim_jtag_tap_enabler(Jim_Interp *interp, int argc, Jim_Obj *const *ar
// do nothing, just return the value
} else if (strcasecmp(cmd_name, "tapenable") == 0) {
if (!jtag_tap_enable(t))
- LOG_WARNING("failed to disable tap");
+ LOG_WARNING("failed to enable tap %s", t->dotted_name);
} else if (strcasecmp(cmd_name, "tapdisable") == 0) {
if (!jtag_tap_disable(t))
- LOG_WARNING("failed to disable tap");
+ LOG_WARNING("failed to disable tap %s", t->dotted_name);
} else {
LOG_ERROR("command '%s' unknown", cmd_name);
return JIM_ERR;
commit 14a25cd6de1fa7d72bae466375cdef3081f7f339
Author: Thomas Koeller <tho...@ba...>
Date: Tue Aug 10 14:56:44 2010 +0200
DM36x: Set OSCDIV divider
The ability to set up the OSCDIV divider was missing.
Signed-off-by: Thomas Koeller <tho...@ba...>
diff --git a/tcl/target/davinci.cfg b/tcl/target/davinci.cfg
index 11ae093..6e9091e 100644
--- a/tcl/target/davinci.cfg
+++ b/tcl/target/davinci.cfg
@@ -222,6 +222,13 @@ proc pll_v03_setup {pll_addr mult config} {
} else {
mww [expr $pll_addr + 0x0120] 0
}
+ if { [dict exists $config oscdiv] } {
+ set div [dict get $config oscdiv]
+ set div [expr 0x8000 | ($div - 1)]
+ mww [expr $pll_addr + 0x0124] $div
+ } else {
+ mww [expr $pll_addr + 0x0124] 0
+ }
if { [dict exists $config div4] } {
set div [dict get $config div4]
set div [expr 0x8000 | ($div - 1)]
commit 4ed89e4e42e1f2f62fdf6d0c660b2ea64479d136
Author: Thomas Koeller <tho...@ba...>
Date: Tue Aug 10 14:56:43 2010 +0200
DM36x: Disable unused SYSCLKs
Clear the enable bits for all clocks that are not set explicitly.
This is done to increase robustness by removing pre-existing
state.
Signed-off-by: Thomas Koeller <tho...@ba...>
diff --git a/tcl/target/davinci.cfg b/tcl/target/davinci.cfg
index b736c6e..11ae093 100644
--- a/tcl/target/davinci.cfg
+++ b/tcl/target/davinci.cfg
@@ -197,63 +197,82 @@ proc pll_v03_setup {pll_addr mult config} {
# 11 - optional: set plldiv1, plldiv2, ...
# NOTE: this assumes some registers have their just-reset values:
# - PLLSTAT.GOSTAT is clear when we enter
- # - ALNCTL has everything set
set aln 0
if { [dict exists $config div1] } {
set div [dict get $config div1]
set div [expr 0x8000 | ($div - 1)]
mww [expr $pll_addr + 0x0118] $div
set aln [expr $aln | 0x1]
+ } else {
+ mww [expr $pll_addr + 0x0118] 0
}
if { [dict exists $config div2] } {
set div [dict get $config div2]
set div [expr 0x8000 | ($div - 1)]
mww [expr $pll_addr + 0x011c] $div
set aln [expr $aln | 0x2]
+ } else {
+ mww [expr $pll_addr + 0x011c] 0
}
if { [dict exists $config div3] } {
set div [dict get $config div3]
set div [expr 0x8000 | ($div - 1)]
mww [expr $pll_addr + 0x0120] $div
set aln [expr $aln | 0x4]
+ } else {
+ mww [expr $pll_addr + 0x0120] 0
}
if { [dict exists $config div4] } {
set div [dict get $config div4]
set div [expr 0x8000 | ($div - 1)]
mww [expr $pll_addr + 0x0160] $div
set aln [expr $aln | 0x8]
+ } else {
+ mww [expr $pll_addr + 0x0160] 0
}
if { [dict exists $config div5] } {
set div [dict get $config div5]
set div [expr 0x8000 | ($div - 1)]
mww [expr $pll_addr + 0x0164] $div
set aln [expr $aln | 0x10]
+ } else {
+ mww [expr $pll_addr + 0x0164] 0
}
if { [dict exists $config div6] } {
set div [dict get $config div6]
set div [expr 0x8000 | ($div - 1)]
mww [expr $pll_addr + 0x0168] $div
set aln [expr $aln | 0x20]
+ } else {
+ mww [expr $pll_addr + 0x0168] 0
}
if { [dict exists $config div7] } {
set div [dict get $config div7]
set div [expr 0x8000 | ($div - 1)]
mww [expr $pll_addr + 0x016c] $div
set aln [expr $aln | 0x40]
+ } else {
+ mww [expr $pll_addr + 0x016c] 0
}
if { [dict exists $config div8] } {
set div [dict get $config div8]
set div [expr 0x8000 | ($div - 1)]
mww [expr $pll_addr + 0x0170] $div
set aln [expr $aln | 0x80]
+ } else {
+ mww [expr $pll_addr + 0x0170] 0
}
if { [dict exists $config div9] } {
set div [dict get $config div9]
set div [expr 0x8000 | ($div - 1)]
mww [expr $pll_addr + 0x0174] $div
set aln [expr $aln | 0x100]
+ } else {
+ mww [expr $pll_addr + 0x0174] 0
}
if {$aln != 0} {
+ # clear pllcmd.GO
+ mww [expr $pll_addr + 0x0138] 0x00
# write alingment flags
mww [expr $pll_addr + 0x0140] $aln
# write pllcmd.GO; poll pllstat.GO
commit 98d2579c61aea1cfc4c1e4bd391b9acf1b1ff5db
Author: Thomas Koeller <tho...@ba...>
Date: Tue Aug 10 14:56:42 2010 +0200
DM36x: Use enable bit for PLL pre-divider
The PLL pre- and postdividers seem to have enable bits, although
these are not mentioned in the chip documentation.
Signed-off-by: Thomas Koeller <tho...@ba...>
diff --git a/tcl/target/davinci.cfg b/tcl/target/davinci.cfg
index 6c6769f..b736c6e 100644
--- a/tcl/target/davinci.cfg
+++ b/tcl/target/davinci.cfg
@@ -179,7 +179,7 @@ proc pll_v03_setup {pll_addr mult config} {
mww [expr $pll_addr + 0x0110] [expr ($mult / 2) & 0x1ff]
if { [dict exists $config prediv] } {
set div [dict get $config prediv]
- set div [expr ($div - 1)]
+ set div [expr 0x8000 | ($div - 1)]
mww [expr $pll_addr + 0x0114] $div
}
if { [dict exists $config postdiv] } {
-----------------------------------------------------------------------
Summary of changes:
src/jtag/tcl.c | 4 ++--
tcl/target/davinci.cfg | 30 ++++++++++++++++++++++++++++--
2 files changed, 30 insertions(+), 4 deletions(-)
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Main OpenOCD repository
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