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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-443-ga9761c9
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From: Øyvind H. <go...@us...> - 2010-07-19 23:02:37
|
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- Log -----------------------------------------------------------------
commit a9761c90931101d280b9443126db017f96d92e3d
Author: Ãyvind Harboe <oyv...@zy...>
Date: Mon Jul 19 14:49:41 2010 +0200
arm_dpm: error propagation fixes
found by inspection
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index 4fbe5e3..012316b 100644
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -123,6 +123,8 @@ static int dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
cpsr = mode;
retval = dpm->instr_write_data_r0(dpm, ARMV4_5_MSR_GP(0, 0xf, 0), cpsr);
+ if (retval != ERROR_OK)
+ return retval;
if (dpm->instr_cpsr_sync)
retval = dpm->instr_cpsr_sync(dpm);
@@ -211,6 +213,8 @@ static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
retval = dpm->instr_write_data_r0(dpm,
ARMV4_5_MSR_GP(0, 0xf, regnum & 1),
value);
+ if (retval != ERROR_OK)
+ return retval;
if (regnum == 16 && dpm->instr_cpsr_sync)
retval = dpm->instr_cpsr_sync(dpm);
@@ -364,6 +368,8 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
retval = dpm_maybe_update_bpwp(dpm, bpwp, &dbp->bpwp,
bp ? &bp->set : NULL);
+ if (retval != ERROR_OK)
+ goto done;
}
}
@@ -374,6 +380,8 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
retval = dpm_maybe_update_bpwp(dpm, bpwp, &dwp->bpwp,
wp ? &wp->set : NULL);
+ if (retval != ERROR_OK)
+ goto done;
}
/* NOTE: writes to breakpoint and watchpoint registers might
@@ -433,7 +441,11 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
/* REVISIT error checks */
if (tmode != ARM_MODE_ANY)
+ {
retval = dpm_modeswitch(dpm, tmode);
+ if (retval != ERROR_OK)
+ goto done;
+ }
}
if (r->mode != mode)
continue;
@@ -441,7 +453,8 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
retval = dpm_write_reg(dpm,
&cache->reg_list[i],
regnum);
-
+ if (retval != ERROR_OK)
+ goto done;
}
} while (did_write);
@@ -451,13 +464,19 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
* defined, and must not write it before CPSR.
*/
retval = dpm_modeswitch(dpm, ARM_MODE_ANY);
+ if (retval != ERROR_OK)
+ goto done;
arm->cpsr->dirty = false;
retval = dpm_write_reg(dpm, arm->pc, 15);
+ if (retval != ERROR_OK)
+ goto done;
arm->pc->dirty = false;
/* flush R0 -- it's *very* dirty by now */
retval = dpm_write_reg(dpm, &cache->reg_list[0], 0);
+ if (retval != ERROR_OK)
+ goto done;
cache->reg_list[0].dirty = false;
/* (void) */ dpm->finish(dpm);
@@ -540,6 +559,8 @@ static int arm_dpm_read_core_reg(struct target *target, struct reg *r,
}
retval = dpm_read_reg(dpm, r, regnum);
+ if (retval != ERROR_OK)
+ goto fail;
/* always clean up, regardless of error */
if (mode != ARM_MODE_ANY)
@@ -636,6 +657,8 @@ static int arm_dpm_full_context(struct target *target)
/* REVISIT error checks */
retval = dpm_modeswitch(dpm, mode);
+ if (retval != ERROR_OK)
+ goto done;
}
if (r->mode != mode)
continue;
@@ -644,7 +667,8 @@ static int arm_dpm_full_context(struct target *target)
retval = dpm_read_reg(dpm,
&cache->reg_list[i],
(r->num == 16) ? 17 : r->num);
-
+ if (retval != ERROR_OK)
+ goto done;
}
} while (did_read);
commit 441ea95f693316052f04486b927abb2b152ca547
Author: Ãyvind Harboe <oyv...@zy...>
Date: Mon Jul 19 14:42:54 2010 +0200
adi_jtag_ error propagation
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/target/adi_v5_jtag.c b/src/target/adi_v5_jtag.c
index 185bd54..8731a1a 100644
--- a/src/target/adi_v5_jtag.c
+++ b/src/target/adi_v5_jtag.c
@@ -211,8 +211,10 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
/* Post CTRL/STAT read; discard any previous posted read value
* but collect its ACK status.
*/
- adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
+ retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
+ if (retval != ERROR_OK)
+ return retval;
if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
@@ -246,8 +248,10 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
return ERROR_JTAG_DEVICE_ERROR;
}
- adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
+ retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
+ if (retval != ERROR_OK)
+ return retval;
if ((retval = dap_run(dap)) != ERROR_OK)
return retval;
dap->ack = dap->ack & 0x7;
@@ -292,12 +296,16 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
LOG_ERROR("JTAG-DP STICKY ERROR");
/* Clear Sticky Error Bits */
- adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
+ retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
DP_CTRL_STAT, DPAP_WRITE,
dap->dp_ctrl_stat | SSTICKYORUN
| SSTICKYERR, NULL);
- adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
+ if (retval != ERROR_OK)
+ return retval;
+ retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
+ if (retval != ERROR_OK)
+ return retval;
if ((retval = dap_run(dap)) != ERROR_OK)
return retval;
commit 4333840ee3d6d79299bf90b719a3c1628c688690
Author: Ãyvind Harboe <oyv...@zy...>
Date: Mon Jul 19 14:37:45 2010 +0200
arm: error propagation of arm_jtag_set_instr
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/target/adi_v5_jtag.c b/src/target/adi_v5_jtag.c
index 0a374be..185bd54 100644
--- a/src/target/adi_v5_jtag.c
+++ b/src/target/adi_v5_jtag.c
@@ -86,8 +86,11 @@ int adi_jtag_dp_scan(struct adiv5_dap *dap,
struct arm_jtag *jtag_info = dap->jtag_info;
struct scan_field fields[2];
uint8_t out_addr_buf;
+ int retval;
- arm_jtag_set_instr(jtag_info, instr, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info, instr, NULL, TAP_IDLE);
+ if (retval != ERROR_OK)
+ return retval;
/* Scan out a read or write operation using some DP or AP register.
* For APACC access with any sticky error flag set, this is discarded.
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index b742dae..abfb21b 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -690,9 +690,13 @@ int arm7_9_execute_sys_speed(struct target *target)
/* set RESTART instruction */
if (arm7_9->need_bypass_before_restart) {
arm7_9->need_bypass_before_restart = 0;
- arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
+ if (retval != ERROR_OK)
+ return retval;
}
- arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE);
+ if (retval != ERROR_OK)
+ return retval;
long long then = timeval_ms();
int timeout;
@@ -738,13 +742,18 @@ static int arm7_9_execute_fast_sys_speed(struct target *target)
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+ int retval;
/* set RESTART instruction */
if (arm7_9->need_bypass_before_restart) {
arm7_9->need_bypass_before_restart = 0;
- arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
+ if (retval != ERROR_OK)
+ return retval;
}
- arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE);
+ if (retval != ERROR_OK)
+ return retval;
if (!set)
{
@@ -1744,13 +1753,19 @@ static int arm7_9_restart_core(struct target *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
+ int retval;
/* set RESTART instruction */
if (arm7_9->need_bypass_before_restart) {
arm7_9->need_bypass_before_restart = 0;
- arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
+
+ retval = arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
+ if (retval != ERROR_OK)
+ return retval;
}
- arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE);
+ if (retval != ERROR_OK)
+ return retval;
jtag_add_runtest(1, TAP_IDLE);
return jtag_execute_queue();
diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c
index 541adc8..8befe2b 100644
--- a/src/target/arm7tdmi.c
+++ b/src/target/arm7tdmi.c
@@ -68,7 +68,9 @@ static int arm7tdmi_examine_debug_reason(struct target *target)
{
return retval;
}
- arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL, TAP_DRPAUSE);
+ retval = arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL, TAP_DRPAUSE);
+ if (retval != ERROR_OK)
+ return retval;
jtag_add_dr_scan(arm7_9->jtag_info.tap, 2, fields, TAP_DRPAUSE);
if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -117,8 +119,11 @@ static __inline int arm7tdmi_clock_out_inner(struct arm_jtag *jtag_info, uint32_
static __inline int arm7tdmi_clock_out(struct arm_jtag *jtag_info,
uint32_t out, uint32_t *deprecated, int breakpoint)
{
+ int retval;
arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE);
- arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+ retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+ if (retval != ERROR_OK)
+ return retval;
return arm7tdmi_clock_out_inner(jtag_info, out, breakpoint);
}
@@ -133,7 +138,9 @@ static int arm7tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in)
{
return retval;
}
- arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+ retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+ if (retval != ERROR_OK)
+ return retval;
fields[0].num_bits = 1;
fields[0].out_value = NULL;
@@ -217,7 +224,9 @@ static int arm7tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info,
{
return retval;
}
- arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+ retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+ if (retval != ERROR_OK)
+ return retval;
fields[0].num_bits = 1;
fields[0].out_value = NULL;
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 7627b25..c5064c1 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -89,11 +89,14 @@ static int arm920t_read_cp15_physical(struct target *target,
uint8_t access_type_buf = 1;
uint8_t reg_addr_buf = reg_addr & 0x3f;
uint8_t nr_w_buf = 0;
+ int retval;
jtag_info = &arm920t->arm7_9_common.jtag_info;
arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
- arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ if (retval != ERROR_OK)
+ return retval;
fields[0].num_bits = 1;
fields[0].out_value = &access_type_buf;
@@ -137,13 +140,16 @@ static int arm920t_write_cp15_physical(struct target *target,
uint8_t reg_addr_buf = reg_addr & 0x3f;
uint8_t nr_w_buf = 1;
uint8_t value_buf[4];
+ int retval;
jtag_info = &arm920t->arm7_9_common.jtag_info;
buf_set_u32(value_buf, 0, 32, value);
arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
- arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ if (retval != ERROR_OK)
+ return retval;
fields[0].num_bits = 1;
fields[0].out_value = &access_type_buf;
@@ -192,7 +198,9 @@ static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode,
jtag_info = &arm920t->arm7_9_common.jtag_info;
arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
- arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ if (retval != ERROR_OK)
+ return retval;
buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode);
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index aa38d27..3765f23 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -67,7 +67,9 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2
{
return retval;
}
- arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ if (retval != ERROR_OK)
+ return retval;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
@@ -120,7 +122,9 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2
LOG_DEBUG("addr: 0x%x value: %8.8x", address, *value);
#endif
- arm_jtag_set_instr(jtag_info, 0xc, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info, 0xc, NULL, TAP_IDLE);
+ if (retval != ERROR_OK)
+ return retval;
return ERROR_OK;
}
@@ -155,7 +159,9 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op
{
return retval;
}
- arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ if (retval != ERROR_OK)
+ return retval;
fields[0].num_bits = 32;
fields[0].out_value = value_buf;
@@ -205,7 +211,9 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op
LOG_DEBUG("addr: 0x%x value: %8.8x", address, value);
#endif
- arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
+ if (retval != ERROR_OK)
+ return retval;
return ERROR_OK;
}
diff --git a/src/target/arm966e.c b/src/target/arm966e.c
index b4207c8..170e3cc 100644
--- a/src/target/arm966e.c
+++ b/src/target/arm966e.c
@@ -88,7 +88,9 @@ static int arm966e_read_cp15(struct target *target, int reg_addr, uint32_t *valu
{
return retval;
}
- arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ if (retval != ERROR_OK)
+ return retval;
fields[0].num_bits = 32;
/* REVISIT: table 7-2 shows that bits 31-31 need to be
@@ -142,7 +144,9 @@ int arm966e_write_cp15(struct target *target, int reg_addr, uint32_t value)
{
return retval;
}
- arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ if (retval != ERROR_OK)
+ return retval;
fields[0].num_bits = 32;
fields[0].out_value = value_buf;
diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c
index 0749a56..fd50703 100644
--- a/src/target/arm9tdmi.c
+++ b/src/target/arm9tdmi.c
@@ -103,7 +103,9 @@ int arm9tdmi_examine_debug_reason(struct target *target)
{
return retval;
}
- arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL, TAP_DRPAUSE);
+ retval = arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL, TAP_DRPAUSE);
+ if (retval != ERROR_OK)
+ return retval;
jtag_add_dr_scan(arm7_9->jtag_info.tap, 3, fields, TAP_DRPAUSE);
if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -157,7 +159,9 @@ int arm9tdmi_clock_out(struct arm_jtag *jtag_info, uint32_t instr,
return retval;
}
- arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+ retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+ if (retval != ERROR_OK)
+ return retval;
fields[0].num_bits = 32;
fields[0].out_value = out_buf;
@@ -215,7 +219,9 @@ int arm9tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in)
return retval;
}
- arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+ retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+ if (retval != ERROR_OK)
+ return retval;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
@@ -281,7 +287,9 @@ int arm9tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info,
return retval;
}
- arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+ retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+ if (retval != ERROR_OK)
+ return retval;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index 7ef4ac4..965260c 100644
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -344,10 +344,13 @@ int embeddedice_read_reg_w_check(struct reg *reg,
struct scan_field fields[3];
uint8_t field1_out[1];
uint8_t field2_out[1];
+ int retval;
arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE);
- arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
+ if (retval != ERROR_OK)
+ return retval;
/* bits 31:0 -- data (ignored here) */
fields[0].num_bits = 32;
@@ -405,9 +408,12 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz
struct scan_field fields[3];
uint8_t field1_out[1];
uint8_t field2_out[1];
+ int retval;
arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
- arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ if (retval != ERROR_OK)
+ return retval;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
@@ -487,12 +493,13 @@ static int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf)
void embeddedice_write_reg(struct reg *reg, uint32_t value)
{
struct embeddedice_reg *ice_reg = reg->arch_info;
+ int retval;
LOG_DEBUG("%i: 0x%8.8" PRIx32 "", ice_reg->addr, value);
arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE);
- arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
uint8_t reg_addr = ice_reg->addr & 0x1f;
embeddedice_write_reg_inner(ice_reg->jtag_info->tap, reg_addr, value);
@@ -521,9 +528,12 @@ int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
uint8_t field0_out[4];
uint8_t field1_out[1];
uint8_t field2_out[1];
+ int retval;
arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
- arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ if (retval != ERROR_OK)
+ return retval;
fields[0].num_bits = 32;
fields[0].out_value = field0_out;
@@ -575,7 +585,9 @@ int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou
return ERROR_INVALID_ARGUMENTS;
arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
- arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ if (retval != ERROR_OK)
+ return retval;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
diff --git a/src/target/etm.c b/src/target/etm.c
index 61ee99a..5c42fb5 100644
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -496,6 +496,7 @@ static int etm_read_reg_w_check(struct reg *reg,
const struct etm_reg_info *r = etm_reg->reg_info;
uint8_t reg_addr = r->addr & 0x7f;
struct scan_field fields[3];
+ int retval;
if (etm_reg->reg_info->mode == WO) {
LOG_ERROR("BUG: can't read write-only register %s", r->name);
@@ -505,7 +506,9 @@ static int etm_read_reg_w_check(struct reg *reg,
LOG_DEBUG("%s (%u)", r->name, reg_addr);
arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
- arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
+ if (retval != ERROR_OK)
+ return retval;
fields[0].num_bits = 32;
fields[0].out_value = reg->value;
@@ -577,6 +580,7 @@ static int etm_write_reg(struct reg *reg, uint32_t value)
const struct etm_reg_info *r = etm_reg->reg_info;
uint8_t reg_addr = r->addr & 0x7f;
struct scan_field fields[3];
+ int retval;
if (etm_reg->reg_info->mode == RO) {
LOG_ERROR("BUG: can't write read--only register %s", r->name);
@@ -586,7 +590,9 @@ static int etm_write_reg(struct reg *reg, uint32_t value)
LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
- arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
+ if (retval != ERROR_OK)
+ return retval;
fields[0].num_bits = 32;
uint8_t tmp1[4];
diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index ea22ca0..6ca432a 100644
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -78,6 +78,7 @@ static int feroceon_dummy_clock_out(struct arm_jtag *jtag_info, uint32_t instr)
uint8_t out_buf[4];
uint8_t instr_buf[4];
uint8_t sysspeed_buf = 0x0;
+ int retval;
/* prepare buffer */
buf_set_u32(out_buf, 0, 32, 0);
@@ -86,7 +87,9 @@ static int feroceon_dummy_clock_out(struct arm_jtag *jtag_info, uint32_t instr)
arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE);
- arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+ retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+ if (retval != ERROR_OK)
+ return retval;
fields[0].num_bits = 32;
fields[0].out_value = out_buf;
commit 5164fe55639877be4dd6a7c0a504aa1bc279d64d
Author: Ãyvind Harboe <oyv...@zy...>
Date: Mon Jul 19 14:22:35 2010 +0200
arm_adi_v5: dap_run() error propagation
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 39d8bde..b26175b 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -321,7 +321,7 @@ int mem_ap_write_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, int count, uint
break;
}
- if (dap_run(dap) == ERROR_OK)
+ if ((retval = dap_run(dap)) == ERROR_OK)
{
wcount = wcount - blocksize;
address = address + 4 * blocksize;
@@ -335,8 +335,7 @@ int mem_ap_write_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, int count, uint
if (errorcount > 1)
{
LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
- /* REVISIT return the *actual* fault code */
- return ERROR_JTAG_DEVICE_ERROR;
+ return retval;
}
}
@@ -406,13 +405,12 @@ static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap,
if (retval != ERROR_OK)
break;
- if (dap_run(dap) != ERROR_OK)
+ if ((retval = dap_run(dap)) != ERROR_OK)
{
LOG_WARNING("Block write error address "
"0x%" PRIx32 ", count 0x%x",
address, count);
- /* REVISIT return *actual* fault code */
- return ERROR_JTAG_DEVICE_ERROR;
+ return retval;
}
}
@@ -515,13 +513,12 @@ static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap,
if (retval != ERROR_OK)
break;
- if (dap_run(dap) != ERROR_OK)
+ if ((retval = dap_run(dap)) != ERROR_OK)
{
LOG_WARNING("Block write error address "
"0x%" PRIx32 ", count 0x%x",
address, count);
- /* REVISIT return *actual* fault code */
- return ERROR_JTAG_DEVICE_ERROR;
+ return retval;
}
}
@@ -712,11 +709,12 @@ static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap,
do
{
retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
- if (dap_run(dap) != ERROR_OK)
+ if (retval != ERROR_OK)
+ return retval;
+ if ((retval = dap_run(dap)) != ERROR_OK)
{
LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
- /* REVISIT return the *actual* fault code */
- return ERROR_JTAG_DEVICE_ERROR;
+ return retval;
}
nbytes = MIN((readcount << 1), 4);
@@ -821,11 +819,12 @@ static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap,
do
{
retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
- if (dap_run(dap) != ERROR_OK)
+ if (retval != ERROR_OK)
+ return retval;
+ if ((retval = dap_run(dap)) != ERROR_OK)
{
LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
- /* REVISIT return the *actual* fault code */
- return ERROR_JTAG_DEVICE_ERROR;
+ return retval;
}
nbytes = MIN(readcount, 4);
@@ -993,7 +992,11 @@ int ahbap_debugport_init(struct adiv5_dap *dap)
* place to scan the table and do any topology detection?
*/
retval = dap_queue_ap_read(dap, AP_REG_IDR, &idreg);
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_queue_ap_read(dap, AP_REG_BASE, &romaddr);
+ if (retval != ERROR_OK)
+ return retval;
if ((retval = dap_run(dap)) != ERROR_OK)
return retval;
@@ -1039,7 +1042,11 @@ static int dap_info_command(struct command_context *cmd_ctx,
apselold = dap->apsel;
dap_ap_select(dap, apsel);
retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_run(dap);
if (retval != ERROR_OK)
return retval;
@@ -1490,6 +1497,8 @@ COMMAND_HANDLER(dap_baseaddr_command)
* use the ID register to verify it's a MEM-AP.
*/
retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_run(dap);
if (retval != ERROR_OK)
return retval;
@@ -1553,6 +1562,8 @@ COMMAND_HANDLER(dap_apsel_command)
dap_ap_select(dap, apsel);
retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_run(dap);
if (retval != ERROR_OK)
return retval;
@@ -1591,6 +1602,8 @@ COMMAND_HANDLER(dap_apid_command)
dap_ap_select(dap, apsel);
retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_run(dap);
if (retval != ERROR_OK)
return retval;
commit b62c8d600995638081f9a34c358db58337df7bdb
Author: Ãyvind Harboe <oyv...@zy...>
Date: Mon Jul 19 14:03:33 2010 +0200
arm_adi_v5: mem_ap_write error propagation
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 194865e..39d8bde 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -376,13 +376,14 @@ static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap,
if (nbytes < 4)
{
- if (mem_ap_write_buf_u16(dap, buffer,
- nbytes, address) != ERROR_OK)
+ retval = mem_ap_write_buf_u16(dap, buffer,
+ nbytes, address);
+ if (retval != ERROR_OK)
{
LOG_WARNING("Block write error address "
"0x%" PRIx32 ", count 0x%x",
address, count);
- return ERROR_JTAG_DEVICE_ERROR;
+ return retval;
}
address += nbytes >> 1;
@@ -485,12 +486,13 @@ static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap,
if (nbytes < 4)
{
- if (mem_ap_write_buf_u8(dap, buffer, nbytes, address) != ERROR_OK)
+ retval = mem_ap_write_buf_u8(dap, buffer, nbytes, address);
+ if (retval != ERROR_OK)
{
LOG_WARNING("Block write error address "
"0x%" PRIx32 ", count 0x%x",
address, count);
- return ERROR_JTAG_DEVICE_ERROR;
+ return retval;
}
address += nbytes;
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 7bdf7d5..2a58f5b 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -166,7 +166,9 @@ static int cortex_m3_clear_halt(struct target *target)
return retval;
/* Clear Debug Fault Status */
- mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
+ retval = mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
+ if (retval != ERROR_OK)
+ return retval;
LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr);
return ERROR_OK;
@@ -177,6 +179,7 @@ static int cortex_m3_single_step_core(struct target *target)
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
uint32_t dhcsr_save;
+ int retval;
/* backup dhcsr reg */
dhcsr_save = cortex_m3->dcb_dhcsr;
@@ -186,10 +189,16 @@ static int cortex_m3_single_step_core(struct target *target)
* HALT can put the core into an unknown state.
*/
if (!(cortex_m3->dcb_dhcsr & C_MASKINTS))
- mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
+ {
+ retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
- mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
+ if (retval != ERROR_OK)
+ return retval;
+ }
+ retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
+ if (retval != ERROR_OK)
+ return retval;
LOG_DEBUG(" ");
/* restore dhcsr reg */
@@ -217,14 +226,20 @@ static int cortex_m3_endreset_event(struct target *target)
LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr);
/* this register is used for emulated dcc channel */
- mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
+ retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
+ if (retval != ERROR_OK)
+ return retval;
/* Enable debug requests */
retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
if (retval != ERROR_OK)
return retval;
if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
- mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
+ {
+ retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
+ if (retval != ERROR_OK)
+ return retval;
+ }
/* clear any interrupt masking */
cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS);
@@ -236,31 +251,44 @@ static int cortex_m3_endreset_event(struct target *target)
* choices *EXCEPT* explicitly scripted overrides like "vector_catch"
* or manual updates to the NVIC SHCSR and CCR registers.
*/
- mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | armv7m->demcr);
+ retval = mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | armv7m->demcr);
+ if (retval != ERROR_OK)
+ return retval;
/* Paranoia: evidently some (early?) chips don't preserve all the
* debug state (including FBP, DWT, etc) across reset...
*/
/* Enable FPB */
- target_write_u32(target, FP_CTRL, 3);
+ retval = target_write_u32(target, FP_CTRL, 3);
+ if (retval != ERROR_OK)
+ return retval;
+
cortex_m3->fpb_enabled = 1;
/* Restore FPB registers */
for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
{
- target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
+ retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
+ if (retval != ERROR_OK)
+ return retval;
}
/* Restore DWT registers */
for (i = 0; i < cortex_m3->dwt_num_comp; i++)
{
- target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
+ retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
dwt_list[i].comp);
- target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
+ if (retval != ERROR_OK)
+ return retval;
+ retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
dwt_list[i].mask);
- target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
+ if (retval != ERROR_OK)
+ return retval;
+ retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
dwt_list[i].function);
+ if (retval != ERROR_OK)
+ return retval;
}
retval = dap_run(swjdp);
if (retval != ERROR_OK)
@@ -639,12 +667,16 @@ static int cortex_m3_soft_reset_halt(struct target *target)
int retval, timeout = 0;
/* Enter debug state on reset; restore DEMCR in endreset_event() */
- mem_ap_write_u32(swjdp, DCB_DEMCR,
+ retval = mem_ap_write_u32(swjdp, DCB_DEMCR,
TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
+ if (retval != ERROR_OK)
+ return retval;
/* Request a core-only reset */
- mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
+ retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
AIRCR_VECTKEY | AIRCR_VECTRESET);
+ if (retval != ERROR_OK)
+ return retval;
target->state = TARGET_RESET;
/* registers are now invalid */
@@ -902,16 +934,26 @@ static int cortex_m3_assert_reset(struct target *target)
if (retval != ERROR_OK)
return retval;
if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
- mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
+ {
+ retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
+ if (retval != ERROR_OK)
+ return retval;
+ }
- mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
+ retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
+ if (retval != ERROR_OK)
+ return retval;
if (!target->reset_halt)
{
/* Set/Clear C_MASKINTS in a separate operation */
if (cortex_m3->dcb_dhcsr & C_MASKINTS)
- mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
+ {
+ retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
DBGKEY | C_DEBUGEN | C_HALT);
+ if (retval != ERROR_OK)
+ return retval;
+ }
/* clear any debug flags before resuming */
cortex_m3_clear_halt(target);
@@ -927,8 +969,10 @@ static int cortex_m3_assert_reset(struct target *target)
* bad vector table entries. Should this include MMERR or
* other flags too?
*/
- mem_ap_write_atomic_u32(swjdp, DCB_DEMCR,
+ retval = mem_ap_write_atomic_u32(swjdp, DCB_DEMCR,
TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
+ if (retval != ERROR_OK)
+ return retval;
}
/*
@@ -992,8 +1036,10 @@ static int cortex_m3_assert_reset(struct target *target)
* core, like watchdog timers, if the SoC wires it up
* correctly. Else VECRESET can reset just the core.
*/
- mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
+ retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
+ if (retval != ERROR_OK)
+ return retval;
LOG_DEBUG("Using Cortex-M3 SYSRESETREQ");
{
@@ -1834,6 +1880,7 @@ static int cortex_m3_examine(struct target *target)
static int cortex_m3_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t *ctrl)
{
uint16_t dcrdr;
+ int retval;
mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
*ctrl = (uint8_t)dcrdr;
@@ -1846,7 +1893,9 @@ static int cortex_m3_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t *
if (dcrdr & (1 << 0))
{
dcrdr = 0;
- mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
+ retval = mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
+ if (retval != ERROR_OK)
+ return retval;
}
return ERROR_OK;
@@ -2041,7 +2090,9 @@ write:
demcr |= catch;
/* write, but don't assume it stuck (why not??) */
- mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
+ retval = mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
+ if (retval != ERROR_OK)
+ return retval;
retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
if (retval != ERROR_OK)
return retval;
commit a7315891eff5ed84dbd88e950321c6ff2a58e867
Author: Ãyvind Harboe <oyv...@zy...>
Date: Mon Jul 19 13:56:59 2010 +0200
arm_adi_v5: error propagation of mem_ap_read_atomic_u32 failure
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 496360f..194865e 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -1124,7 +1124,9 @@ static int dap_info_command(struct command_context *cmd_ctx,
entry_offset = 0;
do
{
- mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
+ retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
+ if (retval != ERROR_OK)
+ return retval;
command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
if (romentry&0x01)
{
@@ -1140,33 +1142,51 @@ static int dap_info_command(struct command_context *cmd_ctx,
/* IDs are in last 4K section */
- mem_ap_read_atomic_u32(dap,
+ retval = mem_ap_read_atomic_u32(dap,
component_base + 0xFE0, &c_pid0);
+ if (retval != ERROR_OK)
+ return retval;
c_pid0 &= 0xff;
- mem_ap_read_atomic_u32(dap,
+ retval = mem_ap_read_atomic_u32(dap,
component_base + 0xFE4, &c_pid1);
+ if (retval != ERROR_OK)
+ return retval;
c_pid1 &= 0xff;
- mem_ap_read_atomic_u32(dap,
+ retval = mem_ap_read_atomic_u32(dap,
component_base + 0xFE8, &c_pid2);
+ if (retval != ERROR_OK)
+ return retval;
c_pid2 &= 0xff;
- mem_ap_read_atomic_u32(dap,
+ retval = mem_ap_read_atomic_u32(dap,
component_base + 0xFEC, &c_pid3);
+ if (retval != ERROR_OK)
+ return retval;
c_pid3 &= 0xff;
- mem_ap_read_atomic_u32(dap,
+ retval = mem_ap_read_atomic_u32(dap,
component_base + 0xFD0, &c_pid4);
+ if (retval != ERROR_OK)
+ return retval;
c_pid4 &= 0xff;
- mem_ap_read_atomic_u32(dap,
+ retval = mem_ap_read_atomic_u32(dap,
component_base + 0xFF0, &c_cid0);
+ if (retval != ERROR_OK)
+ return retval;
c_cid0 &= 0xff;
- mem_ap_read_atomic_u32(dap,
+ retval = mem_ap_read_atomic_u32(dap,
component_base + 0xFF4, &c_cid1);
+ if (retval != ERROR_OK)
+ return retval;
c_cid1 &= 0xff;
- mem_ap_read_atomic_u32(dap,
+ retval = mem_ap_read_atomic_u32(dap,
component_base + 0xFF8, &c_cid2);
+ if (retval != ERROR_OK)
+ return retval;
c_cid2 &= 0xff;
- mem_ap_read_atomic_u32(dap,
+ retval = mem_ap_read_atomic_u32(dap,
component_base + 0xFFC, &c_cid3);
+ if (retval != ERROR_OK)
+ return retval;
c_cid3 &= 0xff;
@@ -1187,9 +1207,11 @@ static int dap_info_command(struct command_context *cmd_ctx,
unsigned minor;
char *major = "Reserved", *subtype = "Reserved";
- mem_ap_read_atomic_u32(dap,
+ retval = mem_ap_read_atomic_u32(dap,
(component_base & 0xfffff000) | 0xfcc,
&devtype);
+ if (retval != ERROR_OK)
+ return retval;
minor = (devtype >> 4) & 0x0f;
switch (devtype & 0x0f) {
case 0:
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 6939890..7bdf7d5 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -155,12 +155,15 @@ static int cortex_m3_clear_halt(struct target *target)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
+ int retval;
/* clear step if any */
cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
/* Read Debug Fault Status Register */
- mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
+ retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
+ if (retval != ERROR_OK)
+ return retval;
/* Clear Debug Fault Status */
mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
@@ -208,14 +211,18 @@ static int cortex_m3_endreset_event(struct target *target)
struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list;
/* REVISIT The four debug monitor bits are currently ignored... */
- mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
+ retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
+ if (retval != ERROR_OK)
+ return retval;
LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr);
/* this register is used for emulated dcc channel */
mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
/* Enable debug requests */
- mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ if (retval != ERROR_OK)
+ return retval;
if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
@@ -262,7 +269,7 @@ static int cortex_m3_endreset_event(struct target *target)
register_cache_invalidate(cortex_m3->armv7m.core_cache);
/* make sure we have latest dhcsr flags */
- mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
return retval;
}
@@ -396,7 +403,9 @@ static int cortex_m3_debug_entry(struct target *target)
LOG_DEBUG(" ");
cortex_m3_clear_halt(target);
- mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ if (retval != ERROR_OK)
+ return retval;
if ((retval = armv7m->examine_debug_reason(target)) != ERROR_OK)
return retval;
@@ -508,13 +517,17 @@ static int cortex_m3_poll(struct target *target)
target->debug_reason = DBG_REASON_DBGRQ;
/* refresh status bits */
- mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ if (retval != ERROR_OK)
+ return retval;
}
if (cortex_m3->dcb_dhcsr & S_RESET_ST)
{
/* check if still in reset */
- mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ if (retval != ERROR_OK)
+ return retval;
if (cortex_m3->dcb_dhcsr & S_RESET_ST)
{
@@ -642,8 +655,10 @@ static int cortex_m3_soft_reset_halt(struct target *target)
retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
if (retval == ERROR_OK)
{
- mem_ap_read_atomic_u32(swjdp, NVIC_DFSR,
+ retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR,
&cortex_m3->nvic_dfsr);
+ if (retval != ERROR_OK)
+ return retval;
if ((dcb_dhcsr & S_HALT)
&& (cortex_m3->nvic_dfsr & DFSR_VCATCH))
{
@@ -835,7 +850,10 @@ static int cortex_m3_step(struct target *target, int current,
cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
}
- mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ int retval;
+ retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ if (retval != ERROR_OK)
+ return retval;
/* registers are now invalid */
register_cache_invalidate(cortex_m3->armv7m.core_cache);
@@ -847,7 +865,6 @@ static int cortex_m3_step(struct target *target, int current,
" nvic_icsr = 0x%" PRIx32,
cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
- int retval;
retval = cortex_m3_debug_entry(target);
if (retval != ERROR_OK)
return retval;
@@ -880,7 +897,10 @@ static int cortex_m3_assert_reset(struct target *target)
assert_srst = 0;
/* Enable debug requests */
- mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ int retval;
+ retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ if (retval != ERROR_OK)
+ return retval;
if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
@@ -982,7 +1002,9 @@ static int cortex_m3_assert_reset(struct target *target)
* after reset) on LM3S6918 -- Michael Schwingen
*/
uint32_t tmp;
- mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
+ retval = mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
+ if (retval != ERROR_OK)
+ return retval;
}
}
@@ -993,7 +1015,6 @@ static int cortex_m3_assert_reset(struct target *target)
if (target->reset_halt)
{
- int retval;
if ((retval = target_halt(target)) != ERROR_OK)
return retval;
}
@@ -1982,7 +2003,9 @@ COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
if (retval != ERROR_OK)
return retval;
- mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
+ retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
+ if (retval != ERROR_OK)
+ return retval;
if (CMD_ARGC > 0) {
unsigned catch = 0;
@@ -2019,7 +2042,9 @@ write:
/* write, but don't assume it stuck (why not??) */
mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
- mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
+ retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
+ if (retval != ERROR_OK)
+ return retval;
/* FIXME be sure to clear DEMCR on clean server shutdown.
* Otherwise the vector catch hardware could fire when there's
commit 7dcde11b459f60d40db9ca53f038cd200c852064
Author: Ãyvind Harboe <oyv...@zy...>
Date: Mon Jul 19 13:50:28 2010 +0200
mem_ap_read_u32 error propagation
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 9a33d82..496360f 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -1088,11 +1088,21 @@ static int dap_info_command(struct command_context *cmd_ctx,
command_print(cmd_ctx, "\tROM table in legacy format");
/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
- mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
- mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
- mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
- mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
- mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
+ retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_run(dap);
if (retval != ERROR_OK)
return retval;
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index d6090f5..6939890 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -68,7 +68,9 @@ static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap *swjdp,
/* because the DCB_DCRDR is used for the emulated dcc channel
* we have to save/restore the DCB_DCRDR when used */
- mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
+ retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
+ if (retval != ERROR_OK)
+ return retval;
/* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
@@ -107,7 +109,9 @@ static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap *swjdp,
/* because the DCB_DCRDR is used for the emulated dcc channel
* we have to save/restore the DCB_DCRDR when used */
- mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
+ retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
+ if (retval != ERROR_OK)
+ return retval;
/* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
@@ -297,33 +301,51 @@ static int cortex_m3_examine_exception_reason(struct target *target)
struct adiv5_dap *swjdp = &armv7m->dap;
int retval;
- mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
+ retval = mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
+ if (retval != ERROR_OK)
+ return retval;
switch (armv7m->exception_number)
{
case 2: /* NMI */
break;
case 3: /* Hard Fault */
- mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
+ retval = mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
+ if (retval != ERROR_OK)
+ return retval;
if (except_sr & 0x40000000)
{
- mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
+ retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
+ if (retval != ERROR_OK)
+ return retval;
}
break;
case 4: /* Memory Management */
- mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
- mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
+ retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
+ if (retval != ERROR_OK)
+ return retval;
break;
case 5: /* Bus Fault */
- mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
- mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
+ retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
+ if (retval != ERROR_OK)
+ return retval;
break;
case 6: /* Usage Fault */
- mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
+ retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
+ if (retval != ERROR_OK)
+ return retval;
break;
case 11: /* SVCall */
break;
case 12: /* Debug Monitor */
- mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
+ retval = mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
+ if (retval != ERROR_OK)
+ return retval;
break;
case 14: /* PendSV */
break;
commit e7a1ec64bface364305e9c355811838e9f310bf3
Author: Ãyvind Harboe <oyv...@zy...>
Date: Mon Jul 19 13:45:53 2010 +0200
arm_adi_v5: add error propagation for dap_setup_accessport
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index dfb45b4..9a33d82 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -5,7 +5,7 @@
* Copyright (C) 2008 by Spencer Oliver *
* sp...@sp... *
* *
- * Copyright (C) 2009 by Oyvind Harboe *
+ * Copyright (C) 2009-2010 by Oyvind Harboe *
* oyv...@zy... *
* *
* Copyright (C) 2009-2010 by David Brownell *
@@ -309,7 +309,9 @@ int mem_ap_write_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, int count, uint
if (blocksize == 0)
blocksize = 1;
- dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
+ retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
+ if (retval != ERROR_OK)
+ return retval;
for (writecount = 0; writecount < blocksize; writecount++)
{
@@ -363,7 +365,9 @@ static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap,
if (blocksize == 0)
blocksize = 1;
- dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
+ retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
+ if (retval != ERROR_OK)
+ return retval;
writecount = blocksize;
do
@@ -430,7 +434,9 @@ int mem_ap_write_buf_u16(struct adiv5_dap *dap, uint8_t *buffer, int count, uint
while (count > 0)
{
- dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
+ retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
+ if (retval != ERROR_OK)
+ return retval;
uint16_t svalue;
memcpy(&svalue, buffer, sizeof(uint16_t));
uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
@@ -468,7 +474,9 @@ static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap,
if (wcount < blocksize)
blocksize = wcount;
- dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
+ retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
+ if (retval != ERROR_OK)
+ return retval;
writecount = blocksize;
do
@@ -534,7 +542,9 @@ int mem_ap_write_buf_u8(struct adiv5_dap *dap, uint8_t *buffer, int count, uint3
while (count > 0)
{
- dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
+ retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
+ if (retval != ERROR_OK)
+ return retval;
uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
if (retval != ERROR_OK)
@@ -592,8 +602,10 @@ int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer,
if (blocksize == 0)
blocksize = 1;
- dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE,
+ retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE,
address);
+ if (retval != ERROR_OK)
+ return retval;
/* FIXME remove these three calls to adi_jtag_dp_scan(),
* so this routine becomes transport-neutral. Be careful
@@ -686,7 +698,9 @@ static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap,
if (wcount < blocksize)
blocksize = wcount;
- dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
+ retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
+ if (retval != ERROR_OK)
+ return retval;
/* handle unaligned data at 4k boundary */
if (blocksize == 0)
@@ -739,7 +753,9 @@ int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer,
while (count > 0)
{
- dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
+ retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
if (retval != ERROR_OK)
break;
@@ -795,7 +811,9 @@ static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap,
if (wcount < blocksize)
blocksize = wcount;
- dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
+ retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
+ if (retval != ERROR_OK)
+ return retval;
readcount = blocksize;
do
@@ -844,8 +862,12 @@ int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer,
while (count > 0)
{
- dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
+ retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_run(dap);
if (retval != ERROR_OK)
break;
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 4f3560f..d6090f5 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -71,13 +71,17 @@ static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap *swjdp,
mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
/* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
- dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
+ retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
if (retval != ERROR_OK)
return retval;
/* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
- dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
+ retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_queue_ap_read(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
if (retval != ERROR_OK)
return retval;
@@ -106,12 +110,16 @@ static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap *swjdp,
mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
/* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
- dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
+ retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
// XXX check retval
/* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
- dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
+ retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
// XXX check retval
commit 44ef0327dd97c1893afc63cd7fd8025cb1b57827
Author: Ãyvind Harboe <oyv...@zy...>
Date: Mon Jul 19 12:34:54 2010 +0200
debug: debug entry error propagation
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/target/arm11.c b/src/target/arm11.c
index 36bbaba..67f0524 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -439,7 +439,7 @@ static int arm11_halt(struct target *target)
enum target_state old_state = target->state;
- arm11_debug_entry(arm11);
+ CHECK_RETVAL(arm11_debug_entry(arm11));
CHECK_RETVAL(
target_call_event_callbacks(target,
diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index 6bf38bb..96e0baa 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -202,13 +202,18 @@ static int arm720t_enable_mmu_caches(struct target *target,
return retval;
}
-static void arm720t_post_debug_entry(struct target *target)
+static int arm720t_post_debug_entry(struct target *target)
{
struct arm720t_common *arm720t = target_to_arm720(target);
+ int retval;
/* examine cp15 control reg */
- arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
- jtag_execute_queue();
+ retval = arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = jtag_execute_queue();
+ if (retval != ERROR_OK)
+ return retval;
LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
@@ -216,9 +221,14 @@ static void arm720t_post_debug_entry(struct target *target)
arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
/* save i/d fault status and address register */
- arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
- arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
- jtag_execute_queue();
+ retval = arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = jtag_execute_queue();
+ return retval;
}
static void arm720t_pre_restore_context(struct target *target)
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index abe0c2f..b742dae 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -1470,7 +1470,11 @@ static int arm7_9_debug_entry(struct target *target)
return retval;
if (arm7_9->post_debug_entry)
- arm7_9->post_debug_entry(target);
+ {
+ retval = arm7_9->post_debug_entry(target);
+ if (retval != ERROR_OK)
+ return retval;
+ }
return ERROR_OK;
}
@@ -1878,7 +1882,9 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand
return err;
}
- arm7_9_debug_entry(target);
+ retval = arm7_9_debug_entry(target);
+ if (retval != ERROR_OK)
+ return retval;
LOG_DEBUG("new PC after step: 0x%8.8" PRIx32,
buf_get_u32(armv4_5->pc->value, 0, 32));
@@ -2079,7 +2085,9 @@ int arm7_9_step(struct target *target, int current, uint32_t address, int handle
{
target->state = TARGET_UNKNOWN;
} else {
- arm7_9_debug_entry(target);
+ retval = arm7_9_debug_entry(target);
+ if (retval != ERROR_OK)
+ retur...
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