Menu
▾
▴
[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-425-g20c1d4c
|
From: Øyvind H. <go...@us...> - 2010-07-19 08:37:16
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 20c1d4cc9a2ce8864b59ef6414f9cf5649b9f046 (commit)
via 221ce7c89b2c8792be4099687ed23f04f4e5018d (commit)
via 8249261b88644c4b6809bf01c2285f27c97ff434 (commit)
via a2d5b0ef77944f2bca5aaf8615e61bdc70ff8c6a (commit)
via ad02493cf2e4e201636d963503a1a2f5c7b0820e (commit)
via 19fc52f00869a4c607483d96c459a51f3979c8db (commit)
from d10f0def80f8837398b9176388ed6110fcebfd2d (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 20c1d4cc9a2ce8864b59ef6414f9cf5649b9f046
Author: Ãyvind Harboe <oyv...@zy...>
Date: Sun Jul 18 23:30:31 2010 +0200
cortex a8: lots of error propagation fixes
found by code inspection
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index a2f3ea0..bd14016 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -468,6 +468,8 @@ static int cortex_a8_instr_write_data_dcc(struct arm_dpm *dpm,
uint32_t dscr = DSCR_INSTR_COMP;
retval = cortex_a8_write_dcc(a8, data);
+ if (retval != ERROR_OK)
+ return retval;
return cortex_a8_exec_opcode(
a8->armv7a_common.armv4_5_common.target,
@@ -483,6 +485,8 @@ static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm,
int retval;
retval = cortex_a8_write_dcc(a8, data);
+ if (retval != ERROR_OK)
+ return retval;
/* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
retval = cortex_a8_exec_opcode(
@@ -837,7 +841,9 @@ static int cortex_a8_resume(struct target *target, int current,
armv4_5->pc->dirty = 1;
armv4_5->pc->valid = 1;
- cortex_a8_restore_context(target, handle_breakpoints);
+ retval = cortex_a8_restore_context(target, handle_breakpoints);
+ if (retval != ERROR_OK)
+ return retval;
#if 0
/* the front-end may request us not to handle breakpoints */
@@ -965,10 +971,14 @@ static int cortex_a8_debug_entry(struct target *target)
else
{
dap_ap_select(swjdp, swjdp_memoryap);
- cortex_a8_read_regs_through_mem(target,
+ retval = cortex_a8_read_regs_through_mem(target,
regfile_working_area->address, regfile);
dap_ap_select(swjdp, swjdp_memoryap);
target_free_working_area(target, regfile_working_area);
+ if (retval != ERROR_OK)
+ {
+ return retval;
+ }
/* read Current PSR */
retval = cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
@@ -1156,9 +1166,7 @@ static int cortex_a8_restore_context(struct target *target, bool bpwp)
if (armv7a->pre_restore_context)
armv7a->pre_restore_context(target);
- arm_dpm_write_dirty_registers(&armv7a->dpm, bpwp);
-
- return ERROR_OK;
+ return arm_dpm_write_dirty_registers(&armv7a->dpm, bpwp);
}
@@ -1204,12 +1212,16 @@ static int cortex_a8_set_breakpoint(struct target *target,
brp_list[brp_i].used = 1;
brp_list[brp_i].value = (breakpoint->address & 0xFFFFFFFC);
brp_list[brp_i].control = control;
- cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
+ retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
brp_list[brp_i].value);
- cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
brp_list[brp_i].control);
+ if (retval != ERROR_OK)
+ return retval;
LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
brp_list[brp_i].control,
brp_list[brp_i].value);
@@ -1268,12 +1280,16 @@ static int cortex_a8_unset_breakpoint(struct target *target, struct breakpoint *
brp_list[brp_i].used = 0;
brp_list[brp_i].value = 0;
brp_list[brp_i].control = 0;
- cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
+ retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
brp_list[brp_i].control);
- cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
brp_list[brp_i].value);
+ if (retval != ERROR_OK)
+ return retval;
}
else
{
@@ -1456,7 +1472,10 @@ static int cortex_a8_read_memory(struct target *target, uint32_t address,
if(enabled)
{
virt = address;
- cortex_a8_virt2phys(target, virt, &phys);
+ retval = cortex_a8_virt2phys(target, virt, &phys);
+ if (retval != ERROR_OK)
+ return retval;
+
LOG_DEBUG("Reading at virtual address. Translating v:0x%x to r:0x%x", virt, phys);
address = phys;
}
@@ -1520,6 +1539,8 @@ static int cortex_a8_write_phys_memory(struct target *target,
retval = dpm->instr_write_data_r0(dpm,
ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
cacheline);
+ if (retval != ERROR_OK)
+ return retval;
}
}
@@ -1536,6 +1557,8 @@ static int cortex_a8_write_phys_memory(struct target *target,
retval = dpm->instr_write_data_r0(dpm,
ARMV4_5_MCR(15, 0, 0, 7, 6, 1),
cacheline);
+ if (retval != ERROR_OK)
+ return retval;
}
}
@@ -1561,7 +1584,9 @@ static int cortex_a8_write_memory(struct target *target, uint32_t address,
if(enabled)
{
virt = address;
- cortex_a8_virt2phys(target, virt, &phys);
+ retval = cortex_a8_virt2phys(target, virt, &phys);
+ if (retval != ERROR_OK)
+ return retval;
LOG_DEBUG("Writing to virtual address. Translating v:0x%x to r:0x%x", virt, phys);
address = phys;
}
@@ -1605,6 +1630,7 @@ static int cortex_a8_handle_target_request(void *priv)
struct target *target = priv;
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = &armv7a->dap;
+ int retval;
if (!target_was_examined(target))
return ERROR_OK;
@@ -1616,7 +1642,9 @@ static int cortex_a8_handle_target_request(void *priv)
uint8_t data = 0;
uint8_t ctrl = 0;
- cortex_a8_dcc_read(swjdp, &data, &ctrl);
+ retval = cortex_a8_dcc_read(swjdp, &data, &ctrl);
+ if (retval != ERROR_OK)
+ return retval;
/* check if we have data */
if (ctrl & (1 << 0))
@@ -1625,11 +1653,17 @@ static int cortex_a8_handle_target_request(void *priv)
/* we assume target is quick enough */
request = data;
- cortex_a8_dcc_read(swjdp, &data, &ctrl);
+ retval = cortex_a8_dcc_read(swjdp, &data, &ctrl);
+ if (retval != ERROR_OK)
+ return retval;
request |= (data << 8);
- cortex_a8_dcc_read(swjdp, &data, &ctrl);
+ retval = cortex_a8_dcc_read(swjdp, &data, &ctrl);
+ if (retval != ERROR_OK)
+ return retval;
request |= (data << 16);
- cortex_a8_dcc_read(swjdp, &data, &ctrl);
+ retval = cortex_a8_dcc_read(swjdp, &data, &ctrl);
+ if (retval != ERROR_OK)
+ return retval;
request |= (data << 24);
target_request(target, request);
}
@@ -1816,11 +1850,10 @@ static int cortex_a8_target_create(struct target *target, Jim_Interp *interp)
{
struct cortex_a8_common *cortex_a8 = calloc(1, sizeof(struct cortex_a8_common));
- cortex_a8_init_arch_info(target, cortex_a8, target->tap);
-
- return ERROR_OK;
+ return cortex_a8_init_arch_info(target, cortex_a8, target->tap);
}
+/* FIX! error propagation missing from this fn */
static uint32_t cortex_a8_get_ttb(struct target *target)
{
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
@@ -1874,6 +1907,7 @@ static uint32_t cortex_a8_get_ttb(struct target *target)
return ttb;
}
+/* FIX! error propagation missing from this fn */
static void cortex_a8_disable_mmu_caches(struct target *target, int mmu,
int d_u_cache, int i_cache)
{
@@ -1903,6 +1937,7 @@ static void cortex_a8_disable_mmu_caches(struct target *target, int mmu,
cp15_control);
}
+/* FIX! error propagation missing from this fn */
static void cortex_a8_enable_mmu_caches(struct target *target, int mmu,
int d_u_cache, int i_cache)
{
commit 221ce7c89b2c8792be4099687ed23f04f4e5018d
Author: Ãyvind Harboe <oyv...@zy...>
Date: Sun Jul 18 23:12:25 2010 +0200
cortex a8: mem_ap_read_buf_u32() error handling
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 0f5c742..a2f3ea0 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -191,7 +191,9 @@ static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t addre
return retval;
dap_ap_select(swjdp, swjdp_memoryap);
- mem_ap_read_buf_u32(swjdp, (uint8_t *)(®file[1]), 4*15, address);
+ retval = mem_ap_read_buf_u32(swjdp, (uint8_t *)(®file[1]), 4*15, address);
+ if (retval != ERROR_OK)
+ return retval;
dap_ap_select(swjdp, swjdp_debugap);
return retval;
commit 8249261b88644c4b6809bf01c2285f27c97ff434
Author: Ãyvind Harboe <oyv...@zy...>
Date: Sun Jul 18 23:10:50 2010 +0200
cortex a8: add missing error handling for cortex_a8_dap_write/read_coreregister_u32()
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index d092223..0f5c742 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -180,8 +180,12 @@ static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t addre
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = &armv7a->dap;
- cortex_a8_dap_read_coreregister_u32(target, regfile, 0);
- cortex_a8_dap_write_coreregister_u32(target, address, 0);
+ retval = cortex_a8_dap_read_coreregister_u32(target, regfile, 0);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cortex_a8_dap_write_coreregister_u32(target, address, 0);
+ if (retval != ERROR_OK)
+ return retval;
retval = cortex_a8_exec_opcode(target, ARMV4_5_STMIA(0, 0xFFFE, 0, 0), NULL);
if (retval != ERROR_OK)
return retval;
@@ -965,7 +969,9 @@ static int cortex_a8_debug_entry(struct target *target)
target_free_working_area(target, regfile_working_area);
/* read Current PSR */
- cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
+ retval = cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
+ if (retval != ERROR_OK)
+ return retval;
dap_ap_select(swjdp, swjdp_debugap);
LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
commit a2d5b0ef77944f2bca5aaf8615e61bdc70ff8c6a
Author: Ãyvind Harboe <oyv...@zy...>
Date: Sun Jul 18 23:08:26 2010 +0200
cortex a8: add missing error handling from cortex_a8_exec_opcode()
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 441c93b..d092223 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -182,7 +182,10 @@ static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t addre
cortex_a8_dap_read_coreregister_u32(target, regfile, 0);
cortex_a8_dap_write_coreregister_u32(target, address, 0);
- cortex_a8_exec_opcode(target, ARMV4_5_STMIA(0, 0xFFFE, 0, 0), NULL);
+ retval = cortex_a8_exec_opcode(target, ARMV4_5_STMIA(0, 0xFFFE, 0, 0), NULL);
+ if (retval != ERROR_OK)
+ return retval;
+
dap_ap_select(swjdp, swjdp_memoryap);
mem_ap_read_buf_u32(swjdp, (uint8_t *)(®file[1]), 4*15, address);
dap_ap_select(swjdp, swjdp_debugap);
@@ -205,27 +208,37 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target,
if (reg < 15)
{
/* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0" 0xEE00nE15 */
- cortex_a8_exec_opcode(target,
+ retval = cortex_a8_exec_opcode(target,
ARMV4_5_MCR(14, 0, reg, 0, 5, 0),
&dscr);
+ if (retval != ERROR_OK)
+ return retval;
}
else if (reg == 15)
{
/* "MOV r0, r15"; then move r0 to DCCTX */
- cortex_a8_exec_opcode(target, 0xE1A0000F, &dscr);
- cortex_a8_exec_opcode(target,
+ retval = cortex_a8_exec_opcode(target, 0xE1A0000F, &dscr);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cortex_a8_exec_opcode(target,
ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
&dscr);
+ if (retval != ERROR_OK)
+ return retval;
}
else
{
/* "MRS r0, CPSR" or "MRS r0, SPSR"
* then move r0 to DCCTX
*/
- cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, reg & 1), &dscr);
- cortex_a8_exec_opcode(target,
+ retval = cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, reg & 1), &dscr);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cortex_a8_exec_opcode(target,
ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
&dscr);
+ if (retval != ERROR_OK)
+ return retval;
}
/* Wait for DTRRXfull then read DTRRTX */
@@ -264,8 +277,10 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
{
LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
/* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */
- cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
+ retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
&dscr);
+ if (retval != ERROR_OK)
+ return retval;
}
if (Rd > 17)
@@ -281,33 +296,47 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
if (Rd < 15)
{
/* DCCRX to Rn, "MCR p14, 0, Rn, c0, c5, 0", 0xEE00nE15 */
- cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0),
+ retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0),
&dscr);
+ if (retval != ERROR_OK)
+ return retval;
}
else if (Rd == 15)
{
/* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
* then "mov r15, r0"
*/
- cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
+ retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
&dscr);
- cortex_a8_exec_opcode(target, 0xE1A0F000, &dscr);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cortex_a8_exec_opcode(target, 0xE1A0F000, &dscr);
+ if (retval != ERROR_OK)
+ return retval;
}
else
{
/* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
* then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
*/
- cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
+ retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
&dscr);
- cortex_a8_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, Rd & 1),
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cortex_a8_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, Rd & 1),
&dscr);
+ if (retval != ERROR_OK)
+ return retval;
/* "Prefetch flush" after modifying execution status in CPSR */
if (Rd == 16)
- cortex_a8_exec_opcode(target,
+ {
+ retval = cortex_a8_exec_opcode(target,
ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
&dscr);
+ if (retval != ERROR_OK)
+ return retval;
+ }
}
return retval;
@@ -412,6 +441,8 @@ static int cortex_a8_dpm_prepare(struct arm_dpm *dpm)
a8->armv7a_common.armv4_5_common.target,
ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
&dscr);
+ if (retval != ERROR_OK)
+ return retval;
}
return retval;
@@ -452,6 +483,8 @@ static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm,
a8->armv7a_common.armv4_5_common.target,
ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
&dscr);
+ if (retval != ERROR_OK)
+ return retval;
/* then the opcode, taking data from R0 */
retval = cortex_a8_exec_opcode(
@@ -485,6 +518,8 @@ static int cortex_a8_instr_read_data_dcc(struct arm_dpm *dpm,
a8->armv7a_common.armv4_5_common.target,
opcode,
&dscr);
+ if (retval != ERROR_OK)
+ return retval;
return cortex_a8_read_dcc(a8, data, &dscr);
}
@@ -502,12 +537,16 @@ static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm,
a8->armv7a_common.armv4_5_common.target,
opcode,
&dscr);
+ if (retval != ERROR_OK)
+ return retval;
/* write R0 to DCC */
retval = cortex_a8_exec_opcode(
a8->armv7a_common.armv4_5_common.target,
ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
&dscr);
+ if (retval != ERROR_OK)
+ return retval;
return cortex_a8_read_dcc(a8, data, &dscr);
}
commit ad02493cf2e4e201636d963503a1a2f5c7b0820e
Author: Ãyvind Harboe <oyv...@zy...>
Date: Sun Jul 18 23:03:05 2010 +0200
cortex a8: add missing error handling for mem_ap_atomic_write_u32()
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 82ce9a1..441c93b 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -147,7 +147,9 @@ static int cortex_a8_exec_opcode(struct target *target,
}
}
- mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_ITR, opcode);
+ retval = mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_ITR, opcode);
+ if (retval != ERROR_OK)
+ return retval;
do
{
@@ -273,6 +275,8 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
LOG_DEBUG("write DCC 0x%08" PRIx32, value);
retval = mem_ap_write_u32(swjdp,
armv7a->debug_base + CPUDBG_DTRRX, value);
+ if (retval != ERROR_OK)
+ return retval;
if (Rd < 15)
{
commit 19fc52f00869a4c607483d96c459a51f3979c8db
Author: Ãyvind Harboe <oyv...@zy...>
Date: Sun Jul 18 23:01:16 2010 +0200
cortex a8: add missing error handling for mem_ap_read_atomic_u32()
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 90e1a00..82ce9a1 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -11,6 +11,9 @@
* Copyright (C) 2009 by Dirk Behme *
* dir...@gm... - copy from cortex_m3 *
* *
+ * Copyright (C) 2010 Ãyvind Harboe *
+ * oyv...@zy... *
+ * *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
@@ -228,6 +231,8 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target,
{
retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
+ if (retval != ERROR_OK)
+ return retval;
}
retval = mem_ap_read_atomic_u32(swjdp,
@@ -251,6 +256,8 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
/* Check that DCCRX is not full */
retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
+ if (retval != ERROR_OK)
+ return retval;
if (dscr & DSCR_DTR_RX_FULL)
{
LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
@@ -352,10 +359,14 @@ static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data,
retval = mem_ap_read_atomic_u32(swjdp,
a8->armv7a_common.debug_base + CPUDBG_DSCR,
&dscr);
+ if (retval != ERROR_OK)
+ return retval;
}
retval = mem_ap_read_atomic_u32(swjdp,
a8->armv7a_common.debug_base + CPUDBG_DTRTX, data);
+ if (retval != ERROR_OK)
+ return retval;
//LOG_DEBUG("read DCC 0x%08" PRIx32, *data);
if (dscr_p)
-----------------------------------------------------------------------
Summary of changes:
src/target/cortex_a8.c | 169 +++++++++++++++++++++++++++++++++++++----------
1 files changed, 133 insertions(+), 36 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
