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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-320-g4d0d649
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From: Øyvind H. <go...@us...> - 2010-06-15 23:27:53
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- Log -----------------------------------------------------------------
commit 4d0d649ef9a066c8662e2ffcc597614fe917fefc
Author: Ãyvind Harboe <oyv...@zy...>
Date: Tue Jun 15 23:27:08 2010 +0200
mips_ejtag: -Wshadow warning fixes
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c
index 84ad529..33507b5 100644
--- a/src/target/mips_ejtag.c
+++ b/src/target/mips_ejtag.c
@@ -304,7 +304,7 @@ int mips_ejtag_init(struct mips_ejtag *ejtag_info)
return ERROR_OK;
}
-int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write, uint32_t *data)
+int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write_t, uint32_t *data)
{
struct jtag_tap *tap;
tap = ejtag_info->tap;
@@ -325,7 +325,7 @@ int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write, uint32_t
fields[1].num_bits = 32;
fields[1].out_value = t;
- if (write)
+ if (write_t)
{
fields[1].in_value = NULL;
buf_set_u32(t, 0, 32, *data);
commit 26a77f71e1d44d12af549c618a1b7010ff83ac2b
Author: Ãyvind Harboe <oyv...@zy...>
Date: Tue Jun 15 23:26:16 2010 +0200
mips32_pracc: -Wshadow warning fixes
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/target/mips32_pracc.c b/src/target/mips32_pracc.c
index d96867a..236f389 100644
--- a/src/target/mips32_pracc.c
+++ b/src/target/mips32_pracc.c
@@ -928,7 +928,7 @@ int mips32_pracc_read_regs(struct mips_ejtag *ejtag_info, uint32_t *regs)
* 3. data ...
*/
int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_area *source,
- int write, uint32_t addr, int count, uint32_t *buf)
+ int write_t, uint32_t addr, int count, uint32_t *buf)
{
uint32_t handler_code[] = {
/* caution when editing, table is modified below */
@@ -973,7 +973,7 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are
if (source->size < MIPS32_FASTDATA_HANDLER_SIZE)
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- if (write)
+ if (write_t)
{
handler_code[8] = MIPS32_LW(11,0,8); /* load data from probe at fastdata area */
handler_code[9] = MIPS32_SW(11,0,9); /* store data to RAM @ r9 */
@@ -1030,7 +1030,7 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are
for (i = 0; i < count; i++)
{
/* Send the data out using fastdata (clears the access pending bit) */
- if ((retval = mips_ejtag_fastdata_scan(ejtag_info, write, buf++)) != ERROR_OK)
+ if ((retval = mips_ejtag_fastdata_scan(ejtag_info, write_t, buf++)) != ERROR_OK)
return retval;
}
commit e85fe0a637d1be9c652ac1779218c1297aaaafec
Author: Ãyvind Harboe <oyv...@zy...>
Date: Tue Jun 15 23:25:32 2010 +0200
mips_m4k: -Wshadow warning fixes
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index 5604b6a..e258b71 100644
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -951,7 +951,7 @@ int mips_m4k_bulk_write_memory(struct target *target, uint32_t address,
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
struct working_area *source;
int retval;
- int write = 1;
+ int write_t = 1;
LOG_DEBUG("address: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, count);
@@ -984,7 +984,7 @@ int mips_m4k_bulk_write_memory(struct target *target, uint32_t address,
}
}
- retval = mips32_pracc_fastdata_xfer(ejtag_info, source, write, address,
+ retval = mips32_pracc_fastdata_xfer(ejtag_info, source, write_t, address,
count, (uint32_t*) buffer);
if (retval != ERROR_OK)
{
commit 43a9282203d5fc0cf9086a18590c8ff89184b320
Author: Ãyvind Harboe <oyv...@zy...>
Date: Tue Jun 15 23:24:47 2010 +0200
mips32: -Wshadow warning fixes
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/target/mips32.c b/src/target/mips32.c
index 0923a79..2547b01 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -388,7 +388,7 @@ int mips32_run_algorithm(struct target *target, int num_mem_params,
}
/* refresh core register cache */
- for (unsigned i = 0; i < MIPS32NUMCOREREGS; i++)
+ for (i = 0; i < MIPS32NUMCOREREGS; i++)
{
if (!mips32->core_cache->reg_list[i].valid)
mips32->read_core_reg(target, i);
@@ -404,7 +404,7 @@ int mips32_run_algorithm(struct target *target, int num_mem_params,
}
}
- for (int i = 0; i < num_reg_params; i++)
+ for (i = 0; i < num_reg_params; i++)
{
struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, 0);
commit 78b7a571e9f9c836189c06c095eb98a57761bc4f
Author: Ãyvind Harboe <oyv...@zy...>
Date: Tue Jun 15 23:23:16 2010 +0200
cortex_a8: -Wshadow warning fixes
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index c2d61a3..0b12abe 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -473,7 +473,7 @@ static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm,
return cortex_a8_read_dcc(a8, data, &dscr);
}
-static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index,
+static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
uint32_t addr, uint32_t control)
{
struct cortex_a8_common *a8 = dpm_to_a8(dpm);
@@ -481,7 +481,7 @@ static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index,
uint32_t cr = a8->armv7a_common.debug_base;
int retval;
- switch (index) {
+ switch (index_t) {
case 0 ... 15: /* breakpoints */
vr += CPUDBG_BVR_BASE;
cr += CPUDBG_BCR_BASE;
@@ -489,13 +489,13 @@ static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index,
case 16 ... 31: /* watchpoints */
vr += CPUDBG_WVR_BASE;
cr += CPUDBG_WCR_BASE;
- index -= 16;
+ index_t -= 16;
break;
default:
return ERROR_FAIL;
}
- vr += 4 * index;
- cr += 4 * index;
+ vr += 4 * index_t;
+ cr += 4 * index_t;
LOG_DEBUG("A8: bpwp enable, vr %08x cr %08x",
(unsigned) vr, (unsigned) cr);
@@ -509,23 +509,23 @@ static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index,
return retval;
}
-static int cortex_a8_bpwp_disable(struct arm_dpm *dpm, unsigned index)
+static int cortex_a8_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
{
struct cortex_a8_common *a8 = dpm_to_a8(dpm);
uint32_t cr;
- switch (index) {
+ switch (index_t) {
case 0 ... 15:
cr = a8->armv7a_common.debug_base + CPUDBG_BCR_BASE;
break;
case 16 ... 31:
cr = a8->armv7a_common.debug_base + CPUDBG_WCR_BASE;
- index -= 16;
+ index_t -= 16;
break;
default:
return ERROR_FAIL;
}
- cr += 4 * index;
+ cr += 4 * index_t;
LOG_DEBUG("A8: bpwp disable, cr %08x", (unsigned) cr);
commit 4bd415d01b70d3afb3aa5d4142dd0cc49a495fe0
Author: Ãyvind Harboe <oyv...@zy...>
Date: Tue Jun 15 23:22:24 2010 +0200
arm11_dbgtap: -Wshadow warning fixes
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c
index 18bf255..9ecd08f 100644
--- a/src/target/arm11_dbgtap.c
+++ b/src/target/arm11_dbgtap.c
@@ -898,7 +898,7 @@ int arm11_sc7_run(struct arm11_common * arm11, struct arm11_sc7_action * actions
}
/* Timeout here so we don't get stuck. */
- int i = 0;
+ int i_n = 0;
while (1)
{
JTAG_DEBUG("SC7 <= c%-3d Data %08x %s",
@@ -917,11 +917,11 @@ int arm11_sc7_run(struct arm11_common * arm11, struct arm11_sc7_action * actions
long long then = 0;
- if (i == 1000)
+ if (i_n == 1000)
{
then = timeval_ms();
}
- if (i >= 1000)
+ if (i_n >= 1000)
{
if ((timeval_ms()-then) > 1000)
{
@@ -930,7 +930,7 @@ int arm11_sc7_run(struct arm11_common * arm11, struct arm11_sc7_action * actions
}
}
- i++;
+ i_n++;
}
if (!nRW)
@@ -1086,7 +1086,7 @@ static int arm11_dpm_instr_read_data_r0(struct arm_dpm *dpm,
* and watchpoint operations instead of running them right away. Since we
* pre-allocated our vector, we don't need to worry about space.
*/
-static int arm11_bpwp_enable(struct arm_dpm *dpm, unsigned index,
+static int arm11_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
uint32_t addr, uint32_t control)
{
struct arm11_common *arm11 = dpm_to_arm11(dpm);
@@ -1104,15 +1104,15 @@ static int arm11_bpwp_enable(struct arm_dpm *dpm, unsigned index,
action[0].value = addr;
action[1].value = control;
- switch (index) {
+ switch (index_t) {
case 0 ... 15:
- action[0].address = ARM11_SC7_BVR0 + index;
- action[1].address = ARM11_SC7_BCR0 + index;
+ action[0].address = ARM11_SC7_BVR0 + index_t;
+ action[1].address = ARM11_SC7_BCR0 + index_t;
break;
case 16 ... 32:
- index -= 16;
- action[0].address = ARM11_SC7_WVR0 + index;
- action[1].address = ARM11_SC7_WCR0 + index;
+ index_t -= 16;
+ action[0].address = ARM11_SC7_WVR0 + index_t;
+ action[1].address = ARM11_SC7_WCR0 + index_t;
break;
default:
return ERROR_FAIL;
@@ -1123,7 +1123,7 @@ static int arm11_bpwp_enable(struct arm_dpm *dpm, unsigned index,
return ERROR_OK;
}
-static int arm11_bpwp_disable(struct arm_dpm *dpm, unsigned index)
+static int arm11_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
{
struct arm11_common *arm11 = dpm_to_arm11(dpm);
struct arm11_sc7_action *action;
@@ -1133,13 +1133,13 @@ static int arm11_bpwp_disable(struct arm_dpm *dpm, unsigned index)
action[0].write = true;
action[0].value = 0;
- switch (index) {
+ switch (index_t) {
case 0 ... 15:
- action[0].address = ARM11_SC7_BCR0 + index;
+ action[0].address = ARM11_SC7_BCR0 + index_t;
break;
case 16 ... 32:
- index -= 16;
- action[0].address = ARM11_SC7_WCR0 + index;
+ index_t -= 16;
+ action[0].address = ARM11_SC7_WCR0 + index_t;
break;
default:
return ERROR_FAIL;
commit 8cfd25d29e5ce786eb001461e6d1ab9355b18597
Author: Ãyvind Harboe <oyv...@zy...>
Date: Tue Jun 15 23:20:00 2010 +0200
arm926ejs: -Wshadow warning fix
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 918306d..d68e5ca 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -59,7 +59,7 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2
struct scan_field fields[4];
uint8_t address_buf[2] = {0, 0};
uint8_t nr_w_buf = 0;
- uint8_t access = 1;
+ uint8_t access_t = 1;
buf_set_u32(address_buf, 0, 14, address);
@@ -74,8 +74,8 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2
fields[0].in_value = (uint8_t *)value;
fields[1].num_bits = 1;
- fields[1].out_value = &access;
- fields[1].in_value = &access;
+ fields[1].out_value = &access_t;
+ fields[1].in_value = &access_t;
fields[2].num_bits = 14;
fields[2].out_value = address_buf;
@@ -92,7 +92,7 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2
for (;;)
{
/* rescan with NOP, to wait for the access to complete */
- access = 0;
+ access_t = 0;
nr_w_buf = 0;
jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE);
@@ -103,7 +103,7 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2
return retval;
}
- if (buf_get_u32(&access, 0, 1) == 1)
+ if (buf_get_u32(&access_t, 0, 1) == 1)
{
break;
}
@@ -146,7 +146,7 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op
uint8_t value_buf[4];
uint8_t address_buf[2] = {0, 0};
uint8_t nr_w_buf = 1;
- uint8_t access = 1;
+ uint8_t access_t = 1;
buf_set_u32(address_buf, 0, 14, address);
buf_set_u32(value_buf, 0, 32, value);
@@ -162,8 +162,8 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op
fields[0].in_value = NULL;
fields[1].num_bits = 1;
- fields[1].out_value = &access;
- fields[1].in_value = &access;
+ fields[1].out_value = &access_t;
+ fields[1].in_value = &access_t;
fields[2].num_bits = 14;
fields[2].out_value = address_buf;
@@ -180,7 +180,7 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op
for (;;)
{
/* rescan with NOP, to wait for the access to complete */
- access = 0;
+ access_t = 0;
nr_w_buf = 0;
jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE);
if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -188,7 +188,7 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op
return retval;
}
- if (buf_get_u32(&access, 0, 1) == 1)
+ if (buf_get_u32(&access_t, 0, 1) == 1)
{
break;
}
commit 97197c98ebd3c62061729fd5b4eb94eece262edb
Author: Ãyvind Harboe <oyv...@zy...>
Date: Tue Jun 15 23:18:44 2010 +0200
arm920t: -Wshadow warning fixes
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index b99b4d5..fe9bba7 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -1,3 +1,4 @@
+
/***************************************************************************
* Copyright (C) 2005 by Dominic Rath *
* Dom...@gm... *
@@ -841,7 +842,7 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
int i;
FILE *output;
struct arm920t_cache_line d_cache[8][64], i_cache[8][64];
- int segment, index;
+ int segment, index_t;
struct reg *r;
retval = arm920t_verify_pointer(CMD_CTX, arm920t);
@@ -910,12 +911,12 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
arm920t_write_cp15_physical(target,
CP15PHYS_TESTSTATE, cp15c15);
- for (index = 0; index < 64; index++)
+ for (index_t = 0; index_t < 64; index_t++)
{
/* Ra:
* r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0)
*/
- regs[0] = 0x0 | (segment << 5) | (index << 26);
+ regs[0] = 0x0 | (segment << 5) | (index_t << 26);
arm9tdmi_write_core_regs(target, 0x1, regs);
/* set interpret mode */
@@ -949,18 +950,18 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
return retval;
}
- d_cache[segment][index].cam = regs[9];
+ d_cache[segment][index_t].cam = regs[9];
/* mask LFSR[6] */
regs[9] &= 0xfffffffe;
fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8"
PRIx32 ", content (%s):\n",
- segment, index, regs[9],
+ segment, index_t, regs[9],
(regs[9] & 0x10) ? "valid" : "invalid");
for (i = 1; i < 9; i++)
{
- d_cache[segment][index].data[i] = regs[i];
+ d_cache[segment][index_t].data[i] = regs[i];
fprintf(output, "%i: 0x%8.8" PRIx32 "\n",
i-1, regs[i]);
}
@@ -1018,12 +1019,12 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
arm920t_write_cp15_physical(target,
CP15PHYS_TESTSTATE, cp15c15);
- for (index = 0; index < 64; index++)
+ for (index_t = 0; index_t < 64; index_t++)
{
/* Ra:
* r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0)
*/
- regs[0] = 0x0 | (segment << 5) | (index << 26);
+ regs[0] = 0x0 | (segment << 5) | (index_t << 26);
arm9tdmi_write_core_regs(target, 0x1, regs);
/* set interpret mode */
@@ -1057,18 +1058,18 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
return retval;
}
- i_cache[segment][index].cam = regs[9];
+ i_cache[segment][index_t].cam = regs[9];
/* mask LFSR[6] */
regs[9] &= 0xfffffffe;
fprintf(output, "\nsegment: %i, index: %i, "
"CAM: 0x%8.8" PRIx32 ", content (%s):\n",
- segment, index, regs[9],
+ segment, index_t, regs[9],
(regs[9] & 0x10) ? "valid" : "invalid");
for (i = 1; i < 9; i++)
{
- i_cache[segment][index].data[i] = regs[i];
+ i_cache[segment][index_t].data[i] = regs[i];
fprintf(output, "%i: 0x%8.8" PRIx32 "\n",
i-1, regs[i]);
}
commit da5979c38d7b373f6aa345ff8f961f5401e67902
Author: Ãyvind Harboe <oyv...@zy...>
Date: Tue Jun 15 23:17:00 2010 +0200
arm720t: -Wshadow warning fix
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index 8db0b5d..0ea6cb2 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -41,7 +41,7 @@
#endif
static int arm720t_scan_cp15(struct target *target,
- uint32_t out, uint32_t *in, int instruction, int clock)
+ uint32_t out, uint32_t *in, int instruction, int clock_arg)
{
int retval;
struct arm720t_common *arm720t = target_to_arm720(target);
@@ -81,7 +81,7 @@ static int arm720t_scan_cp15(struct target *target,
jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
}
- if (clock)
+ if (clock_arg)
jtag_add_runtest(0, TAP_DRPAUSE);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
@@ -93,9 +93,9 @@ static int arm720t_scan_cp15(struct target *target,
if (in)
LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
else
- LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
+ LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock_arg);
#else
- LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock);
+ LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock_arg);
#endif
return ERROR_OK;
commit ab6e62ab76226a4596f7f728d8915acb61507b44
Author: Ãyvind Harboe <oyv...@zy...>
Date: Tue Jun 15 23:15:50 2010 +0200
adi_v5_jtag: -Wshadow warning fixes
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/target/adi_v5_jtag.c b/src/target/adi_v5_jtag.c
index 04c6ae7..b368708 100644
--- a/src/target/adi_v5_jtag.c
+++ b/src/target/adi_v5_jtag.c
@@ -366,15 +366,15 @@ static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned reg,
/** Select the AP register bank matching bits 7:4 of reg. */
static int jtag_ap_q_bankselect(struct adiv5_dap *dap, unsigned reg)
{
- uint32_t select = reg & 0x000000F0;
+ uint32_t select_ap_bank = reg & 0x000000F0;
- if (select == dap->ap_bank_value)
+ if (select_ap_bank == dap->ap_bank_value)
return ERROR_OK;
- dap->ap_bank_value = select;
+ dap->ap_bank_value = select_ap_bank;
- select |= dap->apsel;
+ select_ap_bank |= dap->apsel;
- return jtag_dp_q_write(dap, DP_SELECT, select);
+ return jtag_dp_q_write(dap, DP_SELECT, select_ap_bank);
}
static int jtag_ap_q_read(struct adiv5_dap *dap, unsigned reg,
commit 66f42b6f74125a98fed6d9402f6dc83a0f829100
Author: Ãyvind Harboe <oyv...@zy...>
Date: Tue Jun 15 23:14:41 2010 +0200
arm_adi: -Wshadow warning fix
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 8f43f78..aae60fc 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -102,11 +102,11 @@ static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address
*/
void dap_ap_select(struct adiv5_dap *dap,uint8_t apsel)
{
- uint32_t select = (apsel << 24) & 0xFF000000;
+ uint32_t select_apsel = (apsel << 24) & 0xFF000000;
- if (select != dap->apsel)
+ if (select_apsel != dap->apsel)
{
- dap->apsel = select;
+ dap->apsel = select_apsel;
/* Switching AP invalidates cached values.
* Values MUST BE UPDATED BEFORE AP ACCESS.
*/
commit a09d6020e08ce1b81e8bf2647cd88ecab5c25887
Author: Ãyvind Harboe <oyv...@zy...>
Date: Tue Jun 15 23:14:20 2010 +0200
arm_simulator: -Wshadow warning fixes
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c
index 730f588..0f6fe3f 100644
--- a/src/target/arm_simulator.c
+++ b/src/target/arm_simulator.c
@@ -364,42 +364,42 @@ static int arm_simulate_step_core(struct target *target,
/* branch instructions */
if ((instruction.type >= ARM_B) && (instruction.type <= ARM_BLX))
{
- uint32_t target;
+ uint32_t target_address;
if (instruction.info.b_bl_bx_blx.reg_operand == -1)
{
- target = instruction.info.b_bl_bx_blx.target_address;
+ target_address = instruction.info.b_bl_bx_blx.target_address;
}
else
{
- target = sim->get_reg_mode(sim, instruction.info.b_bl_bx_blx.reg_operand);
+ target_address = sim->get_reg_mode(sim, instruction.info.b_bl_bx_blx.reg_operand);
if (instruction.info.b_bl_bx_blx.reg_operand == 15)
{
- target += 2 * instruction_size;
+ target_address += 2 * instruction_size;
}
}
if (dry_run_pc)
{
- *dry_run_pc = target & ~1;
+ *dry_run_pc = target_address & ~1;
return ERROR_OK;
}
else
{
if (instruction.type == ARM_B)
{
- sim->set_reg(sim, 15, target);
+ sim->set_reg(sim, 15, target_address);
}
else if (instruction.type == ARM_BL)
{
uint32_t old_pc = sim->get_reg(sim, 15);
int T = (sim->get_state(sim) == ARM_STATE_THUMB);
sim->set_reg_mode(sim, 14, old_pc + 4 + T);
- sim->set_reg(sim, 15, target);
+ sim->set_reg(sim, 15, target_address);
}
else if (instruction.type == ARM_BX)
{
- if (target & 0x1)
+ if (target_address & 0x1)
{
sim->set_state(sim, ARM_STATE_THUMB);
}
@@ -407,7 +407,7 @@ static int arm_simulate_step_core(struct target *target,
{
sim->set_state(sim, ARM_STATE_ARM);
}
- sim->set_reg(sim, 15, target & 0xfffffffe);
+ sim->set_reg(sim, 15, target_address & 0xfffffffe);
}
else if (instruction.type == ARM_BLX)
{
@@ -415,7 +415,7 @@ static int arm_simulate_step_core(struct target *target,
int T = (sim->get_state(sim) == ARM_STATE_THUMB);
sim->set_reg_mode(sim, 14, old_pc + 4 + T);
- if (target & 0x1)
+ if (target_address & 0x1)
{
sim->set_state(sim, ARM_STATE_THUMB);
}
@@ -423,7 +423,7 @@ static int arm_simulate_step_core(struct target *target,
{
sim->set_state(sim, ARM_STATE_ARM);
}
- sim->set_reg(sim, 15, target & 0xfffffffe);
+ sim->set_reg(sim, 15, target_address & 0xfffffffe);
}
return ERROR_OK;
commit 748863c2e23aca05a81007ca87129a30eac005c4
Author: Ãyvind Harboe <oyv...@zy...>
Date: Tue Jun 15 23:09:12 2010 +0200
arm_dpm: -Wshadow warning fix
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index 213afbd..4fbe5e3 100644
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -773,11 +773,11 @@ static int dpm_remove_breakpoint(struct target *target, struct breakpoint *bp)
return retval;
}
-static int dpm_watchpoint_setup(struct arm_dpm *dpm, unsigned index,
+static int dpm_watchpoint_setup(struct arm_dpm *dpm, unsigned index_t,
struct watchpoint *wp)
{
int retval;
- struct dpm_wp *dwp = dpm->dwp + index;
+ struct dpm_wp *dwp = dpm->dwp + index_t;
uint32_t control;
/* this hardware doesn't support data value matching or masking */
@@ -804,7 +804,7 @@ static int dpm_watchpoint_setup(struct arm_dpm *dpm, unsigned index,
}
dwp->bpwp.control = control;
- dpm->dwp[index].wp = wp;
+ dpm->dwp[index_t].wp = wp;
return retval;
}
-----------------------------------------------------------------------
Summary of changes:
src/target/adi_v5_jtag.c | 10 +++++-----
src/target/arm11_dbgtap.c | 32 ++++++++++++++++----------------
src/target/arm720t.c | 8 ++++----
src/target/arm920t.c | 23 ++++++++++++-----------
src/target/arm926ejs.c | 20 ++++++++++----------
src/target/arm_adi_v5.c | 6 +++---
src/target/arm_dpm.c | 6 +++---
src/target/arm_simulator.c | 22 +++++++++++-----------
src/target/cortex_a8.c | 18 +++++++++---------
src/target/mips32.c | 4 ++--
src/target/mips32_pracc.c | 6 +++---
src/target/mips_ejtag.c | 4 ++--
src/target/mips_m4k.c | 4 ++--
13 files changed, 82 insertions(+), 81 deletions(-)
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