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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-107-gd37ed90
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From: Spencer O. <nt...@us...> - 2010-03-18 12:17:16
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- Log -----------------------------------------------------------------
commit d37ed9094a62ec144b9d9fdc214d8c7723caadec
Author: Spencer Oliver <nt...@us...>
Date: Thu Mar 18 09:18:53 2010 +0000
DOCS: update flash bank examples
- include the $_FLASHNAME in all flash bank examples.
Signed-off-by: Spencer Oliver <nt...@us...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index da2782b..83a6369 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -4180,8 +4180,8 @@ To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
wide on a sixteen bit bus:
@example
-flash bank cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
-flash bank cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
+flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
+flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
@end example
To configure one bank of 32 MBytes
@@ -4189,7 +4189,7 @@ built from two sixteen bit (two byte) wide parts wired in parallel
to create a thirty-two bit (four byte) bus with doubled throughput:
@example
-flash bank cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
+flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
@end example
@c "cfi part_id" disabled
@@ -4205,7 +4205,7 @@ The setup command only requires the @var{target} argument
since all devices in this family have the same memory layout.
@example
-flash bank aduc702x 0 0 0 0 $_TARGETNAME
+flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
@end example
@end deffn
@@ -4226,9 +4226,9 @@ the following fixed locations:
@example
# Flash bank 0 - all chips
-flash bank at91sam3 0x00080000 0 1 1 $_TARGETNAME
+flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
# Flash bank 1 - only 256K chips
-flash bank at91sam3 0x00100000 0 1 1 $_TARGETNAME
+flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
@end example
Internally, the AT91SAM3 flash memory is organized as follows.
@@ -4280,7 +4280,7 @@ recognizes a number of these chips using the chip identification
register, and autoconfigures itself.
@example
-flash bank at91sam7 0 0 0 0 $_TARGETNAME
+flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
@end example
For chips which are not recognized by the controller driver, you must
@@ -4367,7 +4367,7 @@ with most tool chains @command{verify_image} will fail.
LPC flashes don't require the chip and bus width to be specified.
@example
-flash bank lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
+flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
lpc2000_v2 14765 calc_checksum
@end example
@@ -4385,7 +4385,7 @@ the programming clock rate in Hz.
LPC flashes don't require the chip and bus width to be specified.
@example
-flash bank lpc288x 0 0 0 0 $_TARGETNAME 12000000
+flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
@end example
@end deffn
@@ -4418,7 +4418,7 @@ and not by the standard @code{flash protect} command.
Example for a 125 MHz clock frequency:
@example
-flash bank lpc2900 0 0 0 0 $_TARGETNAME 125000
+flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME 125000
@end example
Some @code{lpc2900}-specific commands are defined. In the following command list,
@@ -4516,7 +4516,7 @@ lpc2900 secure_jtag 0
@emph{No idea what this is, other than using some arm7/arm9 core.}
@example
-flash bank ocl 0 0 0 0 $_TARGETNAME
+flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
@end example
@end deffn
@@ -4525,8 +4525,8 @@ The PIC32MX microcontrollers are based on the MIPS 4K cores,
and integrate flash memory.
@example
-flash bank pix32mx 0x1fc00000 0 0 0 $_TARGETNAME
-flash bank pix32mx 0x1d000000 0 0 0 $_TARGETNAME
+flash bank $_FLASHNAME pix32mx 0x1fc00000 0 0 0 $_TARGETNAME
+flash bank $_FLASHNAME pix32mx 0x1d000000 0 0 0 $_TARGETNAME
@end example
@comment numerous *disabled* commands are defined:
@@ -4555,7 +4555,7 @@ That seems pointless since the same effect can be had using the
standard @command{flash erase_address} command.}
@example
-flash bank stellaris 0 0 0 0 $_TARGETNAME
+flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
@end example
@end deffn
@@ -4581,7 +4581,7 @@ The driver automatically recognizes a number of these chips using
the chip identification register, and autoconfigures itself.
@example
-flash bank stm32x 0 0 0 0 $_TARGETNAME
+flash bank $_FLASHNAME stm32x 0 0 0 0 $_TARGETNAME
@end example
Some stm32x-specific commands
@@ -4619,7 +4619,7 @@ The @var{str7x} driver defines one mandatory parameter, @var{variant},
which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
@example
-flash bank str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
+flash bank $_FLASHNAME str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
@end example
@deffn Command {str7x disable_jtag} bank
@@ -4635,7 +4635,7 @@ The str9 needs the flash controller to be configured using
the @command{str9x flash_config} command prior to Flash programming.
@example
-flash bank str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
+flash bank $_FLASHNAME str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
str9x flash_config 0 4 2 0 0x80000
@end example
@@ -4785,13 +4785,13 @@ Currently, the mflash driver supports s3c2440 and pxa270.
Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
@example
-mflash bank s3c2440 0x10000000 1b 0
+mflash bank $_FLASHNAME s3c2440 0x10000000 1b 0
@end example
Example for pxa270 mflash where @var{RST pin} is GPIO 43:
@example
-mflash bank pxa270 0x08000000 43 0
+mflash bank $_FLASHNAME pxa270 0x08000000 43 0
@end example
@end deffn
@@ -7406,8 +7406,8 @@ has closed the connection to OpenOCD. This might be a GDB issue.
@item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
are described, there is a parameter for specifying the clock frequency
-for LPC2000 internal flash devices (e.g. @option{flash bank lpc2000
-0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}), which must be
+for LPC2000 internal flash devices (e.g. @option{flash bank $_FLASHNAME lpc2000
+0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14746 calc_checksum}), which must be
specified in kilohertz. However, I do have a quartz crystal of a
frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
commit ae1c64706a6fa421b60884e23561f39016950f54
Author: Spencer Oliver <nt...@us...>
Date: Thu Mar 18 09:35:45 2010 +0000
PIC32MX: add unlock cmd
'unlock' performs a full unlock/erase of the device, removing any
code protection.
Signed-off-by: Spencer Oliver <nt...@us...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 98fc690..da2782b 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -4523,10 +4523,10 @@ flash bank ocl 0 0 0 0 $_TARGETNAME
@deffn {Flash Driver} pic32mx
The PIC32MX microcontrollers are based on the MIPS 4K cores,
and integrate flash memory.
-@emph{The current implementation is incomplete.}
@example
-flash bank pix32mx 0 0 0 0 $_TARGETNAME
+flash bank pix32mx 0x1fc00000 0 0 0 $_TARGETNAME
+flash bank pix32mx 0x1d000000 0 0 0 $_TARGETNAME
@end example
@comment numerous *disabled* commands are defined:
@@ -4538,6 +4538,10 @@ Some pic32mx-specific commands are defined:
Programs the specified 32-bit @var{value} at the given @var{address}
in the specified chip @var{bank}.
@end deffn
+@deffn Command {pic32mx unlock} bank
+Unlock and erase specified chip @var{bank}.
+This will remove any Code Protection.
+@end deffn
@end deffn
@deffn {Flash Driver} stellaris
diff --git a/src/flash/nor/pic32mx.c b/src/flash/nor/pic32mx.c
index c46264c..36744e6 100644
--- a/src/flash/nor/pic32mx.c
+++ b/src/flash/nor/pic32mx.c
@@ -31,6 +31,7 @@
#include "pic32mx.h"
#include <target/algorithm.h>
#include <target/mips32.h>
+#include <target/mips_m4k.h>
static const struct pic32mx_devs_s {
uint8_t devid;
@@ -664,6 +665,73 @@ COMMAND_HANDLER(pic32mx_handle_pgm_word_command)
return ERROR_OK;
}
+COMMAND_HANDLER(pic32mx_handle_unlock_command)
+{
+ uint32_t mchip_cmd;
+ struct target *target = NULL;
+ struct mips_m4k_common *mips_m4k;
+ struct mips_ejtag *ejtag_info;
+ int timeout = 10;
+
+ if (CMD_ARGC < 1)
+ {
+ command_print(CMD_CTX, "pic32mx unlock <bank>");
+ return ERROR_OK;
+ }
+
+ struct flash_bank *bank;
+ int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+ if (ERROR_OK != retval)
+ return retval;
+
+ target = bank->target;
+ mips_m4k = target_to_m4k(target);
+ ejtag_info = &mips_m4k->mips32.ejtag_info;
+
+ /* we have to use the MTAP to perform a full erase */
+ mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP);
+ mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND);
+
+ /* first check status of device */
+ mchip_cmd = MCHP_STATUS;
+ mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
+ if (mchip_cmd & (1 << 7))
+ {
+ /* device is not locked */
+ command_print(CMD_CTX, "pic32mx is already unlocked, erasing anyway");
+ }
+
+ /* unlock/erase device */
+ mchip_cmd = MCHP_ASERT_RST;
+ mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
+
+ mchip_cmd = MCHP_ERASE;
+ mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
+
+ do {
+ mchip_cmd = MCHP_STATUS;
+ mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
+ if (timeout-- == 0)
+ {
+ LOG_DEBUG("timeout waiting for unlock: 0x%" PRIx32 "", mchip_cmd);
+ break;
+ }
+ alive_sleep(1);
+ } while ((mchip_cmd & (1 << 2)) || (!(mchip_cmd & (1 << 3))));
+
+ mchip_cmd = MCHP_DE_ASSERT_RST;
+ mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
+
+ /* select ejtag tap */
+ mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
+
+ command_print(CMD_CTX, "pic32mx unlocked.\n"
+ "INFO: a reset or power cycle is required "
+ "for the new settings to take effect.");
+
+ return ERROR_OK;
+}
+
static const struct command_registration pic32mx_exec_command_handlers[] = {
{
.name = "pgm_word",
@@ -671,6 +739,13 @@ static const struct command_registration pic32mx_exec_command_handlers[] = {
.mode = COMMAND_EXEC,
.help = "program a word",
},
+ {
+ .name = "unlock",
+ .handler = pic32mx_handle_unlock_command,
+ .mode = COMMAND_EXEC,
+ .usage = "[bank_id]",
+ .help = "Unlock/Erase entire device.",
+ },
COMMAND_REGISTRATION_DONE
};
diff --git a/src/target/mips_ejtag.h b/src/target/mips_ejtag.h
index 164edd0..f302a70 100644
--- a/src/target/mips_ejtag.h
+++ b/src/target/mips_ejtag.h
@@ -48,6 +48,8 @@
/* microchip specific cmds */
#define MCHP_ASERT_RST 0xd1
#define MCHP_DE_ASSERT_RST 0xd0
+#define MCHP_ERASE 0xfc
+#define MCHP_STATUS 0x00
/* ejtag control register bits ECR */
#define EJTAG_CTRL_TOF (1 << 1)
commit b48a94f05da3a887f1978da01db77b79513d4aa9
Author: Spencer Oliver <nt...@us...>
Date: Wed Mar 17 17:24:22 2010 +0000
MIPS: remove unused arg from mips_ejtag_set_instr
This arg was never used and was just taken from the arm jtag code.
Signed-off-by: Spencer Oliver <nt...@us...>
diff --git a/src/target/mips32_dmaacc.c b/src/target/mips32_dmaacc.c
index aa36d2c..7d3c2da 100644
--- a/src/target/mips32_dmaacc.c
+++ b/src/target/mips32_dmaacc.c
@@ -49,11 +49,11 @@ begin_ejtag_dma_read:
/* Setup Address */
v = addr;
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
mips_ejtag_drscan_32(ejtag_info, &v);
/* Initiate DMA Read & set DSTRT */
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
@@ -64,11 +64,11 @@ begin_ejtag_dma_read:
} while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
/* Read Data */
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
mips_ejtag_drscan_32(ejtag_info, data);
/* Clear DMA & Check DERR */
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
ejtag_ctrl = ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
if (ejtag_ctrl & EJTAG_CTRL_DERR)
@@ -95,11 +95,11 @@ begin_ejtag_dma_read_h:
/* Setup Address */
v = addr;
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
mips_ejtag_drscan_32(ejtag_info, &v);
/* Initiate DMA Read & set DSTRT */
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
@@ -110,11 +110,11 @@ begin_ejtag_dma_read_h:
} while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
/* Read Data */
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
mips_ejtag_drscan_32(ejtag_info, &v);
/* Clear DMA & Check DERR */
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
ejtag_ctrl = ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
if (ejtag_ctrl & EJTAG_CTRL_DERR)
@@ -147,11 +147,11 @@ begin_ejtag_dma_read_b:
/* Setup Address */
v = addr;
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
mips_ejtag_drscan_32(ejtag_info, &v);
/* Initiate DMA Read & set DSTRT */
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
@@ -162,11 +162,11 @@ begin_ejtag_dma_read_b:
} while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
/* Read Data */
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
mips_ejtag_drscan_32(ejtag_info, &v);
/* Clear DMA & Check DERR */
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
ejtag_ctrl = ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
if (ejtag_ctrl & EJTAG_CTRL_DERR)
@@ -209,16 +209,16 @@ begin_ejtag_dma_write:
/* Setup Address */
v = addr;
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
mips_ejtag_drscan_32(ejtag_info, &v);
/* Setup Data */
v = data;
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
mips_ejtag_drscan_32(ejtag_info, &v);
/* Initiate DMA Write & set DSTRT */
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
@@ -229,7 +229,7 @@ begin_ejtag_dma_write:
} while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
/* Clear DMA & Check DERR */
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
ejtag_ctrl = ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
if (ejtag_ctrl & EJTAG_CTRL_DERR)
@@ -260,16 +260,16 @@ begin_ejtag_dma_write_h:
/* Setup Address */
v = addr;
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
mips_ejtag_drscan_32(ejtag_info, &v);
/* Setup Data */
v = data;
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
mips_ejtag_drscan_32(ejtag_info, &v);
/* Initiate DMA Write & set DSTRT */
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
@@ -280,7 +280,7 @@ begin_ejtag_dma_write_h:
} while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
/* Clear DMA & Check DERR */
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
ejtag_ctrl = ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
if (ejtag_ctrl & EJTAG_CTRL_DERR)
@@ -312,16 +312,16 @@ begin_ejtag_dma_write_b:
/* Setup Address*/
v = addr;
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
mips_ejtag_drscan_32(ejtag_info, &v);
/* Setup Data */
v = data;
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
mips_ejtag_drscan_32(ejtag_info, &v);
/* Initiate DMA Write & set DSTRT */
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
@@ -332,7 +332,7 @@ begin_ejtag_dma_write_b:
} while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
/* Clear DMA & Check DERR */
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
ejtag_ctrl = ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
if (ejtag_ctrl & EJTAG_CTRL_DERR)
diff --git a/src/target/mips32_pracc.c b/src/target/mips32_pracc.c
index bcba0f1..19ba886 100644
--- a/src/target/mips32_pracc.c
+++ b/src/target/mips32_pracc.c
@@ -96,7 +96,7 @@ static int wait_for_pracc_rw(struct mips_ejtag *ejtag_info, uint32_t *ctrl)
while (1)
{
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
ejtag_ctrl = ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
if (ejtag_ctrl & EJTAG_CTRL_PRACC)
@@ -149,12 +149,12 @@ static int mips32_pracc_exec_read(struct mips32_pracc_context *ctx, uint32_t add
}
/* Send the data out */
- mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA, NULL);
+ mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA);
mips_ejtag_drscan_32(ctx->ejtag_info, &data);
/* Clear the access pending bit (let the processor eat!) */
ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC;
- mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL, NULL);
+ mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL);
mips_ejtag_drscan_32(ctx->ejtag_info, &ejtag_ctrl);
jtag_add_clocks(5);
@@ -169,12 +169,12 @@ static int mips32_pracc_exec_write(struct mips32_pracc_context *ctx, uint32_t ad
int offset;
struct mips_ejtag *ejtag_info = ctx->ejtag_info;
- mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA, NULL);
+ mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA);
mips_ejtag_drscan_32(ctx->ejtag_info, &data);
/* Clear access pending bit */
ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC;
- mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL, NULL);
+ mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL);
mips_ejtag_drscan_32(ctx->ejtag_info, &ejtag_ctrl);
jtag_add_clocks(5);
@@ -230,7 +230,7 @@ int mips32_pracc_exec(struct mips_ejtag *ejtag_info, int code_len, const uint32_
return retval;
address = data = 0;
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
mips_ejtag_drscan_32(ejtag_info, &address);
/* Check for read or write */
@@ -979,12 +979,12 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are
if ((retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl)) != ERROR_OK)
return retval;
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
mips_ejtag_drscan_32(ejtag_info, &jmp_code[i]);
/* Clear the access pending bit (let the processor eat!) */
ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC;
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
}
@@ -993,7 +993,7 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are
/* next fetch to dmseg should be in FASTDATA_AREA, check */
address = 0;
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
mips_ejtag_drscan_32(ejtag_info, &address);
if (address != MIPS32_PRACC_FASTDATA_AREA)
@@ -1001,12 +1001,12 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are
/* Send the load start address */
val = addr;
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA);
mips_ejtag_fastdata_scan(ejtag_info, 1, &val);
/* Send the load end address */
val = addr + (count - 1) * 4;
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA);
mips_ejtag_fastdata_scan(ejtag_info, 1, &val);
for (i = 0; i < count; i++)
@@ -1026,7 +1026,7 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are
return retval;
address = 0;
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
mips_ejtag_drscan_32(ejtag_info, &address);
if (address != MIPS32_PRACC_TEXT)
diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c
index 974c836..3ea23d4 100644
--- a/src/target/mips_ejtag.c
+++ b/src/target/mips_ejtag.c
@@ -28,7 +28,7 @@
#include "mips32.h"
#include "mips_ejtag.h"
-int mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, int new_instr, void *delete_me_and_submit_patch)
+int mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, int new_instr)
{
struct jtag_tap *tap;
@@ -58,7 +58,7 @@ int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode)
jtag_set_end_state(TAP_IDLE);
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE);
field.num_bits = 32;
field.out_value = NULL;
@@ -80,7 +80,7 @@ int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impcode)
jtag_set_end_state(TAP_IDLE);
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE);
field.num_bits = 32;
field.out_value = NULL;
@@ -210,7 +210,7 @@ int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info)
{
uint32_t ejtag_ctrl;
jtag_set_end_state(TAP_IDLE);
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
/* set debug break bit */
ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_JTAGBRK;
diff --git a/src/target/mips_ejtag.h b/src/target/mips_ejtag.h
index a086cd5..164edd0 100644
--- a/src/target/mips_ejtag.h
+++ b/src/target/mips_ejtag.h
@@ -129,7 +129,7 @@ struct mips_ejtag
};
int mips_ejtag_set_instr(struct mips_ejtag *ejtag_info,
- int new_instr, void *delete_me_and_submit_patch);
+ int new_instr);
int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info);
int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info);
int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impcode);
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index d1b4589..5919f5b 100644
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -113,7 +113,7 @@ int mips_m4k_poll(struct target *target)
/* read ejtag control reg */
jtag_set_end_state(TAP_IDLE);
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
/* clear this bit before handling polling
@@ -125,7 +125,7 @@ int mips_m4k_poll(struct target *target)
jtag_set_end_state(TAP_IDLE);
ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
LOG_DEBUG("Reset Detected");
}
@@ -136,7 +136,7 @@ int mips_m4k_poll(struct target *target)
if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
{
jtag_set_end_state(TAP_IDLE);
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
target->state = TARGET_HALTED;
@@ -228,12 +228,12 @@ int mips_m4k_assert_reset(struct target *target)
{
/* use hardware to catch reset */
jtag_set_end_state(TAP_IDLE);
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT);
}
else
{
jtag_set_end_state(TAP_IDLE);
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
}
if (assert_srst)
@@ -257,21 +257,21 @@ int mips_m4k_assert_reset(struct target *target)
LOG_DEBUG("Using MTAP reset to reset processor...");
/* use microchip specific MTAP reset */
- mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP, NULL);
- mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND, NULL);
+ mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP);
+ mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND);
mchip_cmd = MCHP_ASERT_RST;
mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
mchip_cmd = MCHP_DE_ASSERT_RST;
mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
- mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP, NULL);
+ mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
}
else
{
/* use ejtag reset - not supported by all cores */
uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
}
}
@@ -933,7 +933,7 @@ int mips_m4k_examine(struct target *target)
{
/* we are using a pic32mx so select ejtag port
* as it is not selected by default */
- mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP, NULL);
+ mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
mips_m4k->is_pic32mx = true;
}
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 46 ++++++++++++++------------
src/flash/nor/pic32mx.c | 75 ++++++++++++++++++++++++++++++++++++++++++++
src/target/mips32_dmaacc.c | 48 ++++++++++++++--------------
src/target/mips32_pracc.c | 24 +++++++-------
src/target/mips_ejtag.c | 8 ++--
src/target/mips_ejtag.h | 4 ++-
src/target/mips_m4k.c | 20 ++++++------
7 files changed, 153 insertions(+), 72 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
