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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-98-g3ad171c
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From: Spencer O. <nt...@us...> - 2010-03-17 11:10:49
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- Log -----------------------------------------------------------------
commit 3ad171cd537f8fc1bac649f24513ebfafd95baf2
Author: Spencer Oliver <nt...@us...>
Date: Wed Mar 17 09:57:44 2010 +0000
SCRIPT: add add_script_search_dir cmd
Add a add_script_search_dir cmd so that adding search
dir's can be added to cfg scripts.
Signed-off-by: Spencer Oliver <nt...@us...>
diff --git a/NEWS b/NEWS
index cc2560b..0b9a6a4 100644
--- a/NEWS
+++ b/NEWS
@@ -16,6 +16,11 @@ JTAG Layer:
Boundary Scan:
Target Layer:
+ MIPS:
+ - "ejtag_srst" variant removed. The same functionality is
+ obtained by using "reset_config none".
+ - added PIC32MX software reset support, this means srst is not
+ required to be connected anymore.
Flash Layer:
New "stellaris recover" command, implements the procedure
@@ -23,12 +28,15 @@ Flash Layer:
state to the factory defaults, including erasing
the flash and its protection bits, and possibly
re-enabling hardware debugging).
-
+ PIC32MX now uses algorithm for flash programming, this
+ has increased the performance by approx 96%.
Board, Target, and Interface Configuration Scripts:
Support IAR LPC1768 kickstart board (by Olimex)
Core Jim/TCL Scripting:
+ New "add_script_search_dir" command, behaviour is the same
+ as the "-s" cmd line option.
Documentation:
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 780cd4d..98fc690 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -590,6 +590,7 @@ Configuration files and scripts are searched for in
@enumerate
@item the current directory,
@item any search dir specified on the command line using the @option{-s} option,
+@item any search dir specified using the @command{add_script_search_dir} command,
@item @file{$HOME/.openocd} (not on Windows),
@item the site wide script library @file{$pkgdatadir/site} and
@item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
@@ -5396,6 +5397,10 @@ Redirect logging to @var{filename};
the initial log output channel is stderr.
@end deffn
+@deffn Command add_script_search_dir [directory]
+Add @var{directory} to the file/script search path.
+@end deffn
+
@anchor{Target State handling}
@section Target State handling
@cindex reset
diff --git a/src/openocd.c b/src/openocd.c
index d376f5f..54c454d 100644
--- a/src/openocd.c
+++ b/src/openocd.c
@@ -159,6 +159,16 @@ COMMAND_HANDLER(handle_init_command)
return ERROR_OK;
}
+COMMAND_HANDLER(handle_add_script_search_dir_command)
+{
+ if (CMD_ARGC != 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ add_script_search_dir(CMD_ARGV[0]);
+
+ return ERROR_OK;
+}
+
static const struct command_registration openocd_command_handlers[] = {
{
.name = "version",
@@ -182,6 +192,13 @@ static const struct command_registration openocd_command_handlers[] = {
"called automatically at the end of startup.",
},
+ {
+ .name = "add_script_search_dir",
+ .handler = &handle_add_script_search_dir_command,
+ .mode = COMMAND_ANY,
+ .help = "dir to search for config files and scripts",
+
+ },
COMMAND_REGISTRATION_DONE
};
commit e7e9bfde47768b22be8b15c30c027dc8fb67c778
Author: Spencer Oliver <nt...@us...>
Date: Tue Mar 16 12:54:08 2010 +0000
PIC32: add software reset support
The PIC32MX does not support the ejtag software reset - it is
optional in the ejtag spec.
We perform the equivalent using the microchip specific MTAP cmd's.
Signed-off-by: Spencer Oliver <nt...@us...>
diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c
index 984b535..cea8fa8 100644
--- a/src/target/mips_ejtag.c
+++ b/src/target/mips_ejtag.c
@@ -127,6 +127,37 @@ int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data)
return ERROR_OK;
}
+int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint32_t *data)
+{
+ struct jtag_tap *tap;
+ tap = ejtag_info->tap;
+
+ if (tap == NULL)
+ return ERROR_FAIL;
+ struct scan_field field;
+ uint8_t t[4], r[4];
+ int retval;
+
+ field.num_bits = 8;
+ field.out_value = t;
+ buf_set_u32(field.out_value, 0, field.num_bits, *data);
+ field.in_value = r;
+
+ jtag_add_dr_scan(tap, 1, &field, jtag_get_end_state());
+
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ LOG_ERROR("register read failed");
+ return retval;
+ }
+
+ *data = buf_get_u32(field.in_value, 0, 32);
+
+ keep_alive();
+
+ return ERROR_OK;
+}
+
int mips_ejtag_step_enable(struct mips_ejtag *ejtag_info)
{
static const uint32_t code[] = {
diff --git a/src/target/mips_ejtag.h b/src/target/mips_ejtag.h
index 5c1f245..a086cd5 100644
--- a/src/target/mips_ejtag.h
+++ b/src/target/mips_ejtag.h
@@ -43,6 +43,11 @@
/* microchip PIC32MX specific instructions */
#define MTAP_SW_MTAP 0x04
#define MTAP_SW_ETAP 0x05
+#define MTAP_COMMAND 0x07
+
+/* microchip specific cmds */
+#define MCHP_ASERT_RST 0xd1
+#define MCHP_DE_ASSERT_RST 0xd0
/* ejtag control register bits ECR */
#define EJTAG_CTRL_TOF (1 << 1)
@@ -130,6 +135,7 @@ int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info);
int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impcode);
int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode);
int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data);
+int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint32_t *data);
int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write, uint32_t *data);
int mips_ejtag_init(struct mips_ejtag *ejtag_info);
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index d3536d8..d1b4589 100644
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -250,11 +250,30 @@ int mips_m4k_assert_reset(struct target *target)
}
else
{
+ if (mips_m4k->is_pic32mx)
+ {
+ uint32_t mchip_cmd;
+
+ LOG_DEBUG("Using MTAP reset to reset processor...");
+
+ /* use microchip specific MTAP reset */
+ mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP, NULL);
+ mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND, NULL);
+
+ mchip_cmd = MCHP_ASERT_RST;
+ mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
+ mchip_cmd = MCHP_DE_ASSERT_RST;
+ mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
+ mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP, NULL);
+ }
+ else
+ {
/* use ejtag reset - not supported by all cores */
uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+ }
}
target->state = TARGET_RESET;
@@ -878,7 +897,7 @@ int mips_m4k_init_target(struct command_context *cmd_ctx, struct target *target)
int mips_m4k_init_arch_info(struct target *target, struct mips_m4k_common *mips_m4k,
struct jtag_tap *tap)
{
- struct mips32_common *mips32 = &mips_m4k->mips32_common;
+ struct mips32_common *mips32 = &mips_m4k->mips32;
mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
@@ -901,8 +920,8 @@ int mips_m4k_target_create(struct target *target, Jim_Interp *interp)
int mips_m4k_examine(struct target *target)
{
int retval;
- struct mips32_common *mips32 = target_to_mips32(target);
- struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
+ struct mips_m4k_common *mips_m4k = target_to_m4k(target);
+ struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
uint32_t idcode = 0;
if (!target_was_examined(target))
@@ -916,6 +935,7 @@ int mips_m4k_examine(struct target *target)
* as it is not selected by default */
mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP, NULL);
LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
+ mips_m4k->is_pic32mx = true;
}
}
diff --git a/src/target/mips_m4k.h b/src/target/mips_m4k.h
index 9b33020..5eb2029 100644
--- a/src/target/mips_m4k.h
+++ b/src/target/mips_m4k.h
@@ -32,6 +32,7 @@ struct target;
struct mips_m4k_common
{
int common_magic;
+ bool is_pic32mx;
struct mips32_common mips32;
};
commit 79ca05b106ef92915c4e9288cbf34d5db1cf4cd2
Author: Spencer Oliver <nt...@us...>
Date: Tue Mar 16 12:48:53 2010 +0000
MIPS: remove ejtag_srst variant
The mips_m4k_assert_reset has now been restructured
so the variant ejtag_srst is not required anymore.
The ejtag software reset will be used if the target does not
have srst connected.
Remove ejtag_srst from docs.
Signed-off-by: Spencer Oliver <nt...@us...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index e1bb2b7..780cd4d 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -3453,14 +3453,6 @@ be detected and the normal reset behaviour used.
@item @code{fa526} -- resembles arm920 (w/o Thumb)
@item @code{feroceon} -- resembles arm926
@item @code{mips_m4k} -- a MIPS core. This supports one variant:
-@itemize @minus
-@item @code{ejtag_srst} ... Use this when debugging targets that do not
-provide a functional SRST line on the EJTAG connector. This causes
-OpenOCD to instead use an EJTAG software reset command to reset the
-processor.
-You still need to enable @option{srst} on the @command{reset_config}
-command to enable OpenOCD hardware reset functionality.
-@end itemize
@item @code{xscale} -- this is actually an architecture,
not a CPU type. It is based on the ARMv5 architecture.
There are several variants defined:
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index 389daf9..d3536d8 100644
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -212,18 +212,17 @@ int mips_m4k_halt(struct target *target)
int mips_m4k_assert_reset(struct target *target)
{
- struct mips32_common *mips32 = target_to_mips32(target);
- struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
+ struct mips_m4k_common *mips_m4k = target_to_m4k(target);
+ struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
+ int assert_srst = 1;
LOG_DEBUG("target->state: %s",
target_state_name(target));
enum reset_types jtag_reset_config = jtag_get_reset_config();
+
if (!(jtag_reset_config & RESET_HAS_SRST))
- {
- LOG_ERROR("Can't assert SRST");
- return ERROR_FAIL;
- }
+ assert_srst = 0;
if (target->reset_halt)
{
@@ -237,14 +236,7 @@ int mips_m4k_assert_reset(struct target *target)
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
}
- if (strcmp(target->variant, "ejtag_srst") == 0)
- {
- uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
- LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
- mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
- }
- else
+ if (assert_srst)
{
/* here we should issue a srst only, but we may have to assert trst as well */
if (jtag_reset_config & RESET_SRST_PULLS_TRST)
@@ -256,11 +248,19 @@ int mips_m4k_assert_reset(struct target *target)
jtag_add_reset(0, 1);
}
}
+ else
+ {
+ /* use ejtag reset - not supported by all cores */
+ uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
+ LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+ }
target->state = TARGET_RESET;
jtag_add_sleep(50000);
- register_cache_invalidate(mips32->core_cache);
+ register_cache_invalidate(mips_m4k->mips32.core_cache);
if (target->reset_halt)
{
diff --git a/src/target/mips_m4k.h b/src/target/mips_m4k.h
index 4fe14a0..9b33020 100644
--- a/src/target/mips_m4k.h
+++ b/src/target/mips_m4k.h
@@ -32,14 +32,14 @@ struct target;
struct mips_m4k_common
{
int common_magic;
- struct mips32_common mips32_common;
+ struct mips32_common mips32;
};
static inline struct mips_m4k_common *
target_to_m4k(struct target *target)
{
return container_of(target->arch_info,
- struct mips_m4k_common, mips32_common);
+ struct mips_m4k_common, mips32);
}
int mips_m4k_bulk_write_memory(struct target *target,
-----------------------------------------------------------------------
Summary of changes:
NEWS | 10 +++++++-
doc/openocd.texi | 13 ++++------
src/openocd.c | 17 ++++++++++++++
src/target/mips_ejtag.c | 31 ++++++++++++++++++++++++++
src/target/mips_ejtag.h | 6 +++++
src/target/mips_m4k.c | 56 +++++++++++++++++++++++++++++++---------------
src/target/mips_m4k.h | 5 ++-
7 files changed, 109 insertions(+), 29 deletions(-)
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