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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-54-g45a528f
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From: David B. <dbr...@us...> - 2010-03-05 06:52:59
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from 5e78ddcea0d8303c316f687c05dfa78af27109d8 (commit)
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- Log -----------------------------------------------------------------
commit 45a528ff3c0582f7d22b65d76d925f34a6956957
Author: David Brownell <dbr...@us...>
Date: Thu Mar 4 21:51:58 2010 -0800
rename "swjdp_common" as "adiv5_dap"
This partially corrects an inappropriate name choice (and its
associated FIXME).
There are still too many variables named "swjdp", bug little
current code actually relies on them referencing an SWJ-DP instead
of some other flavor of DAP. Only the two new dap_to{swd,jtag}()
calls could behave differently on an SWJ-DP instead of a SW-DP or
a JTAG-DP.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index c5e0dd3..e30ddf6 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -108,7 +108,7 @@ static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address
* @param invalue NULL, or points to a 32-bit (little-endian) integer
* @param ack points to where the three bit JTAG_ACK_* code will be stored
*/
-static int adi_jtag_dp_scan(struct swjdp_common *swjdp,
+static int adi_jtag_dp_scan(struct adiv5_dap *swjdp,
uint8_t instr, uint8_t reg_addr, uint8_t RnW,
uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
{
@@ -161,7 +161,7 @@ static int adi_jtag_dp_scan(struct swjdp_common *swjdp,
* conversions are performed (so the types of invalue and outvalue
* must be different).
*/
-static int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp,
+static int adi_jtag_dp_scan_u32(struct adiv5_dap *swjdp,
uint8_t instr, uint8_t reg_addr, uint8_t RnW,
uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
{
@@ -185,14 +185,14 @@ static int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp,
/**
* Utility to write AP registers.
*/
-static inline int adi_jtag_ap_write_check(struct swjdp_common *dap,
+static inline int adi_jtag_ap_write_check(struct adiv5_dap *dap,
uint8_t reg_addr, uint8_t *outvalue)
{
return adi_jtag_dp_scan(dap, JTAG_DP_APACC, reg_addr, DPAP_WRITE,
outvalue, NULL, NULL);
}
-static int adi_jtag_scan_inout_check_u32(struct swjdp_common *swjdp,
+static int adi_jtag_scan_inout_check_u32(struct adiv5_dap *swjdp,
uint8_t instr, uint8_t reg_addr, uint8_t RnW,
uint32_t outvalue, uint32_t *invalue)
{
@@ -213,7 +213,7 @@ static int adi_jtag_scan_inout_check_u32(struct swjdp_common *swjdp,
return retval;
}
-static int jtagdp_transaction_endcheck(struct swjdp_common *swjdp)
+static int jtagdp_transaction_endcheck(struct adiv5_dap *swjdp)
{
int retval;
uint32_t ctrlstat;
@@ -367,7 +367,7 @@ static int jtagdp_transaction_endcheck(struct swjdp_common *swjdp)
* @param apsel Number of the AP to (implicitly) use with further
* transactions. This normally identifies a MEM-AP.
*/
-void dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel)
+void dap_ap_select(struct adiv5_dap *swjdp,uint8_t apsel)
{
uint32_t select = (apsel << 24) & 0xFF000000;
@@ -402,7 +402,7 @@ void dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel)
*
* @return ERROR_OK if the transaction was properly queued, else a fault code.
*/
-int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar)
+int dap_setup_accessport(struct adiv5_dap *swjdp, uint32_t csw, uint32_t tar)
{
int retval;
@@ -440,7 +440,7 @@ int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar)
*
* @return ERROR_OK for success. Otherwise a fault code.
*/
-int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address,
+int mem_ap_read_u32(struct adiv5_dap *swjdp, uint32_t address,
uint32_t *value)
{
int retval;
@@ -468,7 +468,7 @@ int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address,
* @return ERROR_OK for success; *value holds the result.
* Otherwise a fault code.
*/
-int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address,
+int mem_ap_read_atomic_u32(struct adiv5_dap *swjdp, uint32_t address,
uint32_t *value)
{
int retval;
@@ -491,7 +491,7 @@ int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address,
*
* @return ERROR_OK for success. Otherwise a fault code.
*/
-int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address,
+int mem_ap_write_u32(struct adiv5_dap *swjdp, uint32_t address,
uint32_t value)
{
int retval;
@@ -519,7 +519,7 @@ int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address,
*
* @return ERROR_OK for success; the data was written. Otherwise a fault code.
*/
-int mem_ap_write_atomic_u32(struct swjdp_common *swjdp, uint32_t address,
+int mem_ap_write_atomic_u32(struct adiv5_dap *swjdp, uint32_t address,
uint32_t value)
{
int retval = mem_ap_write_u32(swjdp, address, value);
@@ -532,12 +532,12 @@ int mem_ap_write_atomic_u32(struct swjdp_common *swjdp, uint32_t address,
/*****************************************************************************
* *
-* mem_ap_write_buf(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
+* mem_ap_write_buf(struct adiv5_dap *swjdp, uint8_t *buffer, int count, uint32_t address) *
* *
* Write a buffer in target order (little endian) *
* *
*****************************************************************************/
-int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
+int mem_ap_write_buf_u32(struct adiv5_dap *swjdp, uint8_t *buffer, int count, uint32_t address)
{
int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
uint32_t adr = address;
@@ -608,7 +608,7 @@ int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count,
return retval;
}
-static int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp,
+static int mem_ap_write_buf_packed_u16(struct adiv5_dap *swjdp,
uint8_t *buffer, int count, uint32_t address)
{
int retval = ERROR_OK;
@@ -688,7 +688,7 @@ static int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp,
return retval;
}
-int mem_ap_write_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
+int mem_ap_write_buf_u16(struct adiv5_dap *swjdp, uint8_t *buffer, int count, uint32_t address)
{
int retval = ERROR_OK;
@@ -717,7 +717,7 @@ int mem_ap_write_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count,
return retval;
}
-static int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp,
+static int mem_ap_write_buf_packed_u8(struct adiv5_dap *swjdp,
uint8_t *buffer, int count, uint32_t address)
{
int retval = ERROR_OK;
@@ -792,7 +792,7 @@ static int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp,
return retval;
}
-int mem_ap_write_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
+int mem_ap_write_buf_u8(struct adiv5_dap *swjdp, uint8_t *buffer, int count, uint32_t address)
{
int retval = ERROR_OK;
@@ -827,7 +827,7 @@ int mem_ap_write_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count,
* @param address Memory address from which to read words; all the
* words must be readable by the currently selected MEM-AP.
*/
-int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer,
+int mem_ap_read_buf_u32(struct adiv5_dap *swjdp, uint8_t *buffer,
int count, uint32_t address)
{
int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
@@ -924,7 +924,7 @@ int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer,
return retval;
}
-static int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp,
+static int mem_ap_read_buf_packed_u16(struct adiv5_dap *swjdp,
uint8_t *buffer, int count, uint32_t address)
{
uint32_t invalue;
@@ -984,7 +984,7 @@ static int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp,
* @param address Memory address from which to read words; all the
* words must be readable by the currently selected MEM-AP.
*/
-int mem_ap_read_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer,
+int mem_ap_read_buf_u16(struct adiv5_dap *swjdp, uint8_t *buffer,
int count, uint32_t address)
{
uint32_t invalue, i;
@@ -1032,7 +1032,7 @@ int mem_ap_read_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer,
* The solution is to arrange for a large out/in scan in this loop and
* and convert data afterwards.
*/
-static int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp,
+static int mem_ap_read_buf_packed_u8(struct adiv5_dap *swjdp,
uint8_t *buffer, int count, uint32_t address)
{
uint32_t invalue;
@@ -1089,7 +1089,7 @@ static int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp,
* @param address Memory address from which to read data; all the
* data must be readable by the currently selected MEM-AP.
*/
-int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer,
+int mem_ap_read_buf_u8(struct adiv5_dap *swjdp, uint8_t *buffer,
int count, uint32_t address)
{
uint32_t invalue;
@@ -1117,7 +1117,7 @@ int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer,
/*--------------------------------------------------------------------------*/
-static int jtag_idcode_q_read(struct swjdp_common *dap,
+static int jtag_idcode_q_read(struct adiv5_dap *dap,
uint8_t *ack, uint32_t *data)
{
struct arm_jtag *jtag_info = dap->jtag_info;
@@ -1147,14 +1147,14 @@ static int jtag_idcode_q_read(struct swjdp_common *dap,
return retval;
}
-static int jtag_dp_q_read(struct swjdp_common *dap, unsigned reg,
+static int jtag_dp_q_read(struct adiv5_dap *dap, unsigned reg,
uint32_t *data)
{
return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
reg, DPAP_READ, 0, data);
}
-static int jtag_dp_q_write(struct swjdp_common *dap, unsigned reg,
+static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned reg,
uint32_t data)
{
return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
@@ -1162,7 +1162,7 @@ static int jtag_dp_q_write(struct swjdp_common *dap, unsigned reg,
}
/** Select the AP register bank matching bits 7:4 of reg. */
-static int jtag_ap_q_bankselect(struct swjdp_common *dap, unsigned reg)
+static int jtag_ap_q_bankselect(struct adiv5_dap *dap, unsigned reg)
{
uint32_t select = reg & 0x000000F0;
@@ -1175,7 +1175,7 @@ static int jtag_ap_q_bankselect(struct swjdp_common *dap, unsigned reg)
return jtag_dp_q_write(dap, DP_SELECT, select);
}
-static int jtag_ap_q_read(struct swjdp_common *dap, unsigned reg,
+static int jtag_ap_q_read(struct adiv5_dap *dap, unsigned reg,
uint32_t *data)
{
int retval = jtag_ap_q_bankselect(dap, reg);
@@ -1187,7 +1187,7 @@ static int jtag_ap_q_read(struct swjdp_common *dap, unsigned reg,
DPAP_READ, 0, data);
}
-static int jtag_ap_q_write(struct swjdp_common *dap, unsigned reg,
+static int jtag_ap_q_write(struct adiv5_dap *dap, unsigned reg,
uint32_t data)
{
uint8_t out_value_buf[4];
@@ -1201,14 +1201,14 @@ static int jtag_ap_q_write(struct swjdp_common *dap, unsigned reg,
return adi_jtag_ap_write_check(dap, reg, out_value_buf);
}
-static int jtag_ap_q_abort(struct swjdp_common *dap, uint8_t *ack)
+static int jtag_ap_q_abort(struct adiv5_dap *dap, uint8_t *ack)
{
/* for JTAG, this is the only valid ABORT register operation */
return adi_jtag_dp_scan_u32(dap, JTAG_DP_ABORT,
0, DPAP_WRITE, 1, NULL, ack);
}
-static int jtag_dp_run(struct swjdp_common *dap)
+static int jtag_dp_run(struct adiv5_dap *dap)
{
return jtagdp_transaction_endcheck(dap);
}
@@ -1237,7 +1237,7 @@ static const struct dap_ops jtag_dp_ops = {
* in layering. (JTAG is useful without any debug target; but not SWD.)
* And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
*/
-int ahbap_debugport_init(struct swjdp_common *swjdp)
+int ahbap_debugport_init(struct adiv5_dap *swjdp)
{
uint32_t idreg, romaddr, dummy;
uint32_t ctrlstat;
@@ -1353,7 +1353,7 @@ is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
}
int dap_info_command(struct command_context *cmd_ctx,
- struct swjdp_common *swjdp, int apsel)
+ struct adiv5_dap *swjdp, int apsel)
{
int retval;
uint32_t dbgbase, apid;
diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index e867b85..abdbd24 100644
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -133,10 +133,8 @@
* a choice made at board design time (by only using the SWD pins), or
* as part of setting up a debug session (if all the dual-role JTAG/SWD
* signals are available).
- *
- * @todo Rename "swjdp_common" as "dap". Use of SWJ-DP is optional!
*/
-struct swjdp_common
+struct adiv5_dap
{
const struct dap_ops *ops;
@@ -201,27 +199,27 @@ struct dap_ops {
bool is_swd;
/** Reads the DAP's IDCODe register. */
- int (*queue_idcode_read)(struct swjdp_common *dap,
+ int (*queue_idcode_read)(struct adiv5_dap *dap,
uint8_t *ack, uint32_t *data);
/** DP register read. */
- int (*queue_dp_read)(struct swjdp_common *dap, unsigned reg,
+ int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg,
uint32_t *data);
/** DP register write. */
- int (*queue_dp_write)(struct swjdp_common *dap, unsigned reg,
+ int (*queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
uint32_t data);
/** AP register read. */
- int (*queue_ap_read)(struct swjdp_common *dap, unsigned reg,
+ int (*queue_ap_read)(struct adiv5_dap *dap, unsigned reg,
uint32_t *data);
/** AP register write. */
- int (*queue_ap_write)(struct swjdp_common *dap, unsigned reg,
+ int (*queue_ap_write)(struct adiv5_dap *dap, unsigned reg,
uint32_t data);
/** AP operation abort. */
- int (*queue_ap_abort)(struct swjdp_common *dap, uint8_t *ack);
+ int (*queue_ap_abort)(struct adiv5_dap *dap, uint8_t *ack);
/** Executes all queued DAP operations. */
- int (*run)(struct swjdp_common *dap);
+ int (*run)(struct adiv5_dap *dap);
};
/**
@@ -235,7 +233,7 @@ struct dap_ops {
*
* @return ERROR_OK for success, else a fault code.
*/
-static inline int dap_queue_idcode_read(struct swjdp_common *dap,
+static inline int dap_queue_idcode_read(struct adiv5_dap *dap,
uint8_t *ack, uint32_t *data)
{
return dap->ops->queue_idcode_read(dap, ack, data);
@@ -253,7 +251,7 @@ static inline int dap_queue_idcode_read(struct swjdp_common *dap,
*
* @return ERROR_OK for success, else a fault code.
*/
-static inline int dap_queue_dp_read(struct swjdp_common *dap,
+static inline int dap_queue_dp_read(struct adiv5_dap *dap,
unsigned reg, uint32_t *data)
{
return dap->ops->queue_dp_read(dap, reg, data);
@@ -270,7 +268,7 @@ static inline int dap_queue_dp_read(struct swjdp_common *dap,
*
* @return ERROR_OK for success, else a fault code.
*/
-static inline int dap_queue_dp_write(struct swjdp_common *dap,
+static inline int dap_queue_dp_write(struct adiv5_dap *dap,
unsigned reg, uint32_t data)
{
return dap->ops->queue_dp_write(dap, reg, data);
@@ -286,7 +284,7 @@ static inline int dap_queue_dp_write(struct swjdp_common *dap,
*
* @return ERROR_OK for success, else a fault code.
*/
-static inline int dap_queue_ap_read(struct swjdp_common *dap,
+static inline int dap_queue_ap_read(struct adiv5_dap *dap,
unsigned reg, uint32_t *data)
{
return dap->ops->queue_ap_read(dap, reg, data);
@@ -301,7 +299,7 @@ static inline int dap_queue_ap_read(struct swjdp_common *dap,
*
* @return ERROR_OK for success, else a fault code.
*/
-static inline int dap_queue_ap_write(struct swjdp_common *dap,
+static inline int dap_queue_ap_write(struct adiv5_dap *dap,
unsigned reg, uint32_t data)
{
return dap->ops->queue_ap_write(dap, reg, data);
@@ -318,7 +316,7 @@ static inline int dap_queue_ap_write(struct swjdp_common *dap,
*
* @return ERROR_OK for success, else a fault code.
*/
-static inline int dap_queue_ap_abort(struct swjdp_common *dap, uint8_t *ack)
+static inline int dap_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
{
return dap->ops->queue_ap_abort(dap, ack);
}
@@ -333,59 +331,59 @@ static inline int dap_queue_ap_abort(struct swjdp_common *dap, uint8_t *ack)
*
* @return ERROR_OK for success, else a fault code.
*/
-static inline int dap_run(struct swjdp_common *dap)
+static inline int dap_run(struct adiv5_dap *dap)
{
return dap->ops->run(dap);
}
/** Accessor for currently selected DAP-AP number (0..255) */
-static inline uint8_t dap_ap_get_select(struct swjdp_common *swjdp)
+static inline uint8_t dap_ap_get_select(struct adiv5_dap *swjdp)
{
return (uint8_t)(swjdp ->apsel >> 24);
}
/* AP selection applies to future AP transactions */
-void dap_ap_select(struct swjdp_common *dap,uint8_t apsel);
+void dap_ap_select(struct adiv5_dap *dap,uint8_t apsel);
/* Queued AP transactions */
-int dap_setup_accessport(struct swjdp_common *swjdp,
+int dap_setup_accessport(struct adiv5_dap *swjdp,
uint32_t csw, uint32_t tar);
/* Queued MEM-AP memory mapped single word transfers */
-int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value);
-int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value);
+int mem_ap_read_u32(struct adiv5_dap *swjdp, uint32_t address, uint32_t *value);
+int mem_ap_write_u32(struct adiv5_dap *swjdp, uint32_t address, uint32_t value);
/* Synchronous MEM-AP memory mapped single word transfers */
-int mem_ap_read_atomic_u32(struct swjdp_common *swjdp,
+int mem_ap_read_atomic_u32(struct adiv5_dap *swjdp,
uint32_t address, uint32_t *value);
-int mem_ap_write_atomic_u32(struct swjdp_common *swjdp,
+int mem_ap_write_atomic_u32(struct adiv5_dap *swjdp,
uint32_t address, uint32_t value);
/* MEM-AP memory mapped bus block transfers */
-int mem_ap_read_buf_u8(struct swjdp_common *swjdp,
+int mem_ap_read_buf_u8(struct adiv5_dap *swjdp,
uint8_t *buffer, int count, uint32_t address);
-int mem_ap_read_buf_u16(struct swjdp_common *swjdp,
+int mem_ap_read_buf_u16(struct adiv5_dap *swjdp,
uint8_t *buffer, int count, uint32_t address);
-int mem_ap_read_buf_u32(struct swjdp_common *swjdp,
+int mem_ap_read_buf_u32(struct adiv5_dap *swjdp,
uint8_t *buffer, int count, uint32_t address);
-int mem_ap_write_buf_u8(struct swjdp_common *swjdp,
+int mem_ap_write_buf_u8(struct adiv5_dap *swjdp,
uint8_t *buffer, int count, uint32_t address);
-int mem_ap_write_buf_u16(struct swjdp_common *swjdp,
+int mem_ap_write_buf_u16(struct adiv5_dap *swjdp,
uint8_t *buffer, int count, uint32_t address);
-int mem_ap_write_buf_u32(struct swjdp_common *swjdp,
+int mem_ap_write_buf_u32(struct adiv5_dap *swjdp,
uint8_t *buffer, int count, uint32_t address);
/* Initialisation of the debug system, power domains and registers */
-int ahbap_debugport_init(struct swjdp_common *swjdp);
+int ahbap_debugport_init(struct adiv5_dap *swjdp);
/* Commands for user dap access */
int dap_info_command(struct command_context *cmd_ctx,
- struct swjdp_common *swjdp, int apsel);
+ struct adiv5_dap *swjdp, int apsel);
#define DAP_COMMAND_HANDLER(name) \
- COMMAND_HELPER(name, struct swjdp_common *swjdp)
+ COMMAND_HELPER(name, struct adiv5_dap *swjdp)
DAP_COMMAND_HANDLER(dap_baseaddr_command);
DAP_COMMAND_HANDLER(dap_memaccess_command);
DAP_COMMAND_HANDLER(dap_apsel_command);
diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index fe87fee..92a373a 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -121,7 +121,7 @@ COMMAND_HANDLER(handle_dap_baseaddr_command)
{
struct target *target = get_current_target(CMD_CTX);
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7a->swjdp_info;
return CALL_COMMAND_HANDLER(dap_baseaddr_command, swjdp);
}
@@ -130,7 +130,7 @@ COMMAND_HANDLER(handle_dap_memaccess_command)
{
struct target *target = get_current_target(CMD_CTX);
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7a->swjdp_info;
return CALL_COMMAND_HANDLER(dap_memaccess_command, swjdp);
}
@@ -139,7 +139,7 @@ COMMAND_HANDLER(handle_dap_apsel_command)
{
struct target *target = get_current_target(CMD_CTX);
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7a->swjdp_info;
return CALL_COMMAND_HANDLER(dap_apsel_command, swjdp);
}
@@ -148,7 +148,7 @@ COMMAND_HANDLER(handle_dap_apid_command)
{
struct target *target = get_current_target(CMD_CTX);
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7a->swjdp_info;
return CALL_COMMAND_HANDLER(dap_apid_command, swjdp);
}
@@ -157,7 +157,7 @@ COMMAND_HANDLER(handle_dap_info_command)
{
struct target *target = get_current_target(CMD_CTX);
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7a->swjdp_info;
uint32_t apsel;
switch (CMD_ARGC) {
diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 581813a..70a2d9e 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -51,7 +51,7 @@ struct armv7a_common
struct reg_cache *core_cache;
/* arm adp debug port */
- struct swjdp_common swjdp_info;
+ struct adiv5_dap swjdp_info;
/* Core Debug Unit */
struct arm_dpm dpm;
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index 65e03bf..5276af8 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -755,7 +755,7 @@ COMMAND_HANDLER(handle_dap_baseaddr_command)
{
struct target *target = get_current_target(CMD_CTX);
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct swjdp_common *swjdp = &armv7m->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7m->swjdp_info;
if (!is_armv7m(armv7m)) {
command_print(CMD_CTX, "current target isn't an ARM7-M");
@@ -773,7 +773,7 @@ COMMAND_HANDLER(handle_dap_apid_command)
{
struct target *target = get_current_target(CMD_CTX);
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct swjdp_common *swjdp = &armv7m->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7m->swjdp_info;
if (!is_armv7m(armv7m)) {
command_print(CMD_CTX, "current target isn't an ARM7-M");
@@ -787,7 +787,7 @@ COMMAND_HANDLER(handle_dap_apsel_command)
{
struct target *target = get_current_target(CMD_CTX);
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct swjdp_common *swjdp = &armv7m->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7m->swjdp_info;
if (!is_armv7m(armv7m)) {
command_print(CMD_CTX, "current target isn't an ARM7-M");
@@ -801,7 +801,7 @@ COMMAND_HANDLER(handle_dap_memaccess_command)
{
struct target *target = get_current_target(CMD_CTX);
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct swjdp_common *swjdp = &armv7m->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7m->swjdp_info;
if (!is_armv7m(armv7m)) {
command_print(CMD_CTX, "current target isn't an ARM7-M");
@@ -816,7 +816,7 @@ COMMAND_HANDLER(handle_dap_info_command)
{
struct target *target = get_current_target(CMD_CTX);
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct swjdp_common *swjdp = &armv7m->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7m->swjdp_info;
uint32_t apsel;
if (!is_armv7m(armv7m)) {
diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index 89c5064..5526505 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -106,7 +106,7 @@ struct armv7m_common
struct reg_cache *core_cache;
enum armv7m_mode core_mode;
int exception_number;
- struct swjdp_common swjdp_info;
+ struct adiv5_dap swjdp_info;
uint32_t demcr;
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index f4818f8..0dc7cee 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -67,7 +67,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
static int cortex_a8_init_debug_access(struct target *target)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7a->swjdp_info;
int retval;
uint32_t dummy;
@@ -103,7 +103,7 @@ static int cortex_a8_exec_opcode(struct target *target,
uint32_t dscr;
int retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7a->swjdp_info;
dscr = dscr_p ? *dscr_p : 0;
@@ -150,7 +150,7 @@ static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t addre
{
int retval = ERROR_OK;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7a->swjdp_info;
cortex_a8_dap_read_coreregister_u32(target, regfile, 0);
cortex_a8_dap_write_coreregister_u32(target, address, 0);
@@ -169,7 +169,7 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target,
uint8_t reg = regnum&0xFF;
uint32_t dscr = 0;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7a->swjdp_info;
if (reg > 17)
return retval;
@@ -221,7 +221,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
uint8_t Rd = regnum&0xFF;
uint32_t dscr;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7a->swjdp_info;
LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value);
@@ -284,7 +284,7 @@ static int cortex_a8_dap_write_memap_register_u32(struct target *target, uint32_
{
int retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7a->swjdp_info;
retval = mem_ap_write_atomic_u32(swjdp, address, value);
@@ -317,7 +317,7 @@ static int cortex_a8_write_dcc(struct cortex_a8_common *a8, uint32_t data)
static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data,
uint32_t *dscr_p)
{
- struct swjdp_common *swjdp = &a8->armv7a_common.swjdp_info;
+ struct adiv5_dap *swjdp = &a8->armv7a_common.swjdp_info;
uint32_t dscr = DSCR_INSTR_COMP;
int retval;
@@ -344,7 +344,7 @@ static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data,
static int cortex_a8_dpm_prepare(struct arm_dpm *dpm)
{
struct cortex_a8_common *a8 = dpm_to_a8(dpm);
- struct swjdp_common *swjdp = &a8->armv7a_common.swjdp_info;
+ struct adiv5_dap *swjdp = &a8->armv7a_common.swjdp_info;
uint32_t dscr;
int retval;
@@ -562,7 +562,7 @@ static int cortex_a8_poll(struct target *target)
uint32_t dscr;
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7a->swjdp_info;
enum target_state prev_target_state = target->state;
uint8_t saved_apsel = dap_ap_get_select(swjdp);
@@ -626,7 +626,7 @@ static int cortex_a8_halt(struct target *target)
int retval = ERROR_OK;
uint32_t dscr;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7a->swjdp_info;
uint8_t saved_apsel = dap_ap_get_select(swjdp);
dap_ap_select(swjdp, swjdp_debugap);
@@ -664,7 +664,7 @@ static int cortex_a8_resume(struct target *target, int current,
{
struct armv7a_common *armv7a = target_to_armv7a(target);
struct arm *armv4_5 = &armv7a->armv4_5_common;
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7a->swjdp_info;
// struct breakpoint *breakpoint = NULL;
uint32_t resume_pc, dscr;
@@ -788,7 +788,7 @@ static int cortex_a8_debug_entry(struct target *target)
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
struct armv7a_common *armv7a = target_to_armv7a(target);
struct arm *armv4_5 = &armv7a->armv4_5_common;
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7a->swjdp_info;
struct reg *reg;
LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
@@ -1276,7 +1276,7 @@ static int cortex_a8_read_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7a->swjdp_info;
int retval = ERROR_INVALID_ARGUMENTS;
/* cortex_a8 handles unaligned memory access */
@@ -1304,7 +1304,7 @@ static int cortex_a8_write_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7a->swjdp_info;
int retval = ERROR_INVALID_ARGUMENTS;
// ??? dap_ap_select(swjdp, swjdp_memoryap);
@@ -1386,7 +1386,7 @@ static int cortex_a8_bulk_write_memory(struct target *target, uint32_t address,
}
-static int cortex_a8_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_t *ctrl)
+static int cortex_a8_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t *ctrl)
{
#if 0
u16 dcrdr;
@@ -1413,7 +1413,7 @@ static int cortex_a8_handle_target_request(void *priv)
{
struct target *target = priv;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7a->swjdp_info;
if (!target_was_examined(target))
return ERROR_OK;
@@ -1455,7 +1455,7 @@ static int cortex_a8_examine_first(struct target *target)
{
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7a->swjdp_info;
int i;
int retval = ERROR_OK;
uint32_t didr, ctypr, ttypr, cpuid;
@@ -1562,7 +1562,7 @@ static int cortex_a8_init_arch_info(struct target *target,
{
struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
struct arm *armv4_5 = &armv7a->armv4_5_common;
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7a->swjdp_info;
/* Setup struct cortex_a8_common */
cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC;
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 3178ce3..852965c 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -59,7 +59,7 @@ static void cortex_m3_enable_watchpoints(struct target *target);
static int cortex_m3_store_core_reg_u32(struct target *target,
enum armv7m_regtype type, uint32_t num, uint32_t value);
-static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp,
+static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap *swjdp,
uint32_t *value, int regnum)
{
int retval;
@@ -94,7 +94,7 @@ static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp,
return retval;
}
-static int cortexm3_dap_write_coreregister_u32(struct swjdp_common *swjdp,
+static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap *swjdp,
uint32_t value, int regnum)
{
int retval;
@@ -129,7 +129,7 @@ static int cortex_m3_write_debug_halt_mask(struct target *target,
uint32_t mask_on, uint32_t mask_off)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
- struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
+ struct adiv5_dap *swjdp = &cortex_m3->armv7m.swjdp_info;
/* mask off status bits */
cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
@@ -142,7 +142,7 @@ static int cortex_m3_write_debug_halt_mask(struct target *target,
static int cortex_m3_clear_halt(struct target *target)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
- struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
+ struct adiv5_dap *swjdp = &cortex_m3->armv7m.swjdp_info;
/* clear step if any */
cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
@@ -160,7 +160,7 @@ static int cortex_m3_clear_halt(struct target *target)
static int cortex_m3_single_step_core(struct target *target)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
- struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
+ struct adiv5_dap *swjdp = &cortex_m3->armv7m.swjdp_info;
uint32_t dhcsr_save;
/* backup dhcsr reg */
@@ -191,7 +191,7 @@ static int cortex_m3_endreset_event(struct target *target)
uint32_t dcb_demcr;
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct armv7m_common *armv7m = &cortex_m3->armv7m;
- struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
+ struct adiv5_dap *swjdp = &cortex_m3->armv7m.swjdp_info;
struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list;
struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list;
@@ -286,7 +286,7 @@ static int cortex_m3_examine_exception_reason(struct target *target)
{
uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1;
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct swjdp_common *swjdp = &armv7m->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7m->swjdp_info;
int retval;
mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
@@ -360,7 +360,7 @@ static int cortex_m3_debug_entry(struct target *target)
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct armv7m_common *armv7m = &cortex_m3->armv7m;
struct arm *arm = &armv7m->arm;
- struct swjdp_common *swjdp = &armv7m->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7m->swjdp_info;
struct reg *r;
LOG_DEBUG(" ");
@@ -452,7 +452,7 @@ static int cortex_m3_poll(struct target *target)
int retval;
enum target_state prev_target_state = target->state;
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
- struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
+ struct adiv5_dap *swjdp = &cortex_m3->armv7m.swjdp_info;
/* Read from Debug Halting Control and Status Register */
retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
@@ -587,7 +587,7 @@ static int cortex_m3_halt(struct target *target)
static int cortex_m3_soft_reset_halt(struct target *target)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
- struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
+ struct adiv5_dap *swjdp = &cortex_m3->armv7m.swjdp_info;
uint32_t dcb_dhcsr = 0;
int retval, timeout = 0;
@@ -761,7 +761,7 @@ static int cortex_m3_step(struct target *target, int current,
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct armv7m_common *armv7m = &cortex_m3->armv7m;
- struct swjdp_common *swjdp = &armv7m->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7m->swjdp_info;
struct breakpoint *breakpoint = NULL;
struct reg *pc = armv7m->arm.pc;
bool bkpt_inst_found = false;
@@ -826,7 +826,7 @@ static int cortex_m3_step(struct target *target, int current,
static int cortex_m3_assert_reset(struct target *target)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
- struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
+ struct adiv5_dap *swjdp = &cortex_m3->armv7m.swjdp_info;
int assert_srst = 1;
LOG_DEBUG("target->state: %s",
@@ -1376,7 +1376,7 @@ static int cortex_m3_load_core_reg_u32(struct target *target,
{
int retval;
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct swjdp_common *swjdp = &armv7m->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7m->swjdp_info;
/* NOTE: we "know" here that the register identifiers used
* in the v7m header match the Cortex-M3 Debug Core Register
@@ -1440,7 +1440,7 @@ static int cortex_m3_store_core_reg_u32(struct target *target,
int retval;
uint32_t reg;
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct swjdp_common *swjdp = &armv7m->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7m->swjdp_info;
#ifdef ARMV7_GDB_HACKS
/* If the LR register is being modified, make sure it will put us
@@ -1518,7 +1518,7 @@ static int cortex_m3_read_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct swjdp_common *swjdp = &armv7m->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7m->swjdp_info;
int retval = ERROR_INVALID_ARGUMENTS;
/* cortex_m3 handles unaligned memory access */
@@ -1543,7 +1543,7 @@ static int cortex_m3_write_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct swjdp_common *swjdp = &armv7m->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7m->swjdp_info;
int retval = ERROR_INVALID_ARGUMENTS;
if (count && buffer) {
@@ -1724,7 +1724,7 @@ static int cortex_m3_examine(struct target *target)
uint32_t cpuid, fpcr;
int i;
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
- struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
+ struct adiv5_dap *swjdp = &cortex_m3->armv7m.swjdp_info;
if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK)
return retval;
@@ -1773,7 +1773,7 @@ static int cortex_m3_examine(struct target *target)
return ERROR_OK;
}
-static int cortex_m3_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_t *ctrl)
+static int cortex_m3_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t *ctrl)
{
uint16_t dcrdr;
@@ -1798,7 +1798,7 @@ static int cortex_m3_target_request_data(struct target *target,
uint32_t size, uint8_t *buffer)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct swjdp_common *swjdp = &armv7m->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7m->swjdp_info;
uint8_t data;
uint8_t ctrl;
uint32_t i;
@@ -1818,7 +1818,7 @@ static int cortex_m3_handle_target_request(void *priv)
if (!target_was_examined(target))
return ERROR_OK;
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct swjdp_common *swjdp = &armv7m->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7m->swjdp_info;
if (!target->dbg_msg_enabled)
return ERROR_OK;
@@ -1936,7 +1936,7 @@ COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
struct target *target = get_current_target(CMD_CTX);
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct armv7m_common *armv7m = &cortex_m3->armv7m;
- struct swjdp_common *swjdp = &armv7m->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7m->swjdp_info;
uint32_t demcr = 0;
int retval;
-----------------------------------------------------------------------
Summary of changes:
src/target/arm_adi_v5.c | 64 +++++++++++++++++++++++-----------------------
src/target/arm_adi_v5.h | 64 ++++++++++++++++++++++------------------------
src/target/armv7a.c | 10 +++---
src/target/armv7a.h | 2 +-
src/target/armv7m.c | 10 +++---
src/target/armv7m.h | 2 +-
src/target/cortex_a8.c | 36 +++++++++++++-------------
src/target/cortex_m3.c | 42 +++++++++++++++---------------
8 files changed, 114 insertions(+), 116 deletions(-)
hooks/post-receive
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Main OpenOCD repository
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