[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-935-gc86a64d

[David B. <dbr...@us...>]

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- Log -----------------------------------------------------------------
commit c86a64dff7e9ebe8ab87e353f5b4156f830a0de7
Author: David Brownell <dbr...@us...>
Date:   Mon Dec 14 16:29:53 2009 -0800

    lm3748: use new Stellaris config file
    
    Use the new file, and remove the old target/lm3s3748.cfg one.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/tcl/board/ek-lm3s3748.cfg b/tcl/board/ek-lm3s3748.cfg
index 1d56c7f..950e511 100644
--- a/tcl/board/ek-lm3s3748.cfg
+++ b/tcl/board/ek-lm3s3748.cfg
@@ -4,10 +4,7 @@
 # NOTE:  to use the on-board FT2232 JTAG interface:
 #  source [find interface/luminary.cfg]
 
-source [find target/lm3s3748.cfg]
-
-# LM3S parts don't support RTCK
-jtag_khz 500
+source [find target/stellaris.cfg]
 
 # Board has only srst
 reset_config srst_only
diff --git a/tcl/target/lm3s3748.cfg b/tcl/target/lm3s3748.cfg
deleted file mode 100644
index 274377a..0000000
--- a/tcl/target/lm3s3748.cfg
+++ /dev/null
@@ -1,29 +0,0 @@
-# TI/Luminary Stellaris lm3s3748
-
-if { [info exists CHIPNAME] } {
-   set  _CHIPNAME $CHIPNAME
-} else {
-   set  _CHIPNAME lm3s3748
-}
-
-if { [info exists CPUTAPID ] } {
-   set _CPUTAPID $CPUTAPID
-} else {
-   set _CPUTAPID 0x3ba00477
-}
-
-# JTAG scan chain
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0xf -expected-id $_CPUTAPID
-
-# The "lm3s" variant works around an erratum when using Rev A of "DustDevil"
-# parts (third generation, includes LM3S3748).  It keeps the debug registers
-# from being cleared, by using software reset not SRST; NOP on newer revs.
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu -variant lm3s
-
-# 8k working area at base of ram, not backed up
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x2000
-
-# flash configuration -- one bank of 128K
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME

commit a1009509fb0fc187243435a0f38ef327e2aac147
Author: Yegor Yefremov <yeg...@go...>
Date:   Mon Dec 14 16:29:31 2009 -0800

    Common target file for Stellaris chips
    
    Common target.cfg file for LM3S CPU family
    
    [dbr...@us...: rename, generalize more]
    
    Signed-off-by: Yegor Yefremov <yeg...@go...>
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/tcl/target/stellaris.cfg b/tcl/target/stellaris.cfg
new file mode 100644
index 0000000..6fafac9
--- /dev/null
+++ b/tcl/target/stellaris.cfg
@@ -0,0 +1,49 @@
+# TI/Luminary Stellaris LM3S chip family
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME lm3s
+}
+
+# CPU TAP ID 0x1ba00477 for early Sandstorm parts
+# CPU TAP ID 0x2ba00477 for later SandStorm parts, e.g. lm3s811 Rev C2
+# CPU TAP ID 0x3ba00477 for Cortex-M3 r1p2 (on Fury, DustDevil)
+# CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest)
+# ... we'll ignore the JTAG version field, rather than list every
+# chip revision that turns up.
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x0ba00477
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -irmask 0xf \
+	-expected-id $_CPUTAPID -ignore-version
+
+# The "lm3s" variant uses a software reset rather than SRST.
+# This stops the debug registers from being cleared; it works
+# around an erratum which should be fixed in later silicon.
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu \
+	-variant lm3s
+
+# 8K working area at base of ram, not backed up
+#
+# NOTE:  you may need or want to reconfigure the work area;
+# some parts have just 6K, and you may want to use other
+# addresses (at end of mem not beginning) or back it up.
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x2000
+
+# JTAG speed ... slow enough to work with a 12 MHz RC oscillator;
+# LM3S parts don't support RTCK
+#
+# NOTE:  this may be increased by a reset-init handler, after it
+# configures and enables the PLL.  Or you might need to decrease
+# this, if you're using a slower clock.
+jtag_khz 500
+$_TARGETNAME configure -event reset-start {jtag_khz 500}
+
+# flash configuration ... autodetects sizes, autoprobed
+flash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME
+

-----------------------------------------------------------------------

Summary of changes:
 tcl/board/ek-lm3s3748.cfg |    5 +---
 tcl/target/lm3s3748.cfg   |   29 --------------------------
 tcl/target/stellaris.cfg  |   49 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 50 insertions(+), 33 deletions(-)
 delete mode 100644 tcl/target/lm3s3748.cfg
 create mode 100644 tcl/target/stellaris.cfg


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