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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-877-gaf1d759
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From: David B. <dbr...@us...> - 2009-12-05 05:51:14
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commit af1d7590edf04077aa8f22fba9097e0c68431f68
Author: David Brownell <dbr...@us...>
Date: Fri Dec 4 20:44:29 2009 -0800
ARM: doc updates for main header
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 56461e7..a93087e 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -30,7 +30,8 @@
#include <helper/command.h>
-/* These numbers match the five low bits of the *PSR registers on
+/**
+ * These numbers match the five low bits of the *PSR registers on
* "classic ARM" processors, which build on the ARMv4 processor
* modes and register set.
*/
@@ -49,7 +50,7 @@ enum arm_mode {
const char *arm_mode_name(unsigned psr_mode);
bool is_arm_mode(unsigned psr_mode);
-/* The PSR "T" and "J" bits define the mode of "classic ARM" cores */
+/** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
enum arm_state {
ARM_STATE_ARM,
ARM_STATE_THUMB,
@@ -95,6 +96,7 @@ struct arm
/** Handle to the SPSR; valid only in core modes with an SPSR. */
struct reg *spsr;
+ /** Support for arm_reg_current() */
const int *map;
/**
@@ -105,7 +107,10 @@ struct arm
*/
enum arm_mode core_type;
+ /** Record the current core mode: SVC, USR, or some other mode. */
enum arm_mode core_mode;
+
+ /** Record the current core state: ARM, Thumb, or otherwise. */
enum arm_state core_state;
/** Flag reporting unavailability of the BKPT instruction. */
@@ -128,7 +133,10 @@ struct arm
/* FIXME all these methods should take "struct arm *" not target */
+ /** Retrieve all core registers, for display. */
int (*full_context)(struct target *target);
+
+ /** Retrieve a single core register. */
int (*read_core_reg)(struct target *target, struct reg *reg,
int num, enum arm_mode mode);
int (*write_core_reg)(struct target *target, struct reg *reg,
@@ -140,7 +148,7 @@ struct arm
uint32_t CRn, uint32_t CRm,
uint32_t *value);
- /* Write coprocessor register. */
+ /** Write coprocessor register. */
int (*mcr)(struct target *target, int cpnum,
uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm,
commit 3edcff8b8efff841dfe601e87f42de7fe7b4792b
Author: David Brownell <dbr...@us...>
Date: Fri Dec 4 20:33:02 2009 -0800
ARM: rename armv4_5_build_reg_cache() as arm_*()
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c
index a0b12b9..fffc632 100644
--- a/src/target/arm7tdmi.c
+++ b/src/target/arm7tdmi.c
@@ -643,7 +643,7 @@ static void arm7tdmi_build_reg_cache(struct target *target)
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct arm *armv4_5 = target_to_arm(target);
- (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
+ (*cache_p) = arm_build_reg_cache(target, armv4_5);
}
int arm7tdmi_init_target(struct command_context *cmd_ctx, struct target *target)
diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c
index 10f88f7..09199c7 100644
--- a/src/target/arm9tdmi.c
+++ b/src/target/arm9tdmi.c
@@ -753,7 +753,7 @@ static void arm9tdmi_build_reg_cache(struct target *target)
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct arm *armv4_5 = target_to_arm(target);
- (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
+ (*cache_p) = arm_build_reg_cache(target, armv4_5);
}
int arm9tdmi_init_target(struct command_context *cmd_ctx,
diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index b65e922..ff89c47 100644
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -819,7 +819,7 @@ int arm_dpm_setup(struct arm_dpm *dpm)
arm->read_core_reg = arm_dpm_read_core_reg;
arm->write_core_reg = arm_dpm_write_core_reg;
- cache = armv4_5_build_reg_cache(target, arm);
+ cache = arm_build_reg_cache(target, arm);
if (!cache)
return ERROR_FAIL;
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index e07f606..ad89b2f 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -533,7 +533,7 @@ static const struct reg_arch_type arm_reg_type = {
.set = armv4_5_set_core_reg,
};
-struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *armv4_5_common)
+struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
{
int num_regs = ARRAY_SIZE(arm_core_regs);
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
@@ -557,7 +557,7 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm
{
/* Skip registers this core doesn't expose */
if (arm_core_regs[i].mode == ARM_MODE_MON
- && armv4_5_common->core_type != ARM_MODE_MON)
+ && arm->core_type != ARM_MODE_MON)
continue;
/* REVISIT handle Cortex-M, which only shadows R13/SP */
@@ -565,7 +565,7 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm
arch_info[i].num = arm_core_regs[i].cookie;
arch_info[i].mode = arm_core_regs[i].mode;
arch_info[i].target = target;
- arch_info[i].armv4_5_common = armv4_5_common;
+ arch_info[i].armv4_5_common = arm;
reg_list[i].name = (char *) arm_core_regs[i].name;
reg_list[i].size = 32;
@@ -576,8 +576,8 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm
cache->num_regs++;
}
- armv4_5_common->cpsr = reg_list + ARMV4_5_CPSR;
- armv4_5_common->core_cache = cache;
+ arm->cpsr = reg_list + ARMV4_5_CPSR;
+ arm->core_cache = cache;
return cache;
}
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 0b28301..56461e7 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -177,8 +177,7 @@ struct arm_reg
uint32_t value;
};
-struct reg_cache* armv4_5_build_reg_cache(struct target *target,
- struct arm *armv4_5_common);
+struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
int armv4_5_arch_state(struct target *target);
int armv4_5_get_gdb_reg_list(struct target *target,
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 352e159..d5b1d63 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -2859,7 +2859,7 @@ static void xscale_build_reg_cache(struct target *target)
int i;
int num_regs = ARRAY_SIZE(xscale_reg_arch_info);
- (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
+ (*cache_p) = arm_build_reg_cache(target, armv4_5);
(*cache_p)->next = malloc(sizeof(struct reg_cache));
cache_p = &(*cache_p)->next;
commit c2cc677056f8b383ff8f88ed8a16f1aa4b530ae2
Author: David Brownell <dbr...@us...>
Date: Fri Dec 4 20:19:49 2009 -0800
ARM: rename armv4_5_algorithm as arm_algorithm
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/flash/arm_nandio.c b/src/flash/arm_nandio.c
index 12c4b2f..67619d5 100644
--- a/src/flash/arm_nandio.c
+++ b/src/flash/arm_nandio.c
@@ -93,7 +93,7 @@ int arm_code_to_working_area(struct target *target,
int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size)
{
struct target *target = nand->target;
- struct armv4_5_algorithm algo;
+ struct arm_algorithm algo;
struct arm *armv4_5 = target->arch_info;
struct reg_param reg_params[3];
uint32_t target_buf;
@@ -177,7 +177,7 @@ int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size)
int arm_nandread(struct arm_nand_data *nand, uint8_t *data, uint32_t size)
{
struct target *target = nand->target;
- struct armv4_5_algorithm algo;
+ struct arm_algorithm algo;
struct arm *armv4_5 = target->arch_info;
struct reg_param reg_params[3];
uint32_t target_buf;
diff --git a/src/flash/nor/aduc702x.c b/src/flash/nor/aduc702x.c
index de362cb..57018bb 100644
--- a/src/flash/nor/aduc702x.c
+++ b/src/flash/nor/aduc702x.c
@@ -165,7 +165,7 @@ static int aduc702x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32
struct working_area *source;
uint32_t address = bank->base + offset;
struct reg_param reg_params[6];
- struct armv4_5_algorithm armv4_5_info;
+ struct arm_algorithm armv4_5_info;
int retval = ERROR_OK;
if (((count%2)!=0)||((offset%2)!=0))
diff --git a/src/flash/nor/cfi.c b/src/flash/nor/cfi.c
index cffc22a..1ab9341 100644
--- a/src/flash/nor/cfi.c
+++ b/src/flash/nor/cfi.c
@@ -1012,7 +1012,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer, uint3
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct target *target = bank->target;
struct reg_param reg_params[7];
- struct armv4_5_algorithm armv4_5_info;
+ struct arm_algorithm armv4_5_info;
struct working_area *source;
uint32_t buffer_size = 32768;
uint32_t write_command_val, busy_pattern_val, error_pattern_val;
@@ -1257,7 +1257,7 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, ui
struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
struct target *target = bank->target;
struct reg_param reg_params[10];
- struct armv4_5_algorithm armv4_5_info;
+ struct arm_algorithm armv4_5_info;
struct working_area *source;
uint32_t buffer_size = 32768;
uint32_t status;
diff --git a/src/flash/nor/ecos.c b/src/flash/nor/ecos.c
index b216903..b51e0a0 100644
--- a/src/flash/nor/ecos.c
+++ b/src/flash/nor/ecos.c
@@ -209,7 +209,7 @@ static int runCode(struct ecosflash_flash_bank *info,
struct target *target = info->target;
struct reg_param reg_params[3];
- struct armv4_5_algorithm armv4_5_info;
+ struct arm_algorithm armv4_5_info;
armv4_5_info.common_magic = ARM_COMMON_MAGIC;
armv4_5_info.core_mode = ARM_MODE_SVC;
armv4_5_info.core_state = ARM_STATE_ARM;
diff --git a/src/flash/nor/lpc2000.c b/src/flash/nor/lpc2000.c
index 6888b76..0caf3e0 100644
--- a/src/flash/nor/lpc2000.c
+++ b/src/flash/nor/lpc2000.c
@@ -242,7 +242,7 @@ static int lpc2000_iap_call(struct flash_bank *bank, int code, uint32_t param_ta
struct target *target = bank->target;
struct mem_param mem_params[2];
struct reg_param reg_params[5];
- struct armv4_5_algorithm armv4_5_info; /* for LPC2000 */
+ struct arm_algorithm armv4_5_info; /* for LPC2000 */
struct armv7m_algorithm armv7m_info; /* for LPC1700 */
uint32_t status_code;
uint32_t iap_entry_point = 0; /* to make compiler happier */
diff --git a/src/flash/nor/lpc2900.c b/src/flash/nor/lpc2900.c
index 1ef759e..ce74bbb 100644
--- a/src/flash/nor/lpc2900.c
+++ b/src/flash/nor/lpc2900.c
@@ -1302,7 +1302,7 @@ static int lpc2900_write(struct flash_bank *bank, uint8_t *buffer,
if( warea )
{
struct reg_param reg_params[5];
- struct armv4_5_algorithm armv4_5_info;
+ struct arm_algorithm armv4_5_info;
/* We can use target mode. Download the algorithm. */
retval = target_write_buffer( target,
diff --git a/src/flash/nor/str7x.c b/src/flash/nor/str7x.c
index 45aa657..ef693e9 100644
--- a/src/flash/nor/str7x.c
+++ b/src/flash/nor/str7x.c
@@ -318,7 +318,7 @@ static int str7x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t
struct working_area *source;
uint32_t address = bank->base + offset;
struct reg_param reg_params[6];
- struct armv4_5_algorithm armv4_5_info;
+ struct arm_algorithm armv4_5_info;
int retval = ERROR_OK;
uint32_t str7x_flash_write_code[] = {
diff --git a/src/flash/nor/str9x.c b/src/flash/nor/str9x.c
index 95da3e2..9cddb50 100644
--- a/src/flash/nor/str9x.c
+++ b/src/flash/nor/str9x.c
@@ -356,7 +356,7 @@ static int str9x_write_block(struct flash_bank *bank,
struct working_area *source;
uint32_t address = bank->base + offset;
struct reg_param reg_params[4];
- struct armv4_5_algorithm armv4_5_info;
+ struct arm_algorithm armv4_5_info;
int retval = ERROR_OK;
uint32_t str9x_flash_write_code[] = {
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 68005c0..25f8cb3 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -2693,7 +2693,7 @@ int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t c
}
}
- struct armv4_5_algorithm armv4_5_info;
+ struct arm_algorithm armv4_5_info;
struct reg_param reg_params[1];
armv4_5_info.common_magic = ARM_COMMON_MAGIC;
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 6941c16..e07f606 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -1037,7 +1037,7 @@ int armv4_5_run_algorithm_inner(struct target *target,
int timeout_ms, void *arch_info))
{
struct arm *armv4_5 = target_to_arm(target);
- struct armv4_5_algorithm *armv4_5_algorithm_info = arch_info;
+ struct arm_algorithm *arm_algorithm_info = arch_info;
enum arm_state core_state = armv4_5->core_state;
uint32_t context[17];
uint32_t cpsr;
@@ -1047,7 +1047,7 @@ int armv4_5_run_algorithm_inner(struct target *target,
LOG_DEBUG("Running algorithm");
- if (armv4_5_algorithm_info->common_magic != ARM_COMMON_MAGIC)
+ if (arm_algorithm_info->common_magic != ARM_COMMON_MAGIC)
{
LOG_ERROR("current target isn't an ARMV4/5 target");
return ERROR_TARGET_INVALID;
@@ -1077,10 +1077,10 @@ int armv4_5_run_algorithm_inner(struct target *target,
struct reg *r;
r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5_algorithm_info->core_mode, i);
+ arm_algorithm_info->core_mode, i);
if (!r->valid)
armv4_5->read_core_reg(target, r, i,
- armv4_5_algorithm_info->core_mode);
+ arm_algorithm_info->core_mode);
context[i] = buf_get_u32(r->value, 0, 32);
}
cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
@@ -1114,7 +1114,7 @@ int armv4_5_run_algorithm_inner(struct target *target,
}
}
- armv4_5->core_state = armv4_5_algorithm_info->core_state;
+ armv4_5->core_state = arm_algorithm_info->core_state;
if (armv4_5->core_state == ARM_STATE_ARM)
exit_breakpoint_size = 4;
else if (armv4_5->core_state == ARM_STATE_THUMB)
@@ -1125,12 +1125,12 @@ int armv4_5_run_algorithm_inner(struct target *target,
return ERROR_INVALID_ARGUMENTS;
}
- if (armv4_5_algorithm_info->core_mode != ARM_MODE_ANY)
+ if (arm_algorithm_info->core_mode != ARM_MODE_ANY)
{
LOG_DEBUG("setting core_mode: 0x%2.2x",
- armv4_5_algorithm_info->core_mode);
+ arm_algorithm_info->core_mode);
buf_set_u32(armv4_5->cpsr->value, 0, 5,
- armv4_5_algorithm_info->core_mode);
+ arm_algorithm_info->core_mode);
armv4_5->cpsr->dirty = 1;
armv4_5->cpsr->valid = 1;
}
@@ -1193,13 +1193,13 @@ int armv4_5_run_algorithm_inner(struct target *target,
for (i = 0; i <= 16; i++)
{
uint32_t regvalue;
- regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32);
+ regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, arm_algorithm_info->core_mode, i).value, 0, 32);
if (regvalue != context[i])
{
- LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, context[i]);
- buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32, context[i]);
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid = 1;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1;
+ LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, arm_algorithm_info->core_mode, i).name, context[i]);
+ buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, arm_algorithm_info->core_mode, i).value, 0, 32, context[i]);
+ ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, arm_algorithm_info->core_mode, i).valid = 1;
+ ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, arm_algorithm_info->core_mode, i).dirty = 1;
}
}
@@ -1225,7 +1225,7 @@ int arm_checksum_memory(struct target *target,
uint32_t address, uint32_t count, uint32_t *checksum)
{
struct working_area *crc_algorithm;
- struct armv4_5_algorithm armv4_5_info;
+ struct arm_algorithm armv4_5_info;
struct reg_param reg_params[2];
int retval;
uint32_t i;
@@ -1320,7 +1320,7 @@ int arm_blank_check_memory(struct target *target,
{
struct working_area *check_algorithm;
struct reg_param reg_params[3];
- struct armv4_5_algorithm armv4_5_info;
+ struct arm_algorithm armv4_5_info;
int retval;
uint32_t i;
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index b56a1f1..0b28301 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -160,7 +160,7 @@ static inline bool is_arm(struct arm *arm)
return arm && arm->common_magic == ARM_COMMON_MAGIC;
}
-struct armv4_5_algorithm
+struct arm_algorithm
{
int common_magic;
commit 340e2eb7629fc1fdb6d2ead2952982584abdcefa
Author: David Brownell <dbr...@us...>
Date: Fri Dec 4 20:14:46 2009 -0800
ARM: misc generic cleanup
Remove an undesirable use of the CPSR symbol ... it needs to vanish.
Flag mode-to-number stuff as obsolete; say why ... should also vanish.
Get rid of no-longer-used mode and state typedefs.
Comment a few of the implicit ties to "classic ARM".
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c
index d71fbae..39625f6 100644
--- a/src/target/arm_semihosting.c
+++ b/src/target/arm_semihosting.c
@@ -379,15 +379,22 @@ static int do_semihosting(struct target *target)
}
/* resume execution to the original mode */
+
+ /* return value in R0 */
buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, result);
armv4_5->core_cache->reg_list[0].dirty = 1;
+
+ /* LR --> PC */
buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, lr);
armv4_5->core_cache->reg_list[15].dirty = 1;
- buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, spsr);
- armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
+
+ /* saved PSR --> current PSR */
+ buf_set_u32(armv4_5->cpsr->value, 0, 32, spsr);
+ armv4_5->cpsr->dirty = 1;
armv4_5->core_mode = spsr & 0x1f;
if (spsr & 0x20)
armv4_5->core_state = ARM_STATE_THUMB;
+
return target_resume(target, 1, 0, 0, 0);
}
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 6a082a5..b56a1f1 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -30,8 +30,11 @@
#include <helper/command.h>
-typedef enum arm_mode
-{
+/* These numbers match the five low bits of the *PSR registers on
+ * "classic ARM" processors, which build on the ARMv4 processor
+ * modes and register set.
+ */
+enum arm_mode {
ARM_MODE_USR = 16,
ARM_MODE_FIQ = 17,
ARM_MODE_IRQ = 18,
@@ -41,24 +44,29 @@ typedef enum arm_mode
ARM_MODE_UND = 27,
ARM_MODE_SYS = 31,
ARM_MODE_ANY = -1
-} arm_mode_t;
+};
const char *arm_mode_name(unsigned psr_mode);
bool is_arm_mode(unsigned psr_mode);
-int arm_mode_to_number(enum arm_mode mode);
-enum arm_mode armv4_5_number_to_mode(int number);
-
-typedef enum arm_state
-{
+/* The PSR "T" and "J" bits define the mode of "classic ARM" cores */
+enum arm_state {
ARM_STATE_ARM,
ARM_STATE_THUMB,
ARM_STATE_JAZELLE,
ARM_STATE_THUMB_EE,
-} arm_state_t;
+};
extern const char *arm_state_strings[];
+/* OBSOLETE, DO NOT USE IN NEW CODE! The "number" of an arm_mode is an
+ * index into the armv4_5_core_reg_map array. Its remaining users are
+ * remnants which could as easily walk * the register cache directly as
+ * use the expensive ARMV4_5_CORE_REG_MODE() macro.
+ */
+int arm_mode_to_number(enum arm_mode mode);
+enum arm_mode armv4_5_number_to_mode(int number);
+
extern const int armv4_5_core_reg_map[8][17];
#define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
diff --git a/src/target/etm.h b/src/target/etm.h
index 92df0bf..5aea657 100644
--- a/src/target/etm.h
+++ b/src/target/etm.h
@@ -164,7 +164,7 @@ struct etm_context
uint32_t trace_depth; /* number of cycles to be analyzed, 0 if no data available */
etm_portmode_t portmode; /* normal, multiplexed or demultiplexed */
etmv1_tracemode_t tracemode; /* type of info trace contains */
- int /*arm_state_t*/ core_state; /* current core state */
+ int /*arm_state*/ core_state; /* current core state */
struct image *image; /* source for target opcodes */
uint32_t pipe_index; /* current trace cycle */
uint32_t data_index; /* cycle holding next data packet */
diff --git a/src/target/xscale.h b/src/target/xscale.h
index 2bb2ba5..43edeec 100644
--- a/src/target/xscale.h
+++ b/src/target/xscale.h
@@ -79,7 +79,7 @@ struct xscale_trace
int buffer_fill; /* maximum number of trace runs to read (-1 for wrap-around) */
int pc_ok;
uint32_t current_pc;
- arm_state_t core_state; /* current core state (ARM, Thumb, Jazelle) */
+ enum arm_state core_state; /* current core state (ARM, Thumb) */
};
struct xscale_common
commit e51b9a4ac7afa0fde11690268ba88861e1000f60
Author: David Brownell <dbr...@us...>
Date: Fri Dec 4 19:46:44 2009 -0800
ARM: ARMV4_5_COMMON_MAGIC --> ARM_COMMON_MAGIC
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/flash/arm_nandio.c b/src/flash/arm_nandio.c
index 3991c0f..12c4b2f 100644
--- a/src/flash/arm_nandio.c
+++ b/src/flash/arm_nandio.c
@@ -136,7 +136,7 @@ int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size)
return retval;
/* set up algorithm and parameters */
- algo.common_magic = ARMV4_5_COMMON_MAGIC;
+ algo.common_magic = ARM_COMMON_MAGIC;
algo.core_mode = ARM_MODE_SVC;
algo.core_state = ARM_STATE_ARM;
@@ -212,7 +212,7 @@ int arm_nandread(struct arm_nand_data *nand, uint8_t *data, uint32_t size)
target_buf = nand->copy_area->address + sizeof(code);
/* set up algorithm and parameters */
- algo.common_magic = ARMV4_5_COMMON_MAGIC;
+ algo.common_magic = ARM_COMMON_MAGIC;
algo.core_mode = ARM_MODE_SVC;
algo.core_state = ARM_STATE_ARM;
diff --git a/src/flash/nor/aduc702x.c b/src/flash/nor/aduc702x.c
index 69c8274..de362cb 100644
--- a/src/flash/nor/aduc702x.c
+++ b/src/flash/nor/aduc702x.c
@@ -241,7 +241,7 @@ static int aduc702x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32
}
}
- armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
+ armv4_5_info.common_magic = ARM_COMMON_MAGIC;
armv4_5_info.core_mode = ARM_MODE_SVC;
armv4_5_info.core_state = ARM_STATE_ARM;
diff --git a/src/flash/nor/cfi.c b/src/flash/nor/cfi.c
index 16ba999..cffc22a 100644
--- a/src/flash/nor/cfi.c
+++ b/src/flash/nor/cfi.c
@@ -1085,7 +1085,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer, uint3
cfi_intel_clear_status_register(bank);
- armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
+ armv4_5_info.common_magic = ARM_COMMON_MAGIC;
armv4_5_info.core_mode = ARM_MODE_SVC;
armv4_5_info.core_state = ARM_STATE_ARM;
@@ -1408,7 +1408,7 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, ui
0xeafffffe /* b 8204 <sp_8_done> */
};
- armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
+ armv4_5_info.common_magic = ARM_COMMON_MAGIC;
armv4_5_info.core_mode = ARM_MODE_SVC;
armv4_5_info.core_state = ARM_STATE_ARM;
diff --git a/src/flash/nor/ecos.c b/src/flash/nor/ecos.c
index 2524ae7..b216903 100644
--- a/src/flash/nor/ecos.c
+++ b/src/flash/nor/ecos.c
@@ -210,7 +210,7 @@ static int runCode(struct ecosflash_flash_bank *info,
struct reg_param reg_params[3];
struct armv4_5_algorithm armv4_5_info;
- armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
+ armv4_5_info.common_magic = ARM_COMMON_MAGIC;
armv4_5_info.core_mode = ARM_MODE_SVC;
armv4_5_info.core_state = ARM_STATE_ARM;
diff --git a/src/flash/nor/lpc2000.c b/src/flash/nor/lpc2000.c
index c14df1f..6888b76 100644
--- a/src/flash/nor/lpc2000.c
+++ b/src/flash/nor/lpc2000.c
@@ -292,7 +292,7 @@ static int lpc2000_iap_call(struct flash_bank *bank, int code, uint32_t param_ta
break;
case lpc2000_v1:
case lpc2000_v2:
- armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
+ armv4_5_info.common_magic = ARM_COMMON_MAGIC;
armv4_5_info.core_mode = ARM_MODE_SVC;
armv4_5_info.core_state = ARM_STATE_ARM;
iap_entry_point = 0x7ffffff1;
diff --git a/src/flash/nor/lpc2900.c b/src/flash/nor/lpc2900.c
index aec8bcd..1ef759e 100644
--- a/src/flash/nor/lpc2900.c
+++ b/src/flash/nor/lpc2900.c
@@ -1423,7 +1423,7 @@ static int lpc2900_write(struct flash_bank *bank, uint8_t *buffer,
buf_set_u32(reg_params[4].value, 0, 32, FPTR_EN_T | prog_time);
/* Execute algorithm, assume breakpoint for last instruction */
- armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
+ armv4_5_info.common_magic = ARM_COMMON_MAGIC;
armv4_5_info.core_mode = ARM_MODE_SVC;
armv4_5_info.core_state = ARM_STATE_ARM;
diff --git a/src/flash/nor/str7x.c b/src/flash/nor/str7x.c
index 5767b93..45aa657 100644
--- a/src/flash/nor/str7x.c
+++ b/src/flash/nor/str7x.c
@@ -371,7 +371,7 @@ static int str7x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t
}
}
- armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
+ armv4_5_info.common_magic = ARM_COMMON_MAGIC;
armv4_5_info.core_mode = ARM_MODE_SVC;
armv4_5_info.core_state = ARM_STATE_ARM;
diff --git a/src/flash/nor/str9x.c b/src/flash/nor/str9x.c
index 60367cb..95da3e2 100644
--- a/src/flash/nor/str9x.c
+++ b/src/flash/nor/str9x.c
@@ -408,7 +408,7 @@ static int str9x_write_block(struct flash_bank *bank,
}
}
- armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
+ armv4_5_info.common_magic = ARM_COMMON_MAGIC;
armv4_5_info.core_mode = ARM_MODE_SVC;
armv4_5_info.core_state = ARM_STATE_ARM;
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 408259e..68005c0 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -2696,7 +2696,7 @@ int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t c
struct armv4_5_algorithm armv4_5_info;
struct reg_param reg_params[1];
- armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
+ armv4_5_info.common_magic = ARM_COMMON_MAGIC;
armv4_5_info.core_mode = ARM_MODE_SVC;
armv4_5_info.core_state = ARM_STATE_ARM;
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 4fc8c82..6941c16 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -585,7 +585,7 @@ int armv4_5_arch_state(struct target *target)
{
struct arm *armv4_5 = target_to_arm(target);
- if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
+ if (armv4_5->common_magic != ARM_COMMON_MAGIC)
{
LOG_ERROR("BUG: called for a non-ARM target");
return ERROR_FAIL;
@@ -1047,7 +1047,7 @@ int armv4_5_run_algorithm_inner(struct target *target,
LOG_DEBUG("Running algorithm");
- if (armv4_5_algorithm_info->common_magic != ARMV4_5_COMMON_MAGIC)
+ if (armv4_5_algorithm_info->common_magic != ARM_COMMON_MAGIC)
{
LOG_ERROR("current target isn't an ARMV4/5 target");
return ERROR_TARGET_INVALID;
@@ -1273,7 +1273,7 @@ int arm_checksum_memory(struct target *target,
return retval;
}
- armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
+ armv4_5_info.common_magic = ARM_COMMON_MAGIC;
armv4_5_info.core_mode = ARM_MODE_SVC;
armv4_5_info.core_state = ARM_STATE_ARM;
@@ -1350,7 +1350,7 @@ int arm_blank_check_memory(struct target *target,
return retval;
}
- armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
+ armv4_5_info.common_magic = ARM_COMMON_MAGIC;
armv4_5_info.core_mode = ARM_MODE_SVC;
armv4_5_info.core_state = ARM_STATE_ARM;
@@ -1424,7 +1424,7 @@ int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5)
target->arch_info = armv4_5;
armv4_5->target = target;
- armv4_5->common_magic = ARMV4_5_COMMON_MAGIC;
+ armv4_5->common_magic = ARM_COMMON_MAGIC;
arm_set_cpsr(armv4_5, ARM_MODE_USR);
/* core_type may be overridden by subtype logic */
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 42fbeac..6a082a5 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -67,7 +67,7 @@ extern const int armv4_5_core_reg_map[8][17];
/* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
enum { ARMV4_5_CPSR = 31, };
-#define ARMV4_5_COMMON_MAGIC 0x0A450A45
+#define ARM_COMMON_MAGIC 0x0A450A45
/**
* Represents a generic ARM core, with standard application registers.
@@ -149,7 +149,7 @@ static inline struct arm *target_to_arm(struct target *target)
static inline bool is_arm(struct arm *arm)
{
- return arm && arm->common_magic == ARMV4_5_COMMON_MAGIC;
+ return arm && arm->common_magic == ARM_COMMON_MAGIC;
}
struct armv4_5_algorithm
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 0fa3270..352e159 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -857,7 +857,7 @@ static int xscale_arch_state(struct target *target)
"", "\n(processor reset)", "\n(trace buffer full)"
};
- if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
+ if (armv4_5->common_magic != ARM_COMMON_MAGIC)
{
LOG_ERROR("BUG: called for a non-ARMv4/5 target");
return ERROR_INVALID_ARGUMENTS;
commit 87589043faf8cdb954c602c988698c40fcf9c108
Author: David Brownell <dbr...@us...>
Date: Fri Dec 4 19:43:03 2009 -0800
ARM: switch target_to_armv4_5() to target_to_arm()
And remove that old symbol.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c
index 7d14ed6..a0b12b9 100644
--- a/src/target/arm7tdmi.c
+++ b/src/target/arm7tdmi.c
@@ -641,7 +641,7 @@ static void arm7tdmi_branch_resume_thumb(struct target *target)
static void arm7tdmi_build_reg_cache(struct target *target)
{
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
- struct arm *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_arm(target);
(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
}
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 6a5faff..305f0de 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -212,7 +212,7 @@ static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode,
static int arm920t_read_cp15_interpreted(struct target *target,
uint32_t cp15_opcode, uint32_t address, uint32_t *value)
{
- struct arm *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_arm(target);
uint32_t* regs_p[1];
uint32_t regs[2];
uint32_t cp15c15 = 0x0;
@@ -259,7 +259,7 @@ int arm920t_write_cp15_interpreted(struct target *target,
uint32_t cp15_opcode, uint32_t value, uint32_t address)
{
uint32_t cp15c15 = 0x0;
- struct arm *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_arm(target);
uint32_t regs[2];
struct reg *r = armv4_5->core_cache->reg_list;
diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c
index 7eb5641..10f88f7 100644
--- a/src/target/arm9tdmi.c
+++ b/src/target/arm9tdmi.c
@@ -751,7 +751,7 @@ void arm9tdmi_disable_single_step(struct target *target)
static void arm9tdmi_build_reg_cache(struct target *target)
{
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
- struct arm *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_arm(target);
(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
}
diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c
index dd6a669..d71fbae 100644
--- a/src/target/arm_semihosting.c
+++ b/src/target/arm_semihosting.c
@@ -43,7 +43,7 @@
static int do_semihosting(struct target *target)
{
- struct arm *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_arm(target);
uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
uint32_t r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
uint32_t lr = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, ARM_MODE_SVC, 14).value, 0, 32);
@@ -406,7 +406,7 @@ static int do_semihosting(struct target *target)
*/
int arm_semihosting(struct target *target, int *retval)
{
- struct arm *arm = target_to_armv4_5(target);
+ struct arm *arm = target_to_arm(target);
uint32_t lr, spsr;
struct reg *r;
diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c
index cb1f651..443f29b 100644
--- a/src/target/arm_simulator.c
+++ b/src/target/arm_simulator.c
@@ -850,7 +850,7 @@ static enum arm_mode armv4_5_get_mode(struct arm_sim_interface *sim)
int arm_simulate_step(struct target *target, uint32_t *dry_run_pc)
{
- struct arm *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_arm(target);
struct arm_sim_interface sim;
sim.user_data = armv4_5;
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 102913b..4fc8c82 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -491,7 +491,7 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
{
struct arm_reg *armv4_5 = reg->arch_info;
struct target *target = armv4_5->target;
- struct arm *armv4_5_target = target_to_armv4_5(target);
+ struct arm *armv4_5_target = target_to_arm(target);
uint32_t value = buf_get_u32(buf, 0, 32);
if (target->state != TARGET_HALTED)
@@ -583,7 +583,7 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm
int armv4_5_arch_state(struct target *target)
{
- struct arm *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_arm(target);
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
{
@@ -611,7 +611,7 @@ int armv4_5_arch_state(struct target *target)
COMMAND_HANDLER(handle_armv4_5_reg_command)
{
struct target *target = get_current_target(CMD_CTX);
- struct arm *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_arm(target);
unsigned num_regs;
struct reg *regs;
@@ -698,7 +698,7 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
COMMAND_HANDLER(handle_armv4_5_core_state_command)
{
struct target *target = get_current_target(CMD_CTX);
- struct arm *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_arm(target);
if (!is_arm(armv4_5))
{
@@ -974,7 +974,7 @@ const struct command_registration arm_command_handlers[] = {
int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
{
- struct arm *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_arm(target);
int i;
if (!is_arm_mode(armv4_5->core_mode))
@@ -999,7 +999,7 @@ int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int
static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
{
int retval;
- struct arm *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_arm(target);
if ((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
{
@@ -1036,7 +1036,7 @@ int armv4_5_run_algorithm_inner(struct target *target,
int (*run_it)(struct target *target, uint32_t exit_point,
int timeout_ms, void *arch_info))
{
- struct arm *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_arm(target);
struct armv4_5_algorithm *armv4_5_algorithm_info = arch_info;
enum arm_state core_state = armv4_5->core_state;
uint32_t context[17];
@@ -1388,7 +1388,7 @@ int arm_blank_check_memory(struct target *target,
static int arm_full_context(struct target *target)
{
- struct arm *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_arm(target);
unsigned num_regs = armv4_5->core_cache->num_regs;
struct reg *reg = armv4_5->core_cache->reg_list;
int retval = ERROR_OK;
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 5d58aa3..42fbeac 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -141,8 +141,6 @@ struct arm
void *arch_info;
};
-#define target_to_armv4_5 target_to_arm
-
/** Convert target handle to generic ARM target state handle. */
static inline struct arm *target_to_arm(struct target *target)
{
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 253decb..0fa3270 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -1429,7 +1429,7 @@ static int xscale_step_inner(struct target *target, int current,
static int xscale_step(struct target *target, int current,
uint32_t address, int handle_breakpoints)
{
- struct arm *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_arm(target);
struct breakpoint *breakpoint = target->breakpoints;
uint32_t current_pc;
@@ -1675,7 +1675,7 @@ static int xscale_write_core_reg(struct target *target, struct reg *r,
static int xscale_full_context(struct target *target)
{
- struct arm *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_arm(target);
uint32_t *buffer;
@@ -1757,7 +1757,7 @@ static int xscale_full_context(struct target *target)
static int xscale_restore_banked(struct target *target)
{
- struct arm *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_arm(target);
int i, j;
commit 56e01714203406b50b40dd7738983e3b019d4df2
Author: David Brownell <dbr...@us...>
Date: Fri Dec 4 19:39:25 2009 -0800
ARM: rename armv4_5_state_* as arm_state_*
And make arm_state_strings[] be const.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index a4d274e..48cfdf0 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -237,7 +237,7 @@ static int arm720t_arch_state(struct target *target)
LOG_USER("target halted in %s state due to %s, current mode: %s\n"
"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
"MMU: %s, Cache: %s",
- armv4_5_state_strings[armv4_5->core_state],
+ arm_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
arm_mode_name(armv4_5->core_mode),
buf_get_u32(armv4_5->cpsr->value, 0, 32),
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index e8c1950..6a5faff 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -451,7 +451,7 @@ int arm920t_arch_state(struct target *target)
LOG_USER("target halted in %s state due to %s, current mode: %s\n"
"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
"MMU: %s, D-Cache: %s, I-Cache: %s",
- armv4_5_state_strings[armv4_5->core_state],
+ arm_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
arm_mode_name(armv4_5->core_mode),
buf_get_u32(armv4_5->cpsr->value, 0, 32),
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 4dec23d..cacb942 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -507,7 +507,7 @@ int arm926ejs_arch_state(struct target *target)
LOG_USER("target halted in %s state due to %s, current mode: %s\n"
"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
"MMU: %s, D-Cache: %s, I-Cache: %s",
- armv4_5_state_strings[armv4_5->core_state],
+ arm_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason,target->debug_reason)->name,
arm_mode_name(armv4_5->core_mode),
buf_get_u32(armv4_5->cpsr->value, 0, 32),
diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c
index c252b44..cb1f651 100644
--- a/src/target/arm_simulator.c
+++ b/src/target/arm_simulator.c
@@ -824,14 +824,14 @@ static uint32_t armv4_5_get_cpsr(struct arm_sim_interface *sim, int pos, int bit
return buf_get_u32(armv4_5->cpsr->value, pos, bits);
}
-static enum armv4_5_state armv4_5_get_state(struct arm_sim_interface *sim)
+static enum arm_state armv4_5_get_state(struct arm_sim_interface *sim)
{
struct arm *armv4_5 = (struct arm *)sim->user_data;
return armv4_5->core_state;
}
-static void armv4_5_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode)
+static void armv4_5_set_state(struct arm_sim_interface *sim, enum arm_state mode)
{
struct arm *armv4_5 = (struct arm *)sim->user_data;
diff --git a/src/target/arm_simulator.h b/src/target/arm_simulator.h
index ae3afad..bd5458e 100644
--- a/src/target/arm_simulator.h
+++ b/src/target/arm_simulator.h
@@ -32,8 +32,8 @@ struct arm_sim_interface
uint32_t (*get_reg_mode)(struct arm_sim_interface *sim, int reg);
void (*set_reg_mode)(struct arm_sim_interface *sim, int reg, uint32_t value);
uint32_t (*get_cpsr)(struct arm_sim_interface *sim, int pos, int bits);
- enum armv4_5_state (*get_state)(struct arm_sim_interface *sim);
- void (*set_state)(struct arm_sim_interface *sim, enum armv4_5_state mode);
+ enum arm_state (*get_state)(struct arm_sim_interface *sim);
+ void (*set_state)(struct arm_sim_interface *sim, enum arm_state mode);
enum arm_mode (*get_mode)(struct arm_sim_interface *sim);
};
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 15c0a7f..102913b 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -216,7 +216,7 @@ enum arm_mode armv4_5_number_to_mode(int number)
}
}
-char* armv4_5_state_strings[] =
+const char *arm_state_strings[] =
{
"ARM", "Thumb", "Jazelle", "ThumbEE",
};
@@ -374,7 +374,7 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
: arm->core_cache->reg_list + arm->map[16];
/* Older ARMs won't have the J bit */
- enum armv4_5_state state;
+ enum arm_state state;
if (cpsr & (1 << 5)) { /* T */
if (cpsr & (1 << 24)) { /* J */
@@ -393,7 +393,7 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
arm_mode_name(mode),
- armv4_5_state_strings[arm->core_state]);
+ arm_state_strings[arm->core_state]);
}
/**
@@ -593,7 +593,7 @@ int armv4_5_arch_state(struct target *target)
LOG_USER("target halted in %s state due to %s, current mode: %s\n"
"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s",
- armv4_5_state_strings[armv4_5->core_state],
+ arm_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason,
target->debug_reason)->name,
arm_mode_name(armv4_5->core_mode),
@@ -718,7 +718,7 @@ COMMAND_HANDLER(handle_armv4_5_core_state_command)
}
}
- command_print(CMD_CTX, "core state: %s", armv4_5_state_strings[armv4_5->core_state]);
+ command_print(CMD_CTX, "core state: %s", arm_state_strings[armv4_5->core_state]);
return ERROR_OK;
}
@@ -1038,7 +1038,7 @@ int armv4_5_run_algorithm_inner(struct target *target,
{
struct arm *armv4_5 = target_to_armv4_5(target);
struct armv4_5_algorithm *armv4_5_algorithm_info = arch_info;
- enum armv4_5_state core_state = armv4_5->core_state;
+ enum arm_state core_state = armv4_5->core_state;
uint32_t context[17];
uint32_t cpsr;
int exit_breakpoint_size = 0;
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index e2b7b5a..5d58aa3 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -49,15 +49,15 @@ bool is_arm_mode(unsigned psr_mode);
int arm_mode_to_number(enum arm_mode mode);
enum arm_mode armv4_5_number_to_mode(int number);
-typedef enum armv4_5_state
+typedef enum arm_state
{
ARM_STATE_ARM,
ARM_STATE_THUMB,
ARM_STATE_JAZELLE,
ARM_STATE_THUMB_EE,
-} armv4_5_state_t;
+} arm_state_t;
-extern char* armv4_5_state_strings[];
+extern const char *arm_state_strings[];
extern const int armv4_5_core_reg_map[8][17];
@@ -98,7 +98,7 @@ struct arm
enum arm_mode core_type;
enum arm_mode core_mode;
- enum armv4_5_state core_state;
+ enum arm_state core_state;
/** Flag reporting unavailability of the BKPT instruction. */
bool is_armv4;
@@ -159,7 +159,7 @@ struct armv4_5_algorithm
int common_magic;
enum arm_mode core_mode;
- enum armv4_5_state core_state;
+ enum arm_state core_state;
};
struct arm_reg
diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index ad1f094..24ec819 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -119,7 +119,7 @@ struct armv7a_algorithm
int common_magic;
enum arm_mode core_mode;
- enum armv4_5_state core_state;
+ enum arm_state core_state;
};
struct armv7a_core_reg
diff --git a/src/target/etm.h b/src/target/etm.h
index 656e04b..92df0bf 100644
--- a/src/target/etm.h
+++ b/src/target/etm.h
@@ -164,7 +164,7 @@ struct etm_context
uint32_t trace_depth; /* number of cycles to be analyzed, 0 if no data available */
etm_portmode_t portmode; /* normal, multiplexed or demultiplexed */
etmv1_tracemode_t tracemode; /* type of info trace contains */
- int /*armv4_5_state_t*/ core_state; /* current core state */
+ int /*arm_state_t*/ core_state; /* current core state */
struct image *image; /* source for target opcodes */
uint32_t pipe_index; /* current trace cycle */
uint32_t data_index; /* cycle holding next data packet */
diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index 2644560..1c70154 100644
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -455,7 +455,7 @@ int feroceon_bulk_write_memory(struct target *target, uint32_t address, uint32_t
int retval;
struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
- enum armv4_5_state core_state = armv4_5->core_state;
+ enum arm_state core_state = armv4_5->core_state;
uint32_t x, flip, shift, save[7];
uint32_t i;
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 45692b8..253decb 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -867,7 +867,7 @@ static int xscale_arch_state(struct target *target)
"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
"MMU: %s, D-Cache: %s, I-Cache: %s"
"%s",
- armv4_5_state_strings[armv4_5->core_state],
+ arm_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
arm_mode_name(armv4_5->core_mode),
buf_get_u32(armv4_5->cpsr->value, 0, 32),
diff --git a/src/target/xscale.h b/src/target/xscale.h
index 6f81178..2bb2ba5 100644
--- a/src/target/xscale.h
+++ b/src/target/xscale.h
@@ -79,7 +79,7 @@ struct xscale_trace
int buffer_fill; /* maximum number of trace runs to read (-1 for wrap-around) */
int pc_ok;
uint32_t current_pc;
- armv4_5_state_t core_state; /* current core state (ARM, Thumb, Jazelle) */
+ arm_state_t core_state; /* current core state (ARM, Thumb, Jazelle) */
};
struct xscale_common
commit d4d16f1036bff4ce3c36edd1995e579fbf64e1c9
Author: David Brownell <dbr...@us...>
Date: Fri Dec 4 19:33:33 2009 -0800
ARM: rename armv4_5_mode_* AS arm_mode_*
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 928923d..408259e 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -1582,7 +1582,7 @@ int arm7_9_restore_context(struct target *target)
struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct reg *reg;
struct arm_reg *reg_arch_info;
- enum armv4_5_mode current_mode = armv4_5->core_mode;
+ enum arm_mode current_mode = armv4_5->core_mode;
int i, j;
int dirty;
int mode_change;
@@ -2093,7 +2093,7 @@ int arm7_9_step(struct target *target, int current, uint32_t address, int handle
}
static int arm7_9_read_core_reg(struct target *target, struct reg *r,
- int num, enum armv4_5_mode mode)
+ int num, enum arm_mode mode)
{
uint32_t* reg_p[16];
uint32_t value;
@@ -2157,7 +2157,7 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r,
}
static int arm7_9_write_core_reg(struct target *target, struct reg *r,
- int num, enum armv4_5_mode mode, uint32_t value)
+ int num, enum arm_mode mode, uint32_t value)
{
uint32_t reg[16];
struct arm_reg *areg = r->arch_info;
diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index 7cc48ab..b65e922 100644
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -102,7 +102,7 @@ static int dpm_mcr(struct target *target, int cpnum,
/* Toggles between recorded core mode (USR, SVC, etc) and a temporary one.
* Routines *must* restore the original mode before returning!!
*/
-static int dpm_modeswitch(struct arm_dpm *dpm, enum armv4_5_mode mode)
+static int dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
{
int retval;
uint32_t cpsr;
@@ -348,7 +348,7 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
* actually find anything to do...
*/
do {
- enum armv4_5_mode mode = ARM_MODE_ANY;
+ enum arm_mode mode = ARM_MODE_ANY;
did_write = false;
@@ -370,7 +370,7 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
/* may need to pick and set a mode */
if (!did_write) {
- enum armv4_5_mode tmode;
+ enum arm_mode tmode;
did_write = true;
mode = tmode = r->mode;
@@ -432,10 +432,10 @@ done:
* Caller already filtered out SPSR access; mode is never MODE_SYS
* or MODE_ANY.
*/
-static enum armv4_5_mode dpm_mapmode(struct arm *arm,
- unsigned num, enum armv4_5_mode mode)
+static enum arm_mode dpm_mapmode(struct arm *arm,
+ unsigned num, enum arm_mode mode)
{
- enum armv4_5_mode amode = arm->core_mode;
+ enum arm_mode amode = arm->core_mode;
/* don't switch if the mode is already correct */
if (amode == ARM_MODE_SYS)
@@ -473,7 +473,7 @@ static enum armv4_5_mode dpm_mapmode(struct arm *arm,
*/
static int arm_dpm_read_core_reg(struct target *target, struct reg *r,
- int regnum, enum armv4_5_mode mode)
+ int regnum, enum arm_mode mode)
{
struct arm_dpm *dpm = target_to_arm(target)->dpm;
int retval;
@@ -513,7 +513,7 @@ fail:
}
static int arm_dpm_write_core_reg(struct target *target, struct reg *r,
- int regnum, enum armv4_5_mode mode, uint32_t value)
+ int regnum, enum arm_mode mode, uint32_t value)
{
struct arm_dpm *dpm = target_to_arm(target)->dpm;
int retval;
@@ -566,7 +566,7 @@ static int arm_dpm_full_context(struct target *target)
goto done;
do {
- enum armv4_5_mode mode = ARM_MODE_ANY;
+ enum arm_mode mode = ARM_MODE_ANY;
did_read = false;
diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c
index 326240b..c252b44 100644
--- a/src/target/arm_simulator.c
+++ b/src/target/arm_simulator.c
@@ -665,7 +665,7 @@ int arm_simulate_step_core(struct target *target,
}
else
{
- enum armv4_5_mode mode = sim->get_mode(sim);
+ enum arm_mode mode = sim->get_mode(sim);
int update_cpsr = 0;
if (instruction.info.load_store_multiple.S)
@@ -721,7 +721,7 @@ int arm_simulate_step_core(struct target *target,
uint32_t Rn = sim->get_reg_mode(sim,
instruction.info.load_store_multiple.Rn);
int bits_set = 0;
- enum armv4_5_mode mode = sim->get_mode(sim);
+ enum arm_mode mode = sim->get_mode(sim);
for (i = 0; i < 16; i++)
{
@@ -839,7 +839,7 @@ static void armv4_5_set_state(struct arm_sim_interface *sim, enum armv4_5_state
}
-static enum armv4_5_mode armv4_5_get_mode(struct arm_sim_interface *sim)
+static enum arm_mode armv4_5_get_mode(struct arm_sim_interface *sim)
{
struct arm *armv4_5 = (struct arm *)sim->user_data;
diff --git a/src/target/arm_simulator.h b/src/target/arm_simulator.h
index daca371..ae3afad 100644
--- a/src/target/arm_simulator.h
+++ b/src/target/arm_simulator.h
@@ -34,7 +34,7 @@ struct arm_sim_interface
uint32_t (*get_cpsr)(struct arm_sim_interface *sim, int pos, int bits);
enum armv4_5_state (*get_state)(struct arm_sim_interface *sim);
void (*set_state)(struct arm_sim_interface *sim, enum armv4_5_state mode);
- enum armv4_5_mode (*get_mode)(struct arm_sim_interface *sim);
+ enum arm_mode (*get_mode)(struct arm_sim_interface *sim);
};
/* armv4_5 version */
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 1a92374..15c0a7f 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -163,7 +163,7 @@ bool is_arm_mode(unsigned psr_mode)
}
/** Map PSR mode bits to linear number indexing armv4_5_core_reg_map */
-int armv4_5_mode_to_number(enum armv4_5_mode mode)
+int arm_mode_to_number(enum arm_mode mode)
{
switch (mode) {
case ARM_MODE_ANY:
@@ -191,7 +191,7 @@ int armv4_5_mode_to_number(enum armv4_5_mode mode)
}
/** Map linear number indexing armv4_5_core_reg_map to PSR mode bits. */
-enum armv4_5_mode armv4_5_number_to_mode(int number)
+enum arm_mode armv4_5_number_to_mode(int number)
{
switch (number) {
case 0:
@@ -243,7 +243,7 @@ static const struct {
* (Exception modes have both CPSR and SPSR registers ...)
*/
unsigned cookie;
- enum armv4_5_mode mode;
+ enum arm_mode mode;
} arm_core_regs[] = {
/* IMPORTANT: we guarantee that the first eight cached registers
* correspond to r0..r7, and the fifteenth to PC, so that callers
@@ -346,7 +346,7 @@ const int armv4_5_core_reg_map[8][17] =
*/
void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
{
- enum armv4_5_mode mode = cpsr & 0x1f;
+ enum arm_mode mode = cpsr & 0x1f;
int num;
/* NOTE: this may be called very early, before the register
@@ -362,7 +362,7 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
arm->core_mode = mode;
/* mode_to_number() warned; set up a somewhat-sane mapping */
- num = armv4_5_mode_to_number(mode);
+ num = arm_mode_to_number(mode);
if (num < 0) {
mode = ARM_MODE_USR;
num = 0;
@@ -512,7 +512,7 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
* it won't hurt since CPSR is always flushed anyway.
*/
if (armv4_5_target->core_mode !=
- (enum armv4_5_mode)(value & 0x1f)) {
+ (enum arm_mode)(value & 0x1f)) {
LOG_DEBUG("changing ARM core mode to '%s'",
arm_mode_name(value & 0x1f));
value &= ~((1 << 24) | (1 << 5));
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 8e2fca2..e2b7b5a 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -30,7 +30,7 @@
#include <helper/command.h>
-typedef enum armv4_5_mode
+typedef enum arm_mode
{
ARM_MODE_USR = 16,
ARM_MODE_FIQ = 17,
@@ -41,13 +41,13 @@ typedef enum armv4_5_mode
ARM_MODE_UND = 27,
ARM_MODE_SYS = 31,
ARM_MODE_ANY = -1
-} armv4_5_mode_t;
+} arm_mode_t;
const char *arm_mode_name(unsigned psr_mode);
bool is_arm_mode(unsigned psr_mode);
-int armv4_5_mode_to_number(enum armv4_5_mode mode);
-enum armv4_5_mode armv4_5_number_to_mode(int number);
+int arm_mode_to_number(enum arm_mode mode);
+enum arm_mode armv4_5_number_to_mode(int number);
typedef enum armv4_5_state
{
@@ -62,7 +62,7 @@ extern char* armv4_5_state_strings[];
extern const int armv4_5_core_reg_map[8][17];
#define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
- cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
+ cache->reg_list[armv4_5_core_reg_map[arm_mode_to_number(mode)][num]]
/* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
enum { ARMV4_5_CPSR = 31, };
@@ -95,9 +95,9 @@ struct arm
* seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three
* more registers are shadowed, for "Secure Monitor" mode.
*/
- enum armv4_5_mode core_type;
+ enum arm_mode core_type;
- enum armv4_5_mode core_mode;
+ enum arm_mode core_mode;
enum armv4_5_state core_state;
/** Flag reporting unavailability of the BKPT instruction. */
@@ -122,9 +122,9 @@ struct arm
int (*full_context)(struct target *target);
int (*read_core_reg)(struct target *target, struct reg *reg,
- int num, enum armv4_5_mode mode);
+ int num, enum arm_mode mode);
int (*write_core_reg)(struct target *target, struct reg *reg,
- int num, enum armv4_5_mode mode, uint32_t value);
+ int num, enum arm_mode mode, uint32_t value);
/** Read coprocessor register. */
int (*mrc)(struct target *target, int cpnum,
@@ -158,14 +158,14 @@ struct armv4_5_algorithm
{
int common_magic;
- enum armv4_5_mode core_mode;
+ enum arm_mode core_mode;
enum armv4_5_state core_state;
};
struct arm_reg
{
int num;
- enum armv4_5_mode mode;
+ enum arm_mode mode;
struct target *target;
struct arm *armv4_5_common;
uint32_t value;
diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index f089c5c..ad1f094 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -118,14 +118,14 @@ struct armv7a_algorithm
{
int common_magic;
- enum armv4_5_mode core_mode;
+ enum arm_mode core_mode;
enum armv4_5_state core_state;
};
struct armv7a_core_reg
{
int num;
- enum armv4_5_mode mode;
+ enum arm_mode mode;
struct target *target;
struct armv7a_common *armv7a_common;
};
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 57b1081..45692b8 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -1658,7 +1658,7 @@ static int xscale_deassert_reset(struct target *target)
}
static int xscale_read_core_reg(struct target *target, struct reg *r,
- int num, enum armv4_5_mode mode)
+ int num, enum arm_mode mode)
{
/** \todo add debug handler support for core register reads */
LOG_ERROR("not implemented");
@@ -1666,7 +1666,7 @@ static int xscale_read_core_reg(struct target *target, struct reg *r,
}
static int xscale_write_core_reg(struct target *target, struct reg *r,
- int num, enum armv4_5_mode mode, uint32_t value)
+ int num, enum arm_mode mode, uint32_t value)
{
/** \todo add debug handler support for core register writes */
LOG_ERROR("not implemented");
@@ -1697,7 +1697,7 @@ static int xscale_full_context(struct target *target)
*/
for (i = 1; i < 7; i++)
{
- enum armv4_5_mode mode = armv4_5_number_to_mode(i);
+ enum arm_mode mode = armv4_5_number_to_mode(i);
bool valid = true;
struct reg *r;
@@ -1774,7 +1774,7 @@ static int xscale_restore_banked(struct target *target)
*/
for (i = 1; i < 7; i++)
{
- enum armv4_5_mode mode = armv4_5_number_to_mode(i);
+ enum arm_mode mode = armv4_5_number_to_mode(i);
struct reg *r;
if (mode == ARM_MODE_USR)
commit 0073e7a69e55eb435fc2e274ba245a27779963e4
Author: David Brownell <dbr...@us...>
Date: Fri Dec 4 19:21:14 2009 -0800
ARM: rename ARMV4_5_MODE_* as ARM_MODE_*
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/flash/arm_nandio.c b/src/flash/arm_nandio.c
index 558ed94..3991c0f 100644
--- a/src/flash/arm_nandio.c
+++ b/src/flash/arm_nandio.c
@@ -137,7 +137,7 @@ int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size)
/* set up algorithm and parameters */
algo.common_magic = ARMV4_5_COMMON_MAGIC;
- algo.core_mode = ARMV4_5_MODE_SVC;
+ algo.core_mode = ARM_MODE_SVC;
algo.core_state = ARM_STATE_ARM;
init_reg_param(®_params[0], "r0", 32, PARAM_IN);
@@ -213,7 +213,7 @@ int arm_nandread(struct arm_nand_data *nand, uint8_t *data, uint32_t size)
/* set up algorithm and parameters */
algo.common_magic = ARMV4_5_COMMON_MAGIC;
- algo.core_mode = ARMV4_5_MODE_SVC;
+ algo.core_mode = ARM_MODE_SVC;
algo.core_state = ARM_STATE_ARM;
init_reg_param(®_params[0], "r0", 32, PARAM_IN);
diff --git a/src/flash/nor/aduc702x.c b/src/flash/nor/aduc702x.c
index c223ec4..69c8274 100644
--- a/src/flash/nor/aduc702x.c
+++ b/src/flash/nor/aduc702x.c
@@ -242,7 +242,7 @@ static int aduc702x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32
}
armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
- armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
+ armv4_5_info.core_mode = ARM_MODE_SVC;
armv4_5_info.core_state = ARM_STATE_ARM;
init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
diff --git a/src/flash/nor/cfi.c b/src/flash/nor/cfi.c
index 991110b..16ba999 100644
--- a/src/flash/nor/cfi.c
+++ b/src/flash/nor/cfi.c
@@ -1086,7 +1086,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer, uint3
cfi_intel_clear_status_register(bank);
armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
- armv4_5_info...
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