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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-839-g7e2dffb
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From: David B. <dbr...@us...> - 2009-12-04 01:18:44
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- Log -----------------------------------------------------------------
commit 7e2dffbbff2534ca5afa52aa3d811b3599d2ca77
Author: David Brownell <dbr...@us...>
Date: Thu Dec 3 16:18:24 2009 -0800
ARMv7-A: tweak arch_state()
Punt to the armv4_5_arch_state() for all the common stuff, to
shrink code and so we will get any improvements it provides.
Don't hide watchpoint status if we happen to be in "abort" mode.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index 5d3976f..e889a8a 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -98,22 +98,16 @@ int armv7a_arch_state(struct target *target)
return ERROR_INVALID_ARGUMENTS;
}
- LOG_USER("target halted in %s state due to %s, current mode: %s\n"
- "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
- "MMU: %s, D-Cache: %s, I-Cache: %s",
- armv4_5_state_strings[armv4_5->core_state],
- Jim_Nvp_value2name_simple(nvp_target_debug_reason,
- target->debug_reason)->name,
- arm_mode_name(armv4_5->core_mode),
- buf_get_u32(armv4_5->cpsr->value, 0, 32),
- buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
+ armv4_5_arch_state(target);
+
+ LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
state[armv7a->armv4_5_mmu.mmu_enabled],
state[armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
state[armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
if (armv4_5->core_mode == ARMV4_5_MODE_ABT)
armv7a_show_fault_registers(target);
- else if (target->debug_reason == DBG_REASON_WATCHPOINT)
+ if (target->debug_reason == DBG_REASON_WATCHPOINT)
LOG_USER("Watchpoint triggered at PC %#08x",
(unsigned) armv7a->dpm.wp_pc);
commit ea7a49cb9b46ccc27daf6c9b306290c7e905a9fc
Author: David Brownell <dbr...@us...>
Date: Thu Dec 3 16:08:04 2009 -0800
ARM DPM: share debug reason logic
No point in both ARM11 and Cortex-A8 having private copies
of the logic sorting out e.g. DBG_REASON_WATCHPOINT.
Add and use a shared routine for this ... there's actually
a bunch more debug entry logic that could be shared, this
is just a start on that. Note that this routine fixes a
bug observed in the ARM11 code, where some abort mode quirks
were displayed as being an unknown debug reason; and also
silences needless ARM11 chatter.
Likewise with private copies of DSCR ... add one to the DPM
struct. Save it as part of setting DBG_REASON_* so later
patches can switch over to using that copy.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/arm11.c b/src/target/arm11.c
index b01e33b..20ad22d 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -83,8 +83,7 @@ static int arm11_check_init(struct arm11_common *arm11)
*/
arm11->arm.target->state = TARGET_HALTED;
- arm11->arm.target->debug_reason =
- arm11_get_DSCR_debug_reason(arm11->dscr);
+ arm_dpm_report_dscr(arm11->arm.dpm, arm11->dscr);
}
else
{
@@ -108,8 +107,7 @@ static int arm11_debug_entry(struct arm11_common *arm11)
int retval;
arm11->arm.target->state = TARGET_HALTED;
- arm11->arm.target->debug_reason =
- arm11_get_DSCR_debug_reason(arm11->dscr);
+ arm_dpm_report_dscr(arm11->arm.dpm, arm11->dscr);
/* REVISIT entire cache should already be invalid !!! */
register_cache_invalidate(arm11->arm.core_cache);
@@ -551,20 +549,12 @@ static int arm11_resume(struct target *target, int current,
i++;
}
+ target->debug_reason = DBG_REASON_NOTHALTED;
if (!debug_execution)
- {
- target->state = TARGET_RUNNING;
- target->debug_reason = DBG_REASON_NOTHALTED;
-
- CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
- }
+ target->state = TARGET_RUNNING;
else
- {
- target->state = TARGET_DEBUG_RUNNING;
- target->debug_reason = DBG_REASON_NOTHALTED;
-
- CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
- }
+ target->state = TARGET_DEBUG_RUNNING;
+ CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
return ERROR_OK;
}
@@ -728,7 +718,7 @@ static int arm11_step(struct target *target, int current,
}
- target->debug_reason = DBG_REASON_SINGLESTEP;
+ target->debug_reason = DBG_REASON_SINGLESTEP;
CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
diff --git a/src/target/arm11.h b/src/target/arm11.h
index 5f78db5..f3f0644 100644
--- a/src/target/arm11.h
+++ b/src/target/arm11.h
@@ -94,18 +94,6 @@ enum arm11_instructions
ARM11_BYPASS = 0x1F,
};
-enum arm11_dscr
-{
-
- ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK = 0x0F << 2,
- ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT = 0x00 << 2,
- ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT = 0x01 << 2,
- ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT = 0x02 << 2,
- ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION = 0x03 << 2,
- ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ = 0x04 << 2,
- ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH = 0x05 << 2,
-};
-
enum arm11_sc7
{
ARM11_SC7_NULL = 0,
diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c
index 3df1c65..e5d3f80 100644
--- a/src/target/arm11_dbgtap.c
+++ b/src/target/arm11_dbgtap.c
@@ -288,50 +288,6 @@ int arm11_write_DSCR(struct arm11_common * arm11, uint32_t dscr)
return ERROR_OK;
}
-
-
-/** Get the debug reason from Debug Status and Control Register (DSCR)
- *
- * \param dscr DSCR value to analyze
- * \return Debug reason
- *
- */
-enum target_debug_reason arm11_get_DSCR_debug_reason(uint32_t dscr)
-{
- switch (dscr & ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK)
- {
- case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT:
- LOG_INFO("Debug entry: JTAG HALT");
- return DBG_REASON_DBGRQ;
-
- case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT:
- LOG_INFO("Debug entry: breakpoint");
- return DBG_REASON_BREAKPOINT;
-
- case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT:
- LOG_INFO("Debug entry: watchpoint");
- return DBG_REASON_WATCHPOINT;
-
- case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION:
- LOG_INFO("Debug entry: BKPT instruction");
- return DBG_REASON_BREAKPOINT;
-
- case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ:
- LOG_INFO("Debug entry: EDBGRQ signal");
- return DBG_REASON_DBGRQ;
-
- case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH:
- LOG_INFO("Debug entry: VCR vector catch");
- return DBG_REASON_BREAKPOINT;
-
- default:
- LOG_INFO("Debug entry: unknown");
- return DBG_REASON_DBGRQ;
- }
-};
-
-
-
/** Prepare the stage for ITR/DTR operations
* from the arm11_run_instr... group of functions.
*
diff --git a/src/target/arm11_dbgtap.h b/src/target/arm11_dbgtap.h
index a6b9bbd..2c586cc 100644
--- a/src/target/arm11_dbgtap.h
+++ b/src/target/arm11_dbgtap.h
@@ -14,8 +14,6 @@ int arm11_add_debug_SCAN_N(struct arm11_common *arm11,
int arm11_read_DSCR(struct arm11_common *arm11);
int arm11_write_DSCR(struct arm11_common *arm11, uint32_t dscr);
-enum target_debug_reason arm11_get_DSCR_debug_reason(uint32_t dscr);
-
int arm11_run_instr_data_prepare(struct arm11_common *arm11);
int arm11_run_instr_data_finish(struct arm11_common *arm11);
int arm11_run_instr_no_data1(struct arm11_common *arm11, uint32_t opcode);
diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index ca3930f..b02baa3 100644
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -756,6 +756,42 @@ void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t addr)
/*----------------------------------------------------------------------*/
/*
+ * Other debug and support utilities
+ */
+
+void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr)
+{
+ struct target *target = dpm->arm->target;
+
+ dpm->dscr = dscr;
+
+ /* Examine debug reason */
+ switch (DSCR_ENTRY(dscr)) {
+ case 6: /* Data abort (v6 only) */
+ case 7: /* Prefetch abort (v6 only) */
+ /* FALL THROUGH -- assume a v6 core in abort mode */
+ case 0: /* HALT request from debugger */
+ case 4: /* EDBGRQ */
+ target->debug_reason = DBG_REASON_DBGRQ;
+ break;
+ case 1: /* HW breakpoint */
+ case 3: /* SW BKPT */
+ case 5: /* vector catch */
+ target->debug_reason = DBG_REASON_BREAKPOINT;
+ break;
+ case 2: /* asynch watchpoint */
+ case 10: /* precise watchpoint */
+ target->debug_reason = DBG_REASON_WATCHPOINT;
+ break;
+ default:
+ target->debug_reason = DBG_REASON_UNDEFINED;
+ break;
+ }
+}
+
+/*----------------------------------------------------------------------*/
+
+/*
* Setup and management support.
*/
diff --git a/src/target/arm_dpm.h b/src/target/arm_dpm.h
index 11213a3..135e3db 100644
--- a/src/target/arm_dpm.h
+++ b/src/target/arm_dpm.h
@@ -125,6 +125,9 @@ struct arm_dpm {
/** Address of the instruction which triggered a watchpoint. */
uint32_t wp_pc;
+ /** Recent value of DSCR. */
+ uint32_t dscr;
+
// FIXME -- read/write DCSR methods and symbols
};
@@ -151,4 +154,6 @@ void arm_dpm_report_wfar(struct arm_dpm *, uint32_t wfar);
#define DSCR_ENTRY(dscr) (((dscr) >> 2) & 0xf)
+void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dcsr);
+
#endif /* __ARM_DPM_H */
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 14cbb9d..eb42a5d 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -782,7 +782,7 @@ static int cortex_a8_resume(struct target *target, int current,
static int cortex_a8_debug_entry(struct target *target)
{
int i;
- uint32_t regfile[16], wfar, cpsr, dscr;
+ uint32_t regfile[16], cpsr, dscr;
int retval = ERROR_OK;
struct working_area *regfile_working_area = NULL;
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
@@ -793,6 +793,7 @@ static int cortex_a8_debug_entry(struct target *target)
LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
+ /* REVISIT surely we should not re-read DSCR !! */
mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
@@ -807,30 +808,16 @@ static int cortex_a8_debug_entry(struct target *target)
armv7a->debug_base + CPUDBG_DSCR, dscr);
/* Examine debug reason */
- switch (DSCR_ENTRY(cortex_a8->cpudbg_dscr))
- {
- case 0: /* DRCR[0] write */
- case 4: /* EDBGRQ */
- target->debug_reason = DBG_REASON_DBGRQ;
- break;
- case 1: /* HW breakpoint */
- case 3: /* SW BKPT */
- case 5: /* vector catch */
- target->debug_reason = DBG_REASON_BREAKPOINT;
- break;
- case 2: /* asynch watchpoint */
- case 10: /* precise watchpoint */
- target->debug_reason = DBG_REASON_WATCHPOINT;
-
- /* save address of faulting instruction */
- retval = mem_ap_read_atomic_u32(swjdp,
- armv7a->debug_base + CPUDBG_WFAR,
- &wfar);
- arm_dpm_report_wfar(&armv7a->dpm, wfar);
- break;
- default:
- target->debug_reason = DBG_REASON_UNDEFINED;
- break;
+ arm_dpm_report_dscr(&armv7a->dpm, cortex_a8->cpudbg_dscr);
+
+ /* save address of instruction that triggered the watchpoint? */
+ if (target->debug_reason == DBG_REASON_WATCHPOINT) {
+ uint32_t wfar;
+
+ retval = mem_ap_read_atomic_u32(swjdp,
+ armv7a->debug_base + CPUDBG_WFAR,
+ &wfar);
+ arm_dpm_report_wfar(&armv7a->dpm, wfar);
}
/* REVISIT fast_reg_read is never set ... */
commit 6eee0729d79eab496d1d4368a2bae7e4e2d19876
Author: David Brownell <dbr...@us...>
Date: Thu Dec 3 16:08:04 2009 -0800
ARM11: use shared DSCR bit names
For the bits now defined in "arm_dpm.h", switch to the
shared DSCR_* symbol and remove the ARM11_DSCR_* version.
Define DSCR_INT_DIS and use it instead of the ARM11_DSCR_*
sibling symbol. (Note: for both ARM11 and Cortex-A8, this
should arguably be enabled by default when single stepping.)
Remove some other unused declarations in "arm11.h".
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/arm11.c b/src/target/arm11.c
index 124868e..b01e33b 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -40,6 +40,10 @@
#define _DEBUG_INSTRUCTION_EXECUTION_
#endif
+
+/* FIXME none of these flags should be global to all ARM11 cores!
+ * Most of them shouldn't exist at all, once the code works...
+ */
static bool arm11_config_memwrite_burst = true;
static bool arm11_config_memwrite_error_fatal = true;
static uint32_t arm11_vcr = 0;
@@ -59,18 +63,18 @@ static int arm11_check_init(struct arm11_common *arm11)
CHECK_RETVAL(arm11_read_DSCR(arm11));
LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
- if (!(arm11->dscr & ARM11_DSCR_MODE_SELECT))
+ if (!(arm11->dscr & DSCR_HALT_DBG_MODE))
{
LOG_DEBUG("Bringing target into debug mode");
- arm11->dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
+ arm11->dscr |= DSCR_HALT_DBG_MODE;
arm11_write_DSCR(arm11, arm11->dscr);
/* add further reset initialization here */
arm11->simulate_reset_on_next_halt = true;
- if (arm11->dscr & ARM11_DSCR_CORE_HALTED)
+ if (arm11->dscr & DSCR_CORE_HALTED)
{
/** \todo TODO: this needs further scrutiny because
* arm11_debug_entry() never gets called. (WHY NOT?)
@@ -113,7 +117,7 @@ static int arm11_debug_entry(struct arm11_common *arm11)
/* See e.g. ARM1136 TRM, "14.8.4 Entering Debug state" */
/* maybe save wDTR (pending DCC write to debug SW, e.g. libdcc) */
- arm11->is_wdtr_saved = !!(arm11->dscr & ARM11_DSCR_WDTR_FULL);
+ arm11->is_wdtr_saved = !!(arm11->dscr & DSCR_DTR_TX_FULL);
if (arm11->is_wdtr_saved)
{
arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
@@ -131,15 +135,13 @@ static int arm11_debug_entry(struct arm11_common *arm11)
}
- /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE
+ /* DSCR: set the Execute ARM instruction enable bit.
*
* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode",
- * but not to issue ITRs. ARM1136 seems to require this to issue
- * ITR's as well...
+ * but not to issue ITRs(?). The ARMv7 arch spec says it's required
+ * for executing instructions via ITR.
*/
-
- arm11_write_DSCR(arm11, ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE
- | arm11->dscr);
+ arm11_write_DSCR(arm11, DSCR_ITR_EN | arm11->dscr);
/* From the spec:
@@ -188,7 +190,7 @@ static int arm11_debug_entry(struct arm11_common *arm11)
return retval;
/* maybe save rDTR (pending DCC read from debug SW, e.g. libdcc) */
- arm11->is_rdtr_saved = !!(arm11->dscr & ARM11_DSCR_RDTR_FULL);
+ arm11->is_rdtr_saved = !!(arm11->dscr & DSCR_DTR_RX_FULL);
if (arm11->is_rdtr_saved)
{
/* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
@@ -248,7 +250,7 @@ static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
{
CHECK_RETVAL(arm11_read_DSCR(arm11));
- if (arm11->dscr & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
+ if (arm11->dscr & (DSCR_DTR_RX_FULL | DSCR_DTR_TX_FULL))
{
/*
The wDTR/rDTR two registers that are used to send/receive data to/from
@@ -324,7 +326,7 @@ static int arm11_poll(struct target *target)
CHECK_RETVAL(arm11_check_init(arm11));
- if (arm11->dscr & ARM11_DSCR_CORE_HALTED)
+ if (arm11->dscr & DSCR_CORE_HALTED)
{
if (target->state != TARGET_HALTED)
{
@@ -401,7 +403,7 @@ static int arm11_halt(struct target *target)
{
CHECK_RETVAL(arm11_read_DSCR(arm11));
- if (arm11->dscr & ARM11_DSCR_CORE_HALTED)
+ if (arm11->dscr & DSCR_CORE_HALTED)
break;
@@ -529,7 +531,7 @@ static int arm11_resume(struct target *target, int current,
LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
- if (arm11->dscr & ARM11_DSCR_CORE_RESTARTED)
+ if (arm11->dscr & DSCR_CORE_RESTARTED)
break;
@@ -674,9 +676,9 @@ static int arm11_step(struct target *target, int current,
if (arm11_config_step_irq_enable)
/* this disable should be redundant ... */
- arm11->dscr &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
+ arm11->dscr &= ~DSCR_INT_DIS;
else
- arm11->dscr |= ARM11_DSCR_INTERRUPTS_DISABLE;
+ arm11->dscr |= DSCR_INT_DIS;
CHECK_RETVAL(arm11_leave_debug_state(arm11, handle_breakpoints));
@@ -690,8 +692,8 @@ static int arm11_step(struct target *target, int current,
while (1)
{
- const uint32_t mask = ARM11_DSCR_CORE_RESTARTED
- | ARM11_DSCR_CORE_HALTED;
+ const uint32_t mask = DSCR_CORE_RESTARTED
+ | DSCR_CORE_HALTED;
CHECK_RETVAL(arm11_read_DSCR(arm11));
LOG_DEBUG("DSCR %08x e", (unsigned) arm11->dscr);
@@ -722,7 +724,7 @@ static int arm11_step(struct target *target, int current,
CHECK_RETVAL(arm11_debug_entry(arm11));
/* restore default state */
- arm11->dscr &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
+ arm11->dscr &= ~DSCR_INT_DIS;
}
diff --git a/src/target/arm11.h b/src/target/arm11.h
index b118e1c..5f78db5 100644
--- a/src/target/arm11.h
+++ b/src/target/arm11.h
@@ -38,6 +38,7 @@
} \
} while (0)
+/* bits from ARMv7 DIDR */
enum arm11_debug_version
{
ARM11_DEBUG_V6 = 0x01,
@@ -95,8 +96,6 @@ enum arm11_instructions
enum arm11_dscr
{
- ARM11_DSCR_CORE_HALTED = 1 << 0,
- ARM11_DSCR_CORE_RESTARTED = 1 << 1,
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK = 0x0F << 2,
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT = 0x00 << 2,
@@ -105,20 +104,6 @@ enum arm11_dscr
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION = 0x03 << 2,
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ = 0x04 << 2,
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH = 0x05 << 2,
-
- ARM11_DSCR_STICKY_PRECISE_DATA_ABORT = 1 << 6,
- ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT = 1 << 7,
- ARM11_DSCR_INTERRUPTS_DISABLE = 1 << 11,
- ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE = 1 << 13,
- ARM11_DSCR_MODE_SELECT = 1 << 14,
- ARM11_DSCR_WDTR_FULL = 1 << 29,
- ARM11_DSCR_RDTR_FULL = 1 << 30,
-};
-
-enum arm11_cpsr
-{
- ARM11_CPSR_T = 1 << 5,
- ARM11_CPSR_J = 1 << 24,
};
enum arm11_sc7
@@ -132,10 +117,4 @@ enum arm11_sc7
ARM11_SC7_WCR0 = 112,
};
-struct arm11_reg_state
-{
- uint32_t def_index;
- struct target * target;
-};
-
#endif /* ARM11_H */
diff --git a/src/target/arm_dpm.h b/src/target/arm_dpm.h
index 1f32e8b..11213a3 100644
--- a/src/target/arm_dpm.h
+++ b/src/target/arm_dpm.h
@@ -141,6 +141,7 @@ void arm_dpm_report_wfar(struct arm_dpm *, uint32_t wfar);
*/
#define DSCR_CORE_HALTED (1 << 0)
#define DSCR_CORE_RESTARTED (1 << 1)
+#define DSCR_INT_DIS (1 << 11)
#define DSCR_ITR_EN (1 << 13)
#define DSCR_HALT_DBG_MODE (1 << 14)
#define DSCR_MON_DBG_MODE (1 << 15)
commit eb6c880ddcb06cb011ebd4557d9057d04ab9b4fb
Author: David Brownell <dbr...@us...>
Date: Thu Dec 3 16:08:04 2009 -0800
ARM DPM: make DSCR bit defs sharable
Move the symbols for these bits from "armv7a.h" to "arm_dpm.h",
where they can be seen and used not just by Cortex-A but also
by the ARM11 (armv6) code.
Change them from bit numbers to bit masks ... this matches the
usage in ARM11 code, and also makes it easier to read.
Rename DSCR_EXT_INT_EN as DSCR_ITR_EN to match the docs; it's
enabling ITR functionality, not external interrupts, so this
changes the name to be less misleading. (There *IS* a bit
affecting interrupts, and this isn't it.)
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/arm_dpm.h b/src/target/arm_dpm.h
index c284144..1f32e8b 100644
--- a/src/target/arm_dpm.h
+++ b/src/target/arm_dpm.h
@@ -136,4 +136,18 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *, bool bpwp);
void arm_dpm_report_wfar(struct arm_dpm *, uint32_t wfar);
+/* Subset of DSCR bits; see ARMv7a arch spec section C10.3.1.
+ * Not all v7 bits are valid in v6.
+ */
+#define DSCR_CORE_HALTED (1 << 0)
+#define DSCR_CORE_RESTARTED (1 << 1)
+#define DSCR_ITR_EN (1 << 13)
+#define DSCR_HALT_DBG_MODE (1 << 14)
+#define DSCR_MON_DBG_MODE (1 << 15)
+#define DSCR_INSTR_COMP (1 << 24)
+#define DSCR_DTR_TX_FULL (1 << 29)
+#define DSCR_DTR_RX_FULL (1 << 30)
+
+#define DSCR_ENTRY(dscr) (((dscr) >> 2) & 0xf)
+
#endif /* __ARM_DPM_H */
diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 0d5da86..f089c5c 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -114,16 +114,6 @@ target_to_armv7a(struct target *target)
/* See ARMv7a arch spec section C10.8 */
#define CPUDBG_AUTHSTATUS 0xFB8
-/* DSCR bit numbers (See ARMv7a arch spec section 12.4.5) */
-#define DSCR_CORE_HALTED 0
-#define DSCR_CORE_RESTARTED 1
-#define DSCR_EXT_INT_EN 13
-#define DSCR_HALT_DBG_MODE 14
-#define DSCR_MON_DBG_MODE 15
-#define DSCR_INSTR_COMP 24
-#define DSCR_DTR_TX_FULL 29
-#define DSCR_DTR_RX_FULL 30
-
struct armv7a_algorithm
{
int common_magic;
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 9ca072e..14cbb9d 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -91,8 +91,8 @@ static int cortex_a8_init_debug_access(struct target *target)
/* To reduce needless round-trips, pass in a pointer to the current
* DSCR value. Initialize it to zero if you just need to know the
- * value on return from this function; or (1 << DSCR_INSTR_COMP) if
- * you happen to know that no instruction is pending.
+ * value on return from this function; or DSCR_INSTR_COMP if you
+ * happen to know that no instruction is pending.
*/
static int cortex_a8_exec_opcode(struct target *target,
uint32_t opcode, uint32_t *dscr_p)
@@ -107,7 +107,7 @@ static int cortex_a8_exec_opcode(struct target *target,
LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
/* Wait for InstrCompl bit to be set */
- while ((dscr & (1 << DSCR_INSTR_COMP)) == 0)
+ while ((dscr & DSCR_INSTR_COMP) == 0)
{
retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
@@ -130,7 +130,7 @@ static int cortex_a8_exec_opcode(struct target *target,
return retval;
}
}
- while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
+ while ((dscr & DSCR_INSTR_COMP) == 0); /* Wait for InstrCompl bit to be set */
if (dscr_p)
*dscr_p = dscr;
@@ -198,7 +198,7 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target,
}
/* Wait for DTRRXfull then read DTRRTX */
- while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0)
+ while ((dscr & DSCR_DTR_TX_FULL) == 0)
{
retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
@@ -225,7 +225,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
/* Check that DCCRX is not full */
retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
- if (dscr & (1 << DSCR_DTR_RX_FULL))
+ if (dscr & DSCR_DTR_RX_FULL)
{
LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
/* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */
@@ -315,14 +315,14 @@ static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data,
uint32_t *dscr_p)
{
struct swjdp_common *swjdp = &a8->armv7a_common.swjdp_info;
- uint32_t dscr = 1 << DSCR_INSTR_COMP;
+ uint32_t dscr = DSCR_INSTR_COMP;
int retval;
if (dscr_p)
dscr = *dscr_p;
/* Wait for DTRRXfull */
- while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0) {
+ while ((dscr & DSCR_DTR_TX_FULL) == 0) {
retval = mem_ap_read_atomic_u32(swjdp,
a8->armv7a_common.debug_base + CPUDBG_DSCR,
&dscr);
@@ -350,10 +350,10 @@ static int cortex_a8_dpm_prepare(struct arm_dpm *dpm)
retval = mem_ap_read_atomic_u32(swjdp,
a8->armv7a_common.debug_base + CPUDBG_DSCR,
&dscr);
- } while ((dscr & (1 << DSCR_INSTR_COMP)) == 0);
+ } while ((dscr & DSCR_INSTR_COMP) == 0);
/* this "should never happen" ... */
- if (dscr & (1 << DSCR_DTR_RX_FULL)) {
+ if (dscr & DSCR_DTR_RX_FULL) {
LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
/* Clear DCCRX */
retval = cortex_a8_exec_opcode(
@@ -376,7 +376,7 @@ static int cortex_a8_instr_write_data_dcc(struct arm_dpm *dpm,
{
struct cortex_a8_common *a8 = dpm_to_a8(dpm);
int retval;
- uint32_t dscr = 1 << DSCR_INSTR_COMP;
+ uint32_t dscr = DSCR_INSTR_COMP;
retval = cortex_a8_write_dcc(a8, data);
@@ -390,7 +390,7 @@ static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm,
uint32_t opcode, uint32_t data)
{
struct cortex_a8_common *a8 = dpm_to_a8(dpm);
- uint32_t dscr = 1 << DSCR_INSTR_COMP;
+ uint32_t dscr = DSCR_INSTR_COMP;
int retval;
retval = cortex_a8_write_dcc(a8, data);
@@ -413,7 +413,7 @@ static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm,
static int cortex_a8_instr_cpsr_sync(struct arm_dpm *dpm)
{
struct target *target = dpm->arm->target;
- uint32_t dscr = 1 << DSCR_INSTR_COMP;
+ uint32_t dscr = DSCR_INSTR_COMP;
/* "Prefetch flush" after modifying execution status in CPSR */
return cortex_a8_exec_opcode(target,
@@ -426,7 +426,7 @@ static int cortex_a8_instr_read_data_dcc(struct arm_dpm *dpm,
{
struct cortex_a8_common *a8 = dpm_to_a8(dpm);
int retval;
- uint32_t dscr = 1 << DSCR_INSTR_COMP;
+ uint32_t dscr = DSCR_INSTR_COMP;
/* the opcode, writing data to DCC */
retval = cortex_a8_exec_opcode(
@@ -442,7 +442,7 @@ static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm,
uint32_t opcode, uint32_t *data)
{
struct cortex_a8_common *a8 = dpm_to_a8(dpm);
- uint32_t dscr = 1 << DSCR_INSTR_COMP;
+ uint32_t dscr = DSCR_INSTR_COMP;
int retval;
/* the opcode, writing data to R0 */
@@ -639,7 +639,7 @@ static int cortex_a8_halt(struct target *target)
*/
mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr);
retval = mem_ap_write_atomic_u32(swjdp,
- armv7a->debug_base + CPUDBG_DSCR, dscr | (1 << DSCR_HALT_DBG_MODE));
+ armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE);
if (retval != ERROR_OK)
goto out;
@@ -647,7 +647,7 @@ static int cortex_a8_halt(struct target *target)
do {
mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
- } while ((dscr & (1 << DSCR_CORE_HALTED)) == 0);
+ } while ((dscr & DSCR_CORE_HALTED) == 0);
target->debug_reason = DBG_REASON_DBGRQ;
@@ -742,13 +742,18 @@ static int cortex_a8_resume(struct target *target, int current,
}
#endif
- /* Restart core and wait for it to be started */
+ /* Restart core and wait for it to be started
+ * NOTE: this clears DSCR_ITR_EN and other bits.
+ *
+ * REVISIT: for single stepping, we probably want to
+ * disable IRQs by default, with optional override...
+ */
mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DRCR, 0x2);
do {
mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
- } while ((dscr & (1 << DSCR_CORE_RESTARTED)) == 0);
+ } while ((dscr & DSCR_CORE_RESTARTED) == 0);
target->debug_reason = DBG_REASON_NOTHALTED;
target->state = TARGET_RUNNING;
@@ -788,7 +793,6 @@ static int cortex_a8_debug_entry(struct target *target)
LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
- /* Enable the ITR execution once we are in debug mode */
mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
@@ -797,12 +801,13 @@ static int cortex_a8_debug_entry(struct target *target)
* Synchronization Barrier: ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
*/
- dscr |= (1 << DSCR_EXT_INT_EN);
+ /* Enable the ITR execution once we are in debug mode */
+ dscr |= DSCR_ITR_EN;
retval = mem_ap_write_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, dscr);
/* Examine debug reason */
- switch ((cortex_a8->cpudbg_dscr >> 2)&0xF)
+ switch (DSCR_ENTRY(cortex_a8->cpudbg_dscr))
{
case 0: /* DRCR[0] write */
case 4: /* EDBGRQ */
@@ -1005,7 +1010,8 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
}
cortex_a8_unset_breakpoint(target, &stepbreakpoint);
- if (timeout > 0) target->debug_reason = DBG_REASON_BREAKPOINT;
+ if (timeout > 0)
+ target->debug_reason = DBG_REASON_BREAKPOINT;
if (breakpoint)
cortex_a8_set_breakpoint(target, breakpoint, 0);
-----------------------------------------------------------------------
Summary of changes:
src/target/arm11.c | 66 +++++++++++++++-------------------
src/target/arm11.h | 35 +-----------------
src/target/arm11_dbgtap.c | 44 -----------------------
src/target/arm11_dbgtap.h | 2 -
src/target/arm_dpm.c | 36 ++++++++++++++++++
src/target/arm_dpm.h | 20 ++++++++++
src/target/armv7a.c | 14 ++-----
src/target/armv7a.h | 10 -----
src/target/cortex_a8.c | 87 ++++++++++++++++++++------------------------
9 files changed, 130 insertions(+), 184 deletions(-)
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