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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-740-ga65e75e
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From: David B. <dbr...@us...> - 2009-12-01 10:11:18
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- Log -----------------------------------------------------------------
commit a65e75ea34153a8d0a0fe0b07497ad75c5726ab6
Author: David Brownell <dbr...@us...>
Date: Tue Dec 1 01:09:10 2009 -0800
Tcl and doc: update to match new 'arm mcr ...' etc
Make them match the C code.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/NEWS b/NEWS
index b7eb0f0..1af1331 100644
--- a/NEWS
+++ b/NEWS
@@ -15,6 +15,8 @@ Target Layer:
- recognize TrustZone "Secure Monitor" mode
- "arm regs" command output changed
- register names use "sp" not "r13"
+ - add top-level "mcr" and "mrc" commands, replacing
+ various core-specific operations
ARM11
- Preliminary ETM and ETB hookup
- accelerated "flash erase_check"
diff --git a/doc/openocd.texi b/doc/openocd.texi
index ea30092..7e23211 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -1524,7 +1524,7 @@ proc setc15 @{regs value@} @{
echo [format "set p15 0x%04x, 0x%08x" $regs $value]
- mcr 15 [expr ($regs>>12)&0x7] \
+ arm mcr 15 [expr ($regs>>12)&0x7] \
[expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
[expr ($regs>>8)&0x7] $value
@}
@@ -5609,6 +5609,24 @@ with a handful of exceptions.
ThumbEE disassembly currently has no explicit support.
@end deffn
+@deffn Command {arm mcr} pX op1 CRn CRm op2 value
+Write @var{value} to a coprocessor @var{pX} register
+passing parameters @var{CRn},
+@var{CRm}, opcodes @var{opc1} and @var{opc2},
+and using the MCR instruction.
+(Parameter sequence matches the ARM instruction, but omits
+an ARM register.)
+@end deffn
+
+@deffn Command {arm mrc} pX coproc op1 CRn CRm op2
+Read a coprocessor @var{pX} register passing parameters @var{CRn},
+@var{CRm}, opcodes @var{opc1} and @var{opc2},
+and the MRC instruction.
+Returns the result so it can be manipulated by Jim scripts.
+(Parameter sequence matches the ARM instruction, but omits
+an ARM register.)
+@end deffn
+
@deffn Command {arm reg}
Display a table of all banked core registers, fetching the current value from every
core mode if necessary.
diff --git a/tcl/board/csb732.cfg b/tcl/board/csb732.cfg
index 9022faf..cad38e2 100644
--- a/tcl/board/csb732.cfg
+++ b/tcl/board/csb732.cfg
@@ -19,13 +19,13 @@ proc csb732_init { } {
# We assume the interpreter latency is enough.
# Allow access to all coprocessors
- mcr 15 0 15 1 0 0x2001
+ arm mcr 15 0 15 1 0 0x2001
# Disable MMU, caches, write buffer
- mcr 15 0 1 0 0 0x78
+ arm mcr 15 0 1 0 0 0x78
# Grant manager access to all domains
- mcr 15 0 3 0 0 0xFFFFFFFF
+ arm mcr 15 0 3 0 0 0xFFFFFFFF
# Set ARM clock to 532 MHz, AHB to 133 MHz
mww 0x53F80004 0x1000
diff --git a/tcl/board/dm355evm.cfg b/tcl/board/dm355evm.cfg
index 2c8bea8..db47b8d 100644
--- a/tcl/board/dm355evm.cfg
+++ b/tcl/board/dm355evm.cfg
@@ -182,7 +182,7 @@ proc dm355evm_init {} {
########################
# turn on icache - set I bit in cp15 register c1
- mcr 15 0 0 1 0 0x00051078
+ arm mcr 15 0 0 1 0 0x00051078
}
# NAND -- socket has two chipselects, MT29F16G08FAA puts 1GByte on each one.
diff --git a/tcl/board/openrd.cfg b/tcl/board/openrd.cfg
index 12cc79e..6371eff 100644
--- a/tcl/board/openrd.cfg
+++ b/tcl/board/openrd.cfg
@@ -29,7 +29,7 @@ proc openrd_init { } {
jtag_reset 0 0
wait_halt
- mcr 15 0 0 1 0 0x00052078
+ arm mcr 15 0 0 1 0 0x00052078
mww 0xD0001400 0x43000C30 # DDR SDRAM Configuration Register
mww 0xD0001404 0x37543000 # Dunit Control Low Register
diff --git a/tcl/board/sheevaplug.cfg b/tcl/board/sheevaplug.cfg
index 9267eb9..b843213 100644
--- a/tcl/board/sheevaplug.cfg
+++ b/tcl/board/sheevaplug.cfg
@@ -29,7 +29,7 @@ proc sheevaplug_init { } {
jtag_reset 0 0
wait_halt
- mcr 15 0 0 1 0 0x00052078
+ arm mcr 15 0 0 1 0 0x00052078
mww 0xD0001400 0x43000C30 # DDR SDRAM Configuration Register
mww 0xD0001404 0x39543000 # Dunit Control Low Register
diff --git a/tcl/target/c100helper.tcl b/tcl/target/c100helper.tcl
index 54fe07f..9658871 100644
--- a/tcl/target/c100helper.tcl
+++ b/tcl/target/c100helper.tcl
@@ -436,22 +436,22 @@ proc initC100 {} {
# */
# mov r0, #0
# mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
- mcr 15 0 7 7 0 0x0
+ arm mcr 15 0 7 7 0 0x0
# mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
- mcr 15 0 8 7 0 0x0
+ arm mcr 15 0 8 7 0 0x0
# /*
# * disable MMU stuff and caches
# */
# mrc p15, 0, r0, c1, c0, 0
- mrc 15 0 1 0 0
+ arm mrc 15 0 1 0 0
# bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
# bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
# orr r0, r0, #0x00000002 @ set bit 2 (A) Align
# orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
# orr r0, r0, #0x00400000 @ set bit 22 (U)
# mcr p15, 0, r0, c1, c0, 0
- mcr 15 0 1 0 0 0x401002
+ arm mcr 15 0 1 0 0 0x401002
# This is from bsp_init() in u-boot/boards/mindspeed/ooma-darwin/board.c
# APB init
# // Setting APB Bus Wait states to 1, set post write
diff --git a/tcl/target/imx.cfg b/tcl/target/imx.cfg
index bfcc652..547ec56 100644
--- a/tcl/target/imx.cfg
+++ b/tcl/target/imx.cfg
@@ -10,7 +10,7 @@ proc setc15 {regs value} {
echo [format "set p15 0x%04x, 0x%08x" $regs $value]
- mcr 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value
+ arm mcr 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value
}
-----------------------------------------------------------------------
Summary of changes:
NEWS | 2 ++
doc/openocd.texi | 20 +++++++++++++++++++-
tcl/board/csb732.cfg | 6 +++---
tcl/board/dm355evm.cfg | 2 +-
tcl/board/openrd.cfg | 2 +-
tcl/board/sheevaplug.cfg | 2 +-
tcl/target/c100helper.tcl | 8 ++++----
tcl/target/imx.cfg | 2 +-
8 files changed, 32 insertions(+), 12 deletions(-)
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