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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-498-ga1777fc
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From: David B. <dbr...@us...> - 2009-11-20 04:03:29
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- Log -----------------------------------------------------------------
commit a1777fc6493b4c1879ef133c565327212859d37c
Author: David Brownell <dbr...@us...>
Date: Thu Nov 19 19:03:12 2009 -0800
Cortex-A8: better context restore
The previous version never wrote dirty registers
for non-current CPU modes ... fix that.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 01b7aee..168fe12 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -531,7 +531,7 @@ static int cortex_a8_resume(struct target *target, int current,
armv4_5->core_mode, 15).valid = 1;
cortex_a8_restore_context(target);
-// arm7_9_restore_context(target); TODO Context is currently NOT Properly restored
+
#if 0
/* the front-end may request us not to handle breakpoints */
if (handle_breakpoints)
@@ -850,30 +850,84 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
static int cortex_a8_restore_context(struct target *target)
{
- int i;
uint32_t value;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
+ struct reg_cache *cache = armv7a->armv4_5_common.core_cache;
+ unsigned max = cache->num_regs;
+ struct reg *r;
+ bool flushed, flush_cpsr = false;
LOG_DEBUG(" ");
if (armv7a->pre_restore_context)
armv7a->pre_restore_context(target);
- for (i = 15; i >= 0; i--)
- {
- if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, i).dirty)
- {
- value = buf_get_u32(ARMV4_5_CORE_REG_MODE(
- armv4_5->core_cache,
- armv4_5->core_mode, i).value,
- 0, 32);
+ /* Flush all dirty registers from the cache, one mode at a time so
+ * that we write CPSR as little as possible. Save CPSR and R0 for
+ * last; they're used to change modes and write other registers.
+ *
+ * REVISIT be smarter: save eventual mode for last loop, don't
+ * need to write CPSR an extra time.
+ */
+ do {
+ enum armv4_5_mode mode = ARMV4_5_MODE_ANY;
+ unsigned i;
+
+ flushed = false;
+
+ /* write dirty non-{R0,CPSR} registers sharing the same mode */
+ for (i = max - 1, r = cache->reg_list + 1; i > 0; i--, r++) {
+ struct armv4_5_core_reg *reg;
+
+ if (!r->dirty || i == ARMV4_5_CPSR)
+ continue;
+ reg = r->arch_info;
+
/* TODO Check return values */
- cortex_a8_dap_write_coreregister_u32(target, value, i);
+
+ /* Pick a mode and update CPSR; else ignore this
+ * register if it's for a different mode than what
+ * we're handling on this pass.
+ *
+ * REVISIT don't distinguish SYS and USR modes.
+ *
+ * FIXME if we restore from FIQ mode, R8..R12 will
+ * get wrongly flushed onto FIQ shadows...
+ */
+ if (mode == ARMV4_5_MODE_ANY) {
+ mode = reg->mode;
+ if (mode != ARMV4_5_MODE_ANY) {
+ cortex_a8_dap_write_coreregister_u32(
+ target, mode, 16);
+ flush_cpsr = true;
+ }
+ } else if (mode != reg->mode)
+ continue;
+
+ /* Write this register */
+ value = buf_get_u32(r->value, 0, 32);
+ cortex_a8_dap_write_coreregister_u32(target, value,
+ (reg->num == 16) ? 17 : reg->num);
+ r->dirty = false;
+ flushed = true;
}
+
+ } while (flushed);
+
+ /* now flush CPSR if needed ... */
+ r = cache->reg_list + ARMV4_5_CPSR;
+ if (flush_cpsr || r->dirty) {
+ value = buf_get_u32(r->value, 0, 32);
+ cortex_a8_dap_write_coreregister_u32(target, value, 16);
+ r->dirty = false;
}
+ /* ... and R0 always (it was dirtied when we saved context) */
+ r = cache->reg_list + 0;
+ value = buf_get_u32(r->value, 0, 32);
+ cortex_a8_dap_write_coreregister_u32(target, value, 0);
+ r->dirty = false;
+
if (armv7a->post_restore_context)
armv7a->post_restore_context(target);
commit d7760352e8044e8eb8cd9b381574e34093e1f26f
Author: David Brownell <dbr...@us...>
Date: Thu Nov 19 19:03:02 2009 -0800
Cortex-A8: mode support
We *should* be able to read and write registers in any core mode,
instead of being stuck with whatever mode the core was when we
entered debug state. This patch makes them work.
Note that the current restore_context() only handles the current
mode; writing to other-mode registers is a NOP without a followup
patch fixing that. Also, that SPSR access needed some bugfixes;
it was confused with CPSR.
Secure monitor mode also seems dubious; there's probably more to
be done before that's sufficiently understood by the debugger.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index d02fee9..01b7aee 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -237,7 +237,7 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target,
struct armv7a_common *armv7a = target_to_armv7a(target);
struct swjdp_common *swjdp = &armv7a->swjdp_info;
- if (reg > 16)
+ if (reg > 17)
return retval;
if (reg < 15)
@@ -251,10 +251,12 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target,
cortex_a8_exec_opcode(target, 0xE1A0000F);
cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
}
- else if (reg == 16)
+ else
{
- /* "MRS r0, CPSR"; then move r0 to DCCTX */
- cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, 0));
+ /* "MRS r0, CPSR" or "MRS r0, SPSR"
+ * then move r0 to DCCTX
+ */
+ cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, reg & 1));
cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
}
@@ -268,11 +270,13 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target,
retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DTRTX, value);
+ LOG_DEBUG("read DCC 0x%08" PRIx32, *value);
return retval;
}
-static int cortex_a8_dap_write_coreregister_u32(struct target *target, uint32_t value, int regnum)
+static int cortex_a8_dap_write_coreregister_u32(struct target *target,
+ uint32_t value, int regnum)
{
int retval = ERROR_OK;
uint8_t Rd = regnum&0xFF;
@@ -292,29 +296,39 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, uint32_t
cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
}
- if (Rd > 16)
+ if (Rd > 17)
return retval;
/* Write to DCCRX */
+ LOG_DEBUG("write DCC 0x%08" PRIx32, value);
retval = mem_ap_write_u32(swjdp,
armv7a->debug_base + CPUDBG_DTRRX, value);
if (Rd < 15)
{
- /* DCCRX to Rd, MCR p14, 0, Rd, c0, c5, 0, 0xEE000E15 */
+ /* DCCRX to Rn, "MCR p14, 0, Rn, c0, c5, 0", 0xEE00nE15 */
cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0));
}
else if (Rd == 15)
{
+ /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
+ * then "mov r15, r0"
+ */
cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
cortex_a8_exec_opcode(target, 0xE1A0F000);
}
- else if (Rd == 16)
+ else
{
+ /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
+ * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
+ */
cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
- cortex_a8_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, 0));
- /* Execute a PrefetchFlush instruction through the ITR. */
- cortex_a8_exec_opcode(target, ARMV4_5_MCR(15, 0, 0, 7, 5, 4));
+ cortex_a8_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, Rd & 1));
+
+ /* "Prefetch flush" after modifying execution status in CPSR */
+ if (Rd == 16)
+ cortex_a8_exec_opcode(target,
+ ARMV4_5_MCR(15, 0, 0, 7, 5, 4));
}
return retval;
@@ -950,28 +964,64 @@ static int cortex_a8_store_core_reg_u32(struct target *target, int num,
#endif
+static int cortex_a8_write_core_reg(struct target *target, int num,
+ enum armv4_5_mode mode, uint32_t value);
+
static int cortex_a8_read_core_reg(struct target *target, int num,
enum armv4_5_mode mode)
{
uint32_t value;
int retval;
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct reg_cache *cache = armv4_5->core_cache;
+ uint32_t cpsr = 0;
+ unsigned cookie = num;
- /* FIXME cortex may not be in "mode" ... */
-
- cortex_a8_dap_read_coreregister_u32(target, &value, num);
+ /* avoid some needless mode changes
+ * FIXME move some of these to shared ARM code...
+ */
+ if (mode != armv4_5->core_mode) {
+ if ((armv4_5->core_mode == ARMV4_5_MODE_SYS)
+ && (mode == ARMV4_5_MODE_USR))
+ mode = ARMV4_5_MODE_ANY;
+ else if ((mode != ARMV4_5_MODE_FIQ) && (num <= 12))
+ mode = ARMV4_5_MODE_ANY;
+
+ if (mode != ARMV4_5_MODE_ANY) {
+ cpsr = buf_get_u32(cache ->reg_list[ARMV4_5_CPSR]
+ .value, 0, 32);
+ cortex_a8_write_core_reg(target, 16,
+ ARMV4_5_MODE_ANY, mode);
+ }
+ }
- if ((retval = jtag_execute_queue()) != ERROR_OK)
- {
- return retval;
+ if (num == 16) {
+ switch (mode) {
+ case ARMV4_5_MODE_USR:
+ case ARMV4_5_MODE_SYS:
+ case ARMV4_5_MODE_ANY:
+ /* CPSR */
+ break;
+ default:
+ /* SPSR */
+ cookie++;
+ break;
+ }
}
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
- buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
- mode, num).value, 0, 32, value);
+ cortex_a8_dap_read_coreregister_u32(target, &value, cookie);
+ retval = jtag_execute_queue();
+ if (retval == ERROR_OK) {
+ struct reg *r = &ARMV4_5_CORE_REG_MODE(cache, mode, num);
- return ERROR_OK;
+ r->valid = 1;
+ r->dirty = 0;
+ buf_set_u32(r->value, 0, 32, value);
+ }
+
+ if (cpsr)
+ cortex_a8_write_core_reg(target, 16, ARMV4_5_MODE_ANY, cpsr);
+ return retval;
}
static int cortex_a8_write_core_reg(struct target *target, int num,
@@ -979,19 +1029,55 @@ static int cortex_a8_write_core_reg(struct target *target, int num,
{
int retval;
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct reg_cache *cache = armv4_5->core_cache;
+ uint32_t cpsr = 0;
+ unsigned cookie = num;
- /* FIXME cortex may not be in "mode" ... */
+ /* avoid some needless mode changes
+ * FIXME move some of these to shared ARM code...
+ */
+ if (mode != armv4_5->core_mode) {
+ if ((armv4_5->core_mode == ARMV4_5_MODE_SYS)
+ && (mode == ARMV4_5_MODE_USR))
+ mode = ARMV4_5_MODE_ANY;
+ else if ((mode != ARMV4_5_MODE_FIQ) && (num <= 12))
+ mode = ARMV4_5_MODE_ANY;
+
+ if (mode != ARMV4_5_MODE_ANY) {
+ cpsr = buf_get_u32(cache ->reg_list[ARMV4_5_CPSR]
+ .value, 0, 32);
+ cortex_a8_write_core_reg(target, 16,
+ ARMV4_5_MODE_ANY, mode);
+ }
+ }
- cortex_a8_dap_write_coreregister_u32(target, value, num);
- if ((retval = jtag_execute_queue()) != ERROR_OK)
- {
- return retval;
+
+ if (num == 16) {
+ switch (mode) {
+ case ARMV4_5_MODE_USR:
+ case ARMV4_5_MODE_SYS:
+ case ARMV4_5_MODE_ANY:
+ /* CPSR */
+ break;
+ default:
+ /* SPSR */
+ cookie++;
+ break;
+ }
}
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
+ cortex_a8_dap_write_coreregister_u32(target, value, cookie);
+ if ((retval = jtag_execute_queue()) == ERROR_OK) {
+ struct reg *r = &ARMV4_5_CORE_REG_MODE(cache, mode, num);
- return ERROR_OK;
+ buf_set_u32(r->value, 0, 32, value);
+ r->valid = 1;
+ r->dirty = 0;
+ }
+
+ if (cpsr)
+ cortex_a8_write_core_reg(target, 16, ARMV4_5_MODE_ANY, cpsr);
+ return retval;
}
commit 71cde5e359f273585880ea8986709b950ba85b08
Author: David Brownell <dbr...@us...>
Date: Thu Nov 19 19:02:10 2009 -0800
target: create/use register_cache_invalidate()
Create a generic register_cache_invalidate(), and use it to
replace three all-but-identical core-specific routines:
- armv4_5_invalidate_core_regs()
- armv7m_invalidate_core_regs
- mips32_invalidate_core_regs() too.
Make cache->num_regs be unsigned, avoiding various errors.
Net code shrink and simplification.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index eb4b038..1c85417 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -1040,7 +1040,7 @@ int arm7_9_assert_reset(struct target *target)
target->state = TARGET_RESET;
jtag_add_sleep(50000);
- armv4_5_invalidate_core_regs(target);
+ register_cache_invalidate(arm7_9->armv4_5_common.core_cache);
if ((target->reset_halt) && ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0))
{
@@ -1224,10 +1224,7 @@ int arm7_9_soft_reset_halt(struct target *target)
}
/* all register content is now invalid */
- if ((retval = armv4_5_invalidate_core_regs(target)) != ERROR_OK)
- {
- return retval;
- }
+ register_cache_invalidate(armv4_5->core_cache);
/* SVC, ARM state, IRQ and FIQ disabled */
buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
@@ -1921,7 +1918,7 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand
if (!debug_execution)
{
/* registers are now invalid */
- armv4_5_invalidate_core_regs(target);
+ register_cache_invalidate(armv4_5->core_cache);
target->state = TARGET_RUNNING;
if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
{
@@ -2064,7 +2061,7 @@ int arm7_9_step(struct target *target, int current, uint32_t address, int handle
arm7_9->disable_single_step(target);
/* registers are now invalid */
- armv4_5_invalidate_core_regs(target);
+ register_cache_invalidate(armv4_5->core_cache);
if (err != ERROR_OK)
{
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 44e5b0a..f8ab153 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -436,22 +436,6 @@ static const struct reg_arch_type arm_reg_type = {
.set = armv4_5_set_core_reg,
};
-/** Marks the contents of the register cache as invalid (and clean). */
-int armv4_5_invalidate_core_regs(struct target *target)
-{
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
- unsigned num_regs = armv4_5->core_cache->num_regs;
- struct reg *reg = armv4_5->core_cache->reg_list;
-
- for (unsigned i = 0; i < num_regs; i++, reg++) {
- reg->valid = 0;
- reg->dirty = 0;
- }
-
- /* FIXME don't bother returning a value then */
- return ERROR_OK;
-}
-
struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *armv4_5_common)
{
int num_regs = ARRAY_SIZE(arm_core_regs);
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 50af57b..dbd62c0 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -162,8 +162,6 @@ int armv4_5_run_algorithm(struct target *target,
uint32_t entry_point, uint32_t exit_point,
int timeout_ms, void *arch_info);
-int armv4_5_invalidate_core_regs(struct target *target);
-
int arm_checksum_memory(struct target *target,
uint32_t address, uint32_t count, uint32_t *checksum);
int arm_blank_check_memory(struct target *target,
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index 56fbb05..88ff6f2 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -246,21 +246,6 @@ static int armv7m_write_core_reg(struct target *target, unsigned num)
return ERROR_OK;
}
-/** Invalidates cache of core registers set up by armv7m_build_reg_cache(). */
-int armv7m_invalidate_core_regs(struct target *target)
-{
- struct armv7m_common *armv7m = target_to_armv7m(target);
- int i;
-
- for (i = 0; i < armv7m->core_cache->num_regs; i++)
- {
- armv7m->core_cache->reg_list[i].valid = 0;
- armv7m->core_cache->reg_list[i].dirty = 0;
- }
-
- return ERROR_OK;
-}
-
/**
* Returns generic ARM userspace registers to GDB.
* GDB doesn't quite understand that most ARMs don't have floating point
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index c0a7466..d02fee9 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -545,7 +545,7 @@ static int cortex_a8_resume(struct target *target, int current,
target->state = TARGET_RUNNING;
/* registers are now invalid */
- armv4_5_invalidate_core_regs(target);
+ register_cache_invalidate(armv4_5->core_cache);
if (!debug_execution)
{
@@ -1182,11 +1182,12 @@ static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint
static int cortex_a8_assert_reset(struct target *target)
{
+ struct armv7a_common *armv7a = target_to_armv7a(target);
LOG_DEBUG(" ");
/* registers are now invalid */
- armv4_5_invalidate_core_regs(target);
+ register_cache_invalidate(armv7a->armv4_5_common.core_cache);
target->state = TARGET_RESET;
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index e7b5110..8279a8b 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -221,7 +221,7 @@ static int cortex_m3_endreset_event(struct target *target)
}
swjdp_transaction_endcheck(swjdp);
- armv7m_invalidate_core_regs(target);
+ register_cache_invalidate(cortex_m3->armv7m.core_cache);
/* make sure we have latest dhcsr flags */
mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
@@ -510,7 +510,7 @@ static int cortex_m3_soft_reset_halt(struct target *target)
target->state = TARGET_RESET;
/* registers are now invalid */
- armv7m_invalidate_core_regs(target);
+ register_cache_invalidate(cortex_m3->armv7m.core_cache);
while (timeout < 100)
{
@@ -617,7 +617,8 @@ static int cortex_m3_resume(struct target *target, int current,
target->debug_reason = DBG_REASON_NOTHALTED;
/* registers are now invalid */
- armv7m_invalidate_core_regs(target);
+ register_cache_invalidate(armv7m->core_cache);
+
if (!debug_execution)
{
target->state = TARGET_RUNNING;
@@ -673,7 +674,7 @@ static int cortex_m3_step(struct target *target, int current,
mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
/* registers are now invalid */
- armv7m_invalidate_core_regs(target);
+ register_cache_invalidate(cortex_m3->armv7m.core_cache);
if (breakpoint)
cortex_m3_set_breakpoint(target, breakpoint);
@@ -812,7 +813,7 @@ static int cortex_m3_assert_reset(struct target *target)
target->state = TARGET_RESET;
jtag_add_sleep(50000);
- armv7m_invalidate_core_regs(target);
+ register_cache_invalidate(cortex_m3->armv7m.core_cache);
if (target->reset_halt)
{
diff --git a/src/target/etm.c b/src/target/etm.c
index 85cc6eb..1678c2f 100644
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -234,7 +234,7 @@ static const struct reg_arch_type etm_scan6_type = {
static struct reg *etm_reg_lookup(struct etm_context *etm_ctx, unsigned id)
{
struct reg_cache *cache = etm_ctx->reg_cache;
- int i;
+ unsigned i;
for (i = 0; i < cache->num_regs; i++) {
struct etm_reg *reg = cache->reg_list[i].arch_info;
diff --git a/src/target/mips32.c b/src/target/mips32.c
index f986079..0b8ebb4 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -175,21 +175,6 @@ int mips32_write_core_reg(struct target *target, int num)
return ERROR_OK;
}
-int mips32_invalidate_core_regs(struct target *target)
-{
- /* get pointers to arch-specific information */
- struct mips32_common *mips32 = target->arch_info;
- int i;
-
- for (i = 0; i < mips32->core_cache->num_regs; i++)
- {
- mips32->core_cache->reg_list[i].valid = 0;
- mips32->core_cache->reg_list[i].dirty = 0;
- }
-
- return ERROR_OK;
-}
-
int mips32_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
{
/* get pointers to arch-specific information */
diff --git a/src/target/mips32.h b/src/target/mips32.h
index 1ac682b..7d1928e 100644
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -147,7 +147,6 @@ int mips32_examine(struct target *target);
int mips32_register_commands(struct command_context *cmd_ctx);
-int mips32_invalidate_core_regs(struct target *target);
int mips32_get_gdb_reg_list(struct target *target,
struct reg **reg_list[], int *reg_list_size);
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index 864ede0..0a566c3 100644
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -309,7 +309,7 @@ int mips_m4k_assert_reset(struct target *target)
target->state = TARGET_RESET;
jtag_add_sleep(50000);
- mips32_invalidate_core_regs(target);
+ register_cache_invalidate(mips32->core_cache);
if (target->reset_halt)
{
@@ -410,7 +410,7 @@ int mips_m4k_resume(struct target *target, int current, uint32_t address, int ha
target->debug_reason = DBG_REASON_NOTHALTED;
/* registers are now invalid */
- mips32_invalidate_core_regs(target);
+ register_cache_invalidate(mips32->core_cache);
if (!debug_execution)
{
@@ -467,7 +467,7 @@ int mips_m4k_step(struct target *target, int current, uint32_t address, int hand
mips_ejtag_exit_debug(ejtag_info);
/* registers are now invalid */
- mips32_invalidate_core_regs(target);
+ register_cache_invalidate(mips32->core_cache);
if (breakpoint)
mips_m4k_set_breakpoint(target, breakpoint);
diff --git a/src/target/register.c b/src/target/register.c
index d9ef53e..392455d 100644
--- a/src/target/register.c
+++ b/src/target/register.c
@@ -28,11 +28,20 @@
#include "register.h"
#include "log.h"
+/**
+ * @file
+ * Holds utilities to work with register caches.
+ *
+ * OpenOCD uses machine registers internally, and exposes them by name
+ * to Tcl scripts. Sets of related registers are grouped into caches.
+ * For example, a CPU core will expose a set of registers, and there
+ * may be separate registers associated with debug or trace modules.
+ */
struct reg* register_get_by_name(struct reg_cache *first,
const char *name, bool search_all)
{
- int i;
+ unsigned i;
struct reg_cache *cache = first;
while (cache)
@@ -65,6 +74,17 @@ struct reg_cache** register_get_last_cache_p(struct reg_cache **first)
return cache_p;
}
+/** Marks the contents of the register cache as invalid (and clean). */
+void register_cache_invalidate(struct reg_cache *cache)
+{
+ struct reg *reg = cache->reg_list;
+
+ for (unsigned n = cache->num_regs; n != 0; n--, reg++) {
+ reg->valid = 0;
+ reg->dirty = 0;
+ }
+}
+
static int register_get_dummy_core_reg(struct reg *reg)
{
return ERROR_OK;
diff --git a/src/target/register.h b/src/target/register.h
index c14dfd4..0f8f2f4 100644
--- a/src/target/register.h
+++ b/src/target/register.h
@@ -41,7 +41,7 @@ struct reg_cache
char *name;
struct reg_cache *next;
struct reg *reg_list;
- int num_regs;
+ unsigned num_regs;
};
struct reg_arch_type
@@ -53,6 +53,7 @@ struct reg_arch_type
struct reg* register_get_by_name(struct reg_cache *first,
const char *name, bool search_all);
struct reg_cache** register_get_last_cache_p(struct reg_cache **first);
+void register_cache_invalidate(struct reg_cache *cache);
void register_init_dummy(struct reg *reg);
diff --git a/src/target/target.c b/src/target/target.c
index f203913..70fd8f2 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -1860,7 +1860,7 @@ COMMAND_HANDLER(handle_reg_command)
{
struct target *target;
struct reg *reg = NULL;
- int count = 0;
+ unsigned count = 0;
char *value;
LOG_DEBUG("-");
@@ -1875,7 +1875,7 @@ COMMAND_HANDLER(handle_reg_command)
count = 0;
while (cache)
{
- int i;
+ unsigned i;
command_print(CMD_CTX, "===== %s", cache->name);
@@ -1917,10 +1917,10 @@ COMMAND_HANDLER(handle_reg_command)
count = 0;
while (cache)
{
- int i;
+ unsigned i;
for (i = 0; i < cache->num_regs; i++)
{
- if (count++ == (int)num)
+ if (count++ == num)
{
reg = &cache->reg_list[i];
break;
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 28f89f1..f13366a 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -1322,7 +1322,7 @@ static int xscale_resume(struct target *target, int current,
if (!debug_execution)
{
/* registers are now invalid */
- armv4_5_invalidate_core_regs(target);
+ register_cache_invalidate(armv4_5->core_cache);
target->state = TARGET_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
}
@@ -1401,8 +1401,7 @@ static int xscale_step_inner(struct target *target, int current,
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
/* registers are now invalid */
- if ((retval = armv4_5_invalidate_core_regs(target)) != ERROR_OK)
- return retval;
+ register_cache_invalidate(armv4_5->core_cache);
/* wait for and process debug entry */
if ((retval = xscale_debug_entry(target)) != ERROR_OK)
@@ -1538,7 +1537,7 @@ static int xscale_deassert_reset(struct target *target)
breakpoint = breakpoint->next;
}
- armv4_5_invalidate_core_regs(target);
+ register_cache_invalidate(xscale->armv4_5_common.core_cache);
/* FIXME mark hardware watchpoints got unset too. Also,
* at least some of the XScale registers are invalid...
-----------------------------------------------------------------------
Summary of changes:
src/target/arm7_9_common.c | 11 +--
src/target/armv4_5.c | 16 ---
src/target/armv4_5.h | 2 -
src/target/armv7m.c | 15 ---
src/target/cortex_a8.c | 231 +++++++++++++++++++++++++++++++++++---------
src/target/cortex_m3.c | 11 +-
src/target/etm.c | 2 +-
src/target/mips32.c | 15 ---
src/target/mips32.h | 1 -
src/target/mips_m4k.c | 6 +-
src/target/register.c | 22 ++++-
src/target/register.h | 3 +-
src/target/target.c | 8 +-
src/target/xscale.c | 7 +-
14 files changed, 230 insertions(+), 120 deletions(-)
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