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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-459-g181d401
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From: David B. <dbr...@us...> - 2009-11-18 08:50:45
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- Log -----------------------------------------------------------------
commit 181d401d59419ec2f5a5d89e2600d9a6dbf8f9ed
Author: David Brownell <dbr...@us...>
Date: Tue Nov 17 23:50:26 2009 -0800
ARM: add is_arm_mode()
Add a new is_arm_mode() predicate, and use it to replace almost
all calls to current armv4_5_mode_to_number().
Eventually those internal mode numbers should vanish... along
with their siblings in the armv7a.c file.
Remove a handful of superfluous checks ... e.g. the mode number
was just initialized, or (debug entry methods) already validated.
Move one of the macros using internal mode numbers into the only
file which uses that macro. Make the tables manipulated with
those numbers be read-only and, where possible, static so they're
not confused with part of the generic ARM interface.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/arm11.c b/src/target/arm11.c
index 5e73275..3a23585 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -1603,7 +1603,7 @@ static int arm11_run_algorithm(struct target *target,
}
// FIXME
-// if (armv4_5_mode_to_number(arm11->core_mode)==-1)
+// if (!is_arm_mode(arm11->core_mode))
// return ERROR_FAIL;
// Save regs
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index ff95a0c..37aa066 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -1242,9 +1242,6 @@ int arm7_9_soft_reset_halt(struct target *target)
armv4_5->core_mode = ARMV4_5_MODE_SVC;
armv4_5->core_state = ARMV4_5_STATE_ARM;
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
- return ERROR_FAIL;
-
/* reset registers */
for (i = 0; i <= 14; i++)
{
@@ -1413,7 +1410,7 @@ static int arm7_9_debug_entry(struct target *target)
armv4_5->core_mode = cpsr & 0x1f;
- if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
+ if (!is_arm_mode(armv4_5->core_mode))
{
target->state = TARGET_UNKNOWN;
LOG_ERROR("cpsr contains invalid mode value - communication failure");
@@ -1439,9 +1436,6 @@ static int arm7_9_debug_entry(struct target *target)
else
context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
- return ERROR_FAIL;
-
for (i = 0; i <= 15; i++)
{
LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]);
@@ -1452,9 +1446,6 @@ static int arm7_9_debug_entry(struct target *target)
LOG_DEBUG("entered debug state at PC 0x%" PRIx32 "", context[15]);
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
- return ERROR_FAIL;
-
/* exceptions other than USR & SYS have a saved program status register */
if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
{
@@ -1506,7 +1497,7 @@ int arm7_9_full_context(struct target *target)
return ERROR_TARGET_NOT_HALTED;
}
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+ if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
/* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
@@ -1606,7 +1597,7 @@ int arm7_9_restore_context(struct target *target)
if (arm7_9->pre_restore_context)
arm7_9->pre_restore_context(target);
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+ if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
/* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
@@ -2104,7 +2095,7 @@ int arm7_9_read_core_reg(struct target *target, int num, enum armv4_5_mode mode)
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+ if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
enum armv4_5_mode reg_mode = ((struct armv4_5_core_reg*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
@@ -2168,7 +2159,7 @@ int arm7_9_write_core_reg(struct target *target, int num, enum armv4_5_mode mode
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+ if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
enum armv4_5_mode reg_mode = ((struct armv4_5_core_reg*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
@@ -2373,7 +2364,7 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u
break;
}
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+ if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
for (i = 0; i <= last_reg; i++)
@@ -2556,7 +2547,7 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size,
buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
embeddedice_store_reg(dbg_ctrl);
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+ if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
for (i = 0; i <= last_reg; i++)
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index e1dcea7..29f7917 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -244,7 +244,7 @@ static int arm920t_read_cp15_interpreted(struct target *target,
LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value);
#endif
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+ if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
@@ -284,7 +284,7 @@ int arm920t_write_cp15_interpreted(struct target *target,
LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address);
#endif
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+ if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
@@ -889,7 +889,7 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
fclose(output);
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+ if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
/* mark registers dirty. */
@@ -1172,7 +1172,7 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
fclose(output);
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+ if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
/* mark registers dirty */
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 6864efb..d22e0f3 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -36,7 +36,7 @@
#include "register.h"
-char* armv4_5_core_reg_list[] =
+static const char *armv4_5_core_reg_list[] =
{
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13_usr", "lr_usr", "pc",
@@ -101,9 +101,7 @@ static const struct {
/** Map PSR mode bits to the name of an ARM processor operating mode. */
const char *arm_mode_name(unsigned psr_mode)
{
- unsigned i;
-
- for (i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
+ for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
if (arm_mode_data[i].psr == psr_mode)
return arm_mode_data[i].name;
}
@@ -111,7 +109,17 @@ const char *arm_mode_name(unsigned psr_mode)
return "UNRECOGNIZED";
}
-/** Map PSR mode bits to linear number */
+/** Return true iff the parameter denotes a valid ARM processor mode. */
+bool is_arm_mode(unsigned psr_mode)
+{
+ for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
+ if (arm_mode_data[i].psr == psr_mode)
+ return true;
+ }
+ return false;
+}
+
+/** Map PSR mode bits to linear number indexing armv4_5_core_reg_map */
int armv4_5_mode_to_number(enum armv4_5_mode mode)
{
switch (mode) {
@@ -137,7 +145,7 @@ int armv4_5_mode_to_number(enum armv4_5_mode mode)
}
}
-/** Map linear number to PSR mode bits. */
+/** Map linear number indexing armv4_5_core_reg_map to PSR mode bits. */
enum armv4_5_mode armv4_5_number_to_mode(int number)
{
switch (number) {
@@ -166,7 +174,7 @@ char* armv4_5_state_strings[] =
"ARM", "Thumb", "Jazelle"
};
-struct armv4_5_core_reg armv4_5_core_reg_list_arch_info[] =
+static const struct armv4_5_core_reg armv4_5_core_reg_list_arch_info[] =
{
{0, ARMV4_5_MODE_ANY, NULL, NULL},
{1, ARMV4_5_MODE_ANY, NULL, NULL},
@@ -214,7 +222,7 @@ struct armv4_5_core_reg armv4_5_core_reg_list_arch_info[] =
};
/* map core mode (USR, FIQ, ...) and register number to indizes into the register cache */
-int armv4_5_core_reg_map[7][17] =
+const int armv4_5_core_reg_map[7][17] =
{
{ /* USR */
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
@@ -383,7 +391,7 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm
arch_info[i] = armv4_5_core_reg_list_arch_info[i];
arch_info[i].target = target;
arch_info[i].armv4_5_common = armv4_5_common;
- reg_list[i].name = armv4_5_core_reg_list[i];
+ reg_list[i].name = (char *) armv4_5_core_reg_list[i];
reg_list[i].size = 32;
reg_list[i].value = calloc(1, 4);
reg_list[i].dirty = 0;
@@ -415,6 +423,9 @@ int armv4_5_arch_state(struct target *target)
return ERROR_OK;
}
+#define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
+ cache->reg_list[armv4_5_core_reg_map[mode][num]]
+
COMMAND_HANDLER(handle_armv4_5_reg_command)
{
char output[128];
@@ -435,7 +446,7 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
return ERROR_OK;
}
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+ if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
if (!armv4_5->full_context) {
@@ -599,7 +610,7 @@ int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
int i;
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+ if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
*reg_list_size = 26;
@@ -679,7 +690,7 @@ int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struc
return ERROR_TARGET_NOT_HALTED;
}
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+ if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
/* armv5 and later can terminate with BKPT instruction; less overhead */
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 5b7a522..81eac47 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -42,6 +42,8 @@ typedef enum armv4_5_mode
} armv4_5_mode_t;
const char *arm_mode_name(unsigned psr_mode);
+bool is_arm_mode(unsigned psr_mode);
+
int armv4_5_mode_to_number(enum armv4_5_mode mode);
enum armv4_5_mode armv4_5_number_to_mode(int number);
@@ -54,12 +56,10 @@ typedef enum armv4_5_state
extern char* armv4_5_state_strings[];
-extern int armv4_5_core_reg_map[7][17];
+extern const int armv4_5_core_reg_map[7][17];
#define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
-#define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
- cache->reg_list[armv4_5_core_reg_map[mode][num]]
/* offsets into armv4_5 core register cache */
enum
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 38928f4..09e6825 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -954,7 +954,7 @@ static int xscale_debug_entry(struct target *target)
LOG_DEBUG("cpsr: 0x%8.8" PRIx32 "", buffer[9]);
armv4_5->core_mode = buffer[9] & 0x1f;
- if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
+ if (!is_arm_mode(armv4_5->core_mode))
{
target->state = TARGET_UNKNOWN;
LOG_ERROR("cpsr contains invalid mode value - communication failure");
@@ -969,9 +969,6 @@ static int xscale_debug_entry(struct target *target)
armv4_5->core_state = ARMV4_5_STATE_ARM;
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
- return ERROR_FAIL;
-
/* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
{
commit ec93209f51afc09e273a4742dc0b5f2cefc15e76
Author: David Brownell <dbr...@us...>
Date: Tue Nov 17 23:50:23 2009 -0800
ARM: add arm_mode_name()
Add and use arm_mode_name() to map from PSR bits to user
meaningful names. It uses a new table which, later, can
be used to hold other mode-coupled data.
Add definitions for the "Secure Monitor" mode, as seen on
some ARM11 cores (like ARM1176) and on Cortex-A8. The
previous mode name scheme didn't understand that mode.
Remove the old mechanism ... there were two copies, caused
by Cortex-A8 needing to add "Secure Monitor" mode support.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index b51f969..a6c7cc7 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -239,7 +239,7 @@ static int arm720t_arch_state(struct target *target)
"MMU: %s, Cache: %s",
armv4_5_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
- armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
+ arm_mode_name(armv4_5->core_mode),
buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
state[arm720t->armv4_5_mmu.mmu_enabled],
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index b29eb5c..ff95a0c 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -1420,7 +1420,8 @@ static int arm7_9_debug_entry(struct target *target)
return ERROR_TARGET_FAILURE;
}
- LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
+ LOG_DEBUG("target entered debug state in %s mode",
+ arm_mode_name(armv4_5->core_mode));
if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
{
@@ -1613,7 +1614,8 @@ int arm7_9_restore_context(struct target *target)
*/
for (i = 0; i < 6; i++)
{
- LOG_DEBUG("examining %s mode", armv4_5_mode_strings[i]);
+ LOG_DEBUG("examining %s mode",
+ arm_mode_name(armv4_5->core_mode));
dirty = 0;
mode_change = 0;
/* check if there are dirty registers in the current mode
@@ -1675,7 +1677,10 @@ int arm7_9_restore_context(struct target *target)
num_regs++;
reg->dirty = 0;
reg->valid = 1;
- LOG_DEBUG("writing register %i of mode %s with value 0x%8.8" PRIx32 "", j, armv4_5_mode_strings[i], regs[j]);
+ LOG_DEBUG("writing register %i mode %s "
+ "with value 0x%8.8" PRIx32, j,
+ arm_mode_name(armv4_5->core_mode),
+ regs[j]);
}
}
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 99b4bbd..e1dcea7 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -451,7 +451,7 @@ int arm920t_arch_state(struct target *target)
"MMU: %s, D-Cache: %s, I-Cache: %s",
armv4_5_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
- armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
+ arm_mode_name(armv4_5->core_mode),
buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
state[arm920t->armv4_5_mmu.mmu_enabled],
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index cc6318b..27eb752 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -509,7 +509,7 @@ int arm926ejs_arch_state(struct target *target)
"MMU: %s, D-Cache: %s, I-Cache: %s",
armv4_5_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason,target->debug_reason)->name,
- armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
+ arm_mode_name(armv4_5->core_mode),
buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
state[arm926ejs->armv4_5_mmu.mmu_enabled],
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index aba4431..6864efb 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -53,13 +53,63 @@ char* armv4_5_core_reg_list[] =
"cpsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_abt", "spsr_und"
};
-static const char *armv4_5_mode_strings_list[] =
-{
- "Illegal mode value", "User", "FIQ", "IRQ", "Supervisor", "Abort", "Undefined", "System"
+static const struct {
+ const char *name;
+ unsigned psr;
+} arm_mode_data[] = {
+ /* Seven modes are standard from ARM7 on. "System" and "User" share
+ * the same registers; other modes shadow from 3 to 8 registers.
+ */
+ {
+ .name = "User",
+ .psr = ARMV4_5_MODE_USR,
+ },
+ {
+ .name = "FIQ",
+ .psr = ARMV4_5_MODE_FIQ,
+ },
+ {
+ .name = "Supervisor",
+ .psr = ARMV4_5_MODE_SVC,
+ },
+ {
+ .name = "Abort",
+ .psr = ARMV4_5_MODE_ABT,
+ },
+ {
+ .name = "IRQ",
+ .psr = ARMV4_5_MODE_IRQ,
+ },
+ {
+ .name = "Undefined" /* instruction */,
+ .psr = ARMV4_5_MODE_UND,
+ },
+ {
+ .name = "System",
+ .psr = ARMV4_5_MODE_SYS,
+ },
+ /* TrustZone "Security Extensions" add a secure monitor mode.
+ * This is distinct from a "debug monitor" which can support
+ * non-halting debug, in conjunction with some debuggers.
+ */
+ {
+ .name = "Secure Monitor",
+ .psr = ARM_MODE_MON,
+ },
};
-/* Hack! Yuk! allow -1 index, which simplifies codepaths elsewhere in the code */
-const char **armv4_5_mode_strings = armv4_5_mode_strings_list + 1;
+/** Map PSR mode bits to the name of an ARM processor operating mode. */
+const char *arm_mode_name(unsigned psr_mode)
+{
+ unsigned i;
+
+ for (i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
+ if (arm_mode_data[i].psr == psr_mode)
+ return arm_mode_data[i].name;
+ }
+ LOG_ERROR("unrecognized psr mode: %#02x", psr_mode);
+ return "UNRECOGNIZED";
+}
/** Map PSR mode bits to linear number */
int armv4_5_mode_to_number(enum armv4_5_mode mode)
@@ -282,7 +332,8 @@ int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
if (armv4_5_target->core_mode != (enum armv4_5_mode)(value & 0x1f))
{
- LOG_DEBUG("changing ARM core mode to '%s'", armv4_5_mode_strings[armv4_5_mode_to_number(value & 0x1f)]);
+ LOG_DEBUG("changing ARM core mode to '%s'",
+ arm_mode_name(value & 0x1f));
armv4_5_target->core_mode = value & 0x1f;
armv4_5_target->write_core_reg(target, 16, ARMV4_5_MODE_ANY, value);
}
@@ -357,7 +408,7 @@ int armv4_5_arch_state(struct target *target)
LOG_USER("target halted in %s state due to %s, current mode: %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
armv4_5_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
- armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
+ arm_mode_name(armv4_5->core_mode),
buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index d126f96..5b7a522 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -35,16 +35,16 @@ typedef enum armv4_5_mode
ARMV4_5_MODE_IRQ = 18,
ARMV4_5_MODE_SVC = 19,
ARMV4_5_MODE_ABT = 23,
+ ARM_MODE_MON = 26,
ARMV4_5_MODE_UND = 27,
ARMV4_5_MODE_SYS = 31,
ARMV4_5_MODE_ANY = -1
} armv4_5_mode_t;
+const char *arm_mode_name(unsigned psr_mode);
int armv4_5_mode_to_number(enum armv4_5_mode mode);
enum armv4_5_mode armv4_5_number_to_mode(int number);
-extern const char **armv4_5_mode_strings;
-
typedef enum armv4_5_state
{
ARMV4_5_STATE_ARM,
diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index 1518674..e13b33b 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -47,15 +47,6 @@ char* armv7a_core_reg_list[] =
"r13_mon", "lr_mon", "spsr_mon"
};
-char * armv7a_mode_strings_list[] =
-{
- "Illegal mode value", "User", "FIQ", "IRQ",
- "Supervisor", "Abort", "Undefined", "System", "Monitor"
-};
-
-/* Hack! Yuk! allow -1 index, which simplifies codepaths elsewhere in the code */
-char** armv7a_mode_strings = armv7a_mode_strings_list+1;
-
char* armv7a_state_strings[] =
{
"ARM", "Thumb", "Jazelle", "ThumbEE"
@@ -183,8 +174,7 @@ int armv7a_arch_state(struct target *target)
armv7a_state_strings[armv7a->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason,
target->debug_reason)->name,
- armv7a_mode_strings[
- armv7a_mode_to_number(armv4_5->core_mode)],
+ arm_mode_name(armv4_5->core_mode),
armv7a_core_reg_list[armv7a_core_reg_map[
armv7a_mode_to_number(armv4_5->core_mode)][16]],
buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 4d29ef9..e781e72 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -37,8 +37,6 @@ typedef enum armv7a_mode
ARMV7A_MODE_ANY = -1
} armv7a_t;
-extern char **armv7a_mode_strings;
-
typedef enum armv7a_state
{
ARMV7A_STATE_ARM,
diff --git a/src/target/xscale.c b/src/target/xscale.c
index a4a8eab..38928f4 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -857,7 +857,7 @@ static int xscale_arch_state(struct target *target)
"%s",
armv4_5_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
- armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
+ arm_mode_name(armv4_5->core_mode),
buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
state[xscale->armv4_5_mmu.mmu_enabled],
@@ -960,7 +960,8 @@ static int xscale_debug_entry(struct target *target)
LOG_ERROR("cpsr contains invalid mode value - communication failure");
return ERROR_TARGET_FAILURE;
}
- LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
+ LOG_DEBUG("target entered debug state in %s mode",
+ arm_mode_name(armv4_5->core_mode));
if (buffer[9] & 0x20)
armv4_5->core_state = ARMV4_5_STATE_THUMB;
commit d6c8945662e6027f6ba12d73bac2473088672db5
Author: David Brownell <dbr...@us...>
Date: Tue Nov 17 23:50:17 2009 -0800
ARM: only use one set of dummy FPA registers
All ARM cores need to provide obsolete FPA registers in their
GDB register dumps. (Even though cores with floating point
support now generally use some version of VFP...)
Clean up that support a bit by sharing the same dummy registers,
and removing the duplicate copies. Eventually we shouldn't need
to export those dummies.
(This makes the ARMv7-M support include the armv4_5 header, and
cleans up related #includes, but doesn't yet use anything from
there except those dummies.)
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/flash/lpc2000.c b/src/flash/lpc2000.c
index 191eb4b..5442e71 100644
--- a/src/flash/lpc2000.c
+++ b/src/flash/lpc2000.c
@@ -26,7 +26,6 @@
#endif
#include "lpc2000.h"
-#include "armv4_5.h"
#include "armv7m.h"
#include "binarybuffer.h"
#include "algorithm.h"
diff --git a/src/target/arm11.c b/src/target/arm11.c
index 65e0780..5e73275 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -246,36 +246,6 @@ enum arm11_regcache_ids
#define ARM11_GDB_REGISTER_COUNT 26
-/* FIXME these are *identical* to the ARMv4_5 dummies ... except
- * for their names, and being static vs global, and having different
- * addresses. Ditto ARMv7a and ARMv7m dummies.
- */
-
-static uint8_t arm11_gdb_dummy_fp_value[12];
-
-static struct reg arm11_gdb_dummy_fp_reg =
-{
- .name = "GDB dummy floating-point register",
- .value = arm11_gdb_dummy_fp_value,
- .dirty = 0,
- .valid = 1,
- .size = 96,
- .arch_info = NULL,
-};
-
-static uint8_t arm11_gdb_dummy_fps_value[4];
-
-static struct reg arm11_gdb_dummy_fps_reg =
-{
- .name = "GDB dummy floating-point status register",
- .value = arm11_gdb_dummy_fps_value,
- .dirty = 0,
- .valid = 1,
- .size = 32,
- .arch_info = NULL,
-};
-
-
static int arm11_on_enter_debug_state(struct arm11_common *arm11);
static int arm11_step(struct target *target, int current,
uint32_t address, int handle_breakpoints);
@@ -1265,12 +1235,10 @@ static int arm11_get_gdb_reg_list(struct target *target,
*reg_list_size = ARM11_GDB_REGISTER_COUNT;
*reg_list = malloc(sizeof(struct reg*) * ARM11_GDB_REGISTER_COUNT);
+ /* nine unused legacy FPA registers are expected by GDB */
for (size_t i = 16; i < 24; i++)
- {
- (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
- }
-
- (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
+ (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
+ (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
{
@@ -1954,9 +1922,6 @@ static int arm11_build_reg_cache(struct target *target)
NEW(struct reg, reg_list, ARM11_REGCACHE_COUNT);
NEW(struct arm11_reg_state, arm11_reg_states, ARM11_REGCACHE_COUNT);
- register_init_dummy(&arm11_gdb_dummy_fp_reg);
- register_init_dummy(&arm11_gdb_dummy_fps_reg);
-
arm11->reg_list = reg_list;
/* Build the process context cache */
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 6f8d14c..aba4431 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -189,30 +189,44 @@ int armv4_5_core_reg_map[7][17] =
}
};
-uint8_t armv4_5_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const uint8_t arm_gdb_dummy_fp_value[12];
-struct reg armv4_5_gdb_dummy_fp_reg =
+/**
+ * Dummy FPA registers are required to support GDB on ARM.
+ * Register packets require eight obsolete FPA register values.
+ * Modern ARM cores use Vector Floating Point (VFP), if they
+ * have any floating point support. VFP is not FPA-compatible.
+ */
+struct reg arm_gdb_dummy_fp_reg =
{
- .name = "GDB dummy floating-point register",
- .value = armv4_5_gdb_dummy_fp_value,
- .dirty = 0,
+ .name = "GDB dummy FPA register",
+ .value = (uint8_t *) arm_gdb_dummy_fp_value,
.valid = 1,
.size = 96,
- .arch_info = NULL,
};
-uint8_t armv4_5_gdb_dummy_fps_value[] = {0, 0, 0, 0};
+static const uint8_t arm_gdb_dummy_fps_value[4];
-struct reg armv4_5_gdb_dummy_fps_reg =
+/**
+ * Dummy FPA status registers are required to support GDB on ARM.
+ * Register packets require an obsolete FPA status register.
+ */
+struct reg arm_gdb_dummy_fps_reg =
{
- .name = "GDB dummy floating-point status register",
- .value = armv4_5_gdb_dummy_fps_value,
- .dirty = 0,
+ .name = "GDB dummy FPA status register",
+ .value = (uint8_t *) arm_gdb_dummy_fps_value,
.valid = 1,
.size = 32,
- .arch_info = NULL,
};
+static void arm_gdb_dummy_init(void) __attribute__ ((constructor));
+
+static void arm_gdb_dummy_init(void)
+{
+ register_init_dummy(&arm_gdb_dummy_fp_reg);
+ register_init_dummy(&arm_gdb_dummy_fps_reg);
+}
+
int armv4_5_get_core_reg(struct reg *reg)
{
int retval;
@@ -313,9 +327,6 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm
cache->reg_list = reg_list;
cache->num_regs = num_regs;
- register_init_dummy(&armv4_5_gdb_dummy_fp_reg);
- register_init_dummy(&armv4_5_gdb_dummy_fps_reg);
-
for (i = 0; i < 37; i++)
{
arch_info[i] = armv4_5_core_reg_list_arch_info[i];
@@ -550,10 +561,10 @@ int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int
for (i = 16; i < 24; i++)
{
- (*reg_list)[i] = &armv4_5_gdb_dummy_fp_reg;
+ (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
}
- (*reg_list)[24] = &armv4_5_gdb_dummy_fps_reg;
+ (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
(*reg_list)[25] = &armv4_5->core_cache->reg_list[ARMV4_5_CPSR];
return ERROR_OK;
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 5fef094..d126f96 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -158,6 +158,8 @@ int arm_checksum_memory(struct target *target,
int arm_blank_check_memory(struct target *target,
uint32_t address, uint32_t count, uint32_t *blank);
+extern struct reg arm_gdb_dummy_fp_reg;
+extern struct reg arm_gdb_dummy_fps_reg;
/* ARM mode instructions
*/
diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index 8f90dd3..1518674 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -144,21 +144,6 @@ int armv7a_core_reg_map[8][17] =
}
};
-/* FIXME this dummy is IDENTICAL to the armv4_5, arm11, and armv7m
- * ones... except for naming/scoping
- */
-uint8_t armv7a_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
-
-struct reg armv7a_gdb_dummy_fp_reg =
-{
- .name = "GDB dummy floating-point register",
- .value = armv7a_gdb_dummy_fp_value,
- .dirty = 0,
- .valid = 1,
- .size = 96,
- .arch_info = NULL,
-};
-
void armv7a_show_fault_registers(struct target *target)
{
uint32_t dfsr, ifsr, dfar, ifar;
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index 862261d..56fbb05 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -35,7 +35,6 @@
#endif
#include "breakpoints.h"
-#include "target.h"
#include "armv7m.h"
#include "algorithm.h"
#include "register.h"
@@ -59,33 +58,6 @@ static char *armv7m_exception_strings[] =
"DebugMonitor", "RESERVED", "PendSV", "SysTick"
};
-/* FIXME these dummies are IDENTICAL to the armv4_5, arm11, and armv7a
- * ones... except for naming/scoping
- */
-static uint8_t armv7m_gdb_dummy_fp_value[12];
-
-static struct reg armv7m_gdb_dummy_fp_reg =
-{
- .name = "GDB dummy floating-point register",
- .value = armv7m_gdb_dummy_fp_value,
- .dirty = 0,
- .valid = 1,
- .size = 96,
- .arch_info = NULL,
-};
-
-static uint8_t armv7m_gdb_dummy_fps_value[4];
-
-static struct reg armv7m_gdb_dummy_fps_reg =
-{
- .name = "GDB dummy floating-point status register",
- .value = armv7m_gdb_dummy_fps_value,
- .dirty = 0,
- .valid = 1,
- .size = 32,
- .arch_info = NULL,
-};
-
#ifdef ARMV7_GDB_HACKS
uint8_t armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0};
@@ -316,11 +288,8 @@ int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int
}
for (i = 16; i < 24; i++)
- {
- (*reg_list)[i] = &armv7m_gdb_dummy_fp_reg;
- }
-
- (*reg_list)[24] = &armv7m_gdb_dummy_fps_reg;
+ (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
+ (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
#ifdef ARMV7_GDB_HACKS
/* use dummy cpsr reg otherwise gdb may try and set the thumb bit */
@@ -553,11 +522,9 @@ struct reg_cache *armv7m_build_reg_cache(struct target *target)
struct armv7m_core_reg *arch_info = calloc(num_regs, sizeof(struct armv7m_core_reg));
int i;
- register_init_dummy(&armv7m_gdb_dummy_fps_reg);
#ifdef ARMV7_GDB_HACKS
register_init_dummy(&armv7m_gdb_dummy_cpsr_reg);
#endif
- register_init_dummy(&armv7m_gdb_dummy_fp_reg);
/* Build the process context cache */
cache->name = "arm v7m registers";
diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index dba9a3b..9dd4ddb 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -27,6 +27,7 @@
#define ARMV7M_COMMON_H
#include "arm_adi_v5.h"
+#include "armv4_5.h"
/* define for enabling armv7 gdb workarounds */
#if 1
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index c9938c9..42f8ee0 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -334,6 +334,9 @@ static int cortex_m3_debug_entry(struct target *target)
xPSR = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32);
#ifdef ARMV7_GDB_HACKS
+ /* FIXME this breaks on scan chains with more than one Cortex-M3.
+ * Instead, each CM3 should have its own dummy value...
+ */
/* copy real xpsr reg for gdb, setting thumb bit */
buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR);
buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1);
diff --git a/src/target/cortex_m3.h b/src/target/cortex_m3.h
index 759c2bc..7ce8901 100644
--- a/src/target/cortex_m3.h
+++ b/src/target/cortex_m3.h
@@ -26,7 +26,6 @@
#ifndef CORTEX_M3_H
#define CORTEX_M3_H
-#include "target.h"
#include "armv7m.h"
-----------------------------------------------------------------------
Summary of changes:
src/flash/lpc2000.c | 1 -
src/target/arm11.c | 43 +------------
src/target/arm720t.c | 2 +-
src/target/arm7_9_common.c | 34 +++++------
src/target/arm920t.c | 10 ++--
src/target/arm926ejs.c | 2 +-
src/target/armv4_5.c | 139 +++++++++++++++++++++++++++++++++----------
src/target/armv4_5.h | 12 ++--
src/target/armv7a.c | 27 +--------
src/target/armv7a.h | 2 -
src/target/armv7m.c | 37 +-----------
src/target/armv7m.h | 1 +
src/target/cortex_m3.c | 3 +
src/target/cortex_m3.h | 1 -
src/target/xscale.c | 10 +--
15 files changed, 150 insertions(+), 174 deletions(-)
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