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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-429-g56adbaf
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From: David B. <dbr...@us...> - 2009-11-17 01:37:27
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- Log -----------------------------------------------------------------
commit 56adbaffd0a0fab320a64097cd6aa6e74473f840
Author: David Brownell <dbr...@us...>
Date: Mon Nov 16 16:36:21 2009 -0800
ARMv7A: use standard disassembler
We no longer need v7A-specific code for this.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 092de7d..2767d78 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -5535,10 +5535,17 @@ that is not currently supported in OpenOCD.)
Disassembles @var{count} instructions starting at @var{address}.
If @var{count} is not specified, a single instruction is disassembled.
If @option{thumb} is specified, or the low bit of the address is set,
-Thumb (16-bit) instructions are used;
+Thumb2 (mixed 16/32-bit) instructions are used;
else ARM (32-bit) instructions are used.
(Processors may also support the Jazelle state, but
those instructions are not currently understood by OpenOCD.)
+
+Note that all Thumb instructions are Thumb2 instructions,
+so older processors (without Thumb2 support) will still
+see correct disassembly of Thumb code.
+Also, ThumbEE opcodes are the same as Thumb2,
+with a handful of exceptions.
+ThumbEE disassembly currently has no explicit support.
@end deffn
@deffn Command {arm reg}
@@ -5941,23 +5948,6 @@ Displays the number of extra tck for mem-ap memory bus access [0-255].
If @var{value} is defined, first assigns that.
@end deffn
-@subsection ARMv7-A specific commands
-@cindex ARMv7-A
-
-@deffn Command {armv7a disassemble} address [count [@option{thumb}]]
-@cindex disassemble
-Disassembles @var{count} instructions starting at @var{address}.
-If @var{count} is not specified, a single instruction is disassembled.
-If @option{thumb} is specified, or the low bit of the address is set,
-Thumb2 (mixed 16/32-bit) instructions are used;
-else ARM (32-bit) instructions are used.
-With a handful of exceptions, ThumbEE instructions are the same as Thumb2;
-ThumbEE disassembly currently has no explicit support.
-(Processors may also support the Jazelle state, but
-those instructions are not currently understood by OpenOCD.)
-@end deffn
-
-
@subsection Cortex-M3 specific commands
@cindex Cortex-M3
diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index 7f2c387..8b16336 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -274,84 +274,9 @@ COMMAND_HANDLER(handle_dap_info_command)
return dap_info_command(cmd_ctx, swjdp, apsel);
}
-COMMAND_HANDLER(handle_armv7a_disassemble_command)
-{
- struct target *target = get_current_target(cmd_ctx);
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
- int thumb = 0;
- int count = 1;
- uint32_t address;
- int i;
-
- if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) {
- command_print(cmd_ctx, "current target isn't an ARM target");
- return ERROR_OK;
- }
-
- /* REVISIT: eventually support ThumbEE disassembly too;
- * some opcodes work differently.
- */
-
- switch (argc) {
- case 3:
- if (strcmp(args[2], "thumb") != 0)
- goto usage;
- thumb = 1;
- /* FALL THROUGH */
- case 2:
- COMMAND_PARSE_NUMBER(int, args[1], count);
- /* FALL THROUGH */
- case 1:
- COMMAND_PARSE_NUMBER(u32, args[0], address);
- if (address & 0x01) {
- if (!thumb) {
- command_print(cmd_ctx, "Disassemble as Thumb");
- thumb = 1;
- }
- address &= ~1;
- }
- break;
- default:
-usage:
- command_print(cmd_ctx,
- "usage: armv7a disassemble <address> [<count> ['thumb']]");
- return ERROR_OK;
- }
-
- for (i = 0; i < count; i++) {
- struct arm_instruction cur_instruction;
- int retval;
-
- if (thumb) {
- retval = thumb2_opcode(target, address, &cur_instruction);
- if (retval != ERROR_OK)
- return retval;
-
- address += cur_instruction.instruction_size;
- } else {
- uint32_t opcode;
-
- retval = target_read_u32(target, address, &opcode);
- if (retval != ERROR_OK)
- return retval;
-
- retval = arm_evaluate_opcode(opcode, address,
- &cur_instruction);
- if (retval != ERROR_OK)
- return retval;
-
- address += 4;
- }
- command_print(cmd_ctx, "%s", cur_instruction.text);
- }
-
- return ERROR_OK;
-}
-
int armv7a_register_commands(struct command_context *cmd_ctx)
{
struct command *arm_adi_v5_dap_cmd;
- struct command *armv7a_cmd;
arm_adi_v5_dap_cmd = register_command(cmd_ctx, NULL, "dap",
NULL, COMMAND_ANY,
@@ -377,13 +302,5 @@ int armv7a_register_commands(struct command_context *cmd_ctx)
"set/get number of extra tck for mem-ap memory "
"bus access [0-255]");
- armv7a_cmd = register_command(cmd_ctx, NULL, "armv7a",
- NULL, COMMAND_ANY,
- "ARMv7-A specific commands");
-
- register_command(cmd_ctx, armv7a_cmd, "disassemble",
- handle_armv7a_disassemble_command, COMMAND_EXEC,
- "disassemble instructions <address> [<count> ['thumb']]");
-
return ERROR_OK;
}
commit d7d857a1896005df53956565644b138a76a1f0ec
Author: David Brownell <dbr...@us...>
Date: Mon Nov 16 16:36:12 2009 -0800
ARM11: register (most) standard ARM commands
Have ARM11 register the "standard" ARM commands. For now, only
disassembly really works.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/arm11.c b/src/target/arm11.c
index 750c1f5..4d9016f 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -2138,6 +2138,8 @@ static int arm11_register_commands(struct command_context *cmd_ctx)
struct command *top_cmd, *mw_cmd;
+ armv4_5_register_commands(cmd_ctx);
+
top_cmd = register_command(cmd_ctx, NULL, "arm11",
NULL, COMMAND_ANY, NULL);
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 7c4861f..b60b8b2 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -378,6 +378,12 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
return ERROR_FAIL;
+ if (!armv4_5->full_context) {
+ command_print(cmd_ctx, "error: target doesn't support %s",
+ CMD_NAME);
+ return ERROR_FAIL;
+ }
+
for (num = 0; num <= 15; num++)
{
output_len = 0;
@@ -522,7 +528,8 @@ int armv4_5_register_commands(struct command_context *cmd_ctx)
"display/change ARM core state <arm | thumb>");
register_command(cmd_ctx, armv4_5_cmd, "disassemble",
handle_armv4_5_disassemble_command, COMMAND_EXEC,
- "disassemble instructions <address> [<count> ['thumb']]");
+ "disassemble instructions "
+ "<address> [<count> ['thumb']]");
return ERROR_OK;
}
commit f86137066a6b42c46c457c9837a8015990bf71e6
Author: David Brownell <dbr...@us...>
Date: Mon Nov 16 16:36:09 2009 -0800
ARM: "armv4_5" command prefix becomes "arm"
Rename the "armv4_5" command prefix to straight "arm" so it makes
more sense for newer cores. Add a simple compatibility script.
Make sure all the commands give the same "not an ARM" diagnostic
message (and fail properly) when called against non-ARM targets.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/NEWS b/NEWS
index 7387d70..1a024e4 100644
--- a/NEWS
+++ b/NEWS
@@ -8,6 +8,8 @@ JTAG Layer:
Boundary Scan:
Target Layer:
+ ARM
+ - renamed "armv4_5" command prefix as "arm"
ARM11
- Preliminary ETM and ETB hookup
- accelerated "flash erase_check"
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 81409ac..092de7d 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -5515,16 +5515,14 @@ Reports whether the capture clock is locked or not.
@end deffn
-@section ARMv4 and ARMv5 Architecture
-@cindex ARMv4
-@cindex ARMv5
+@section Generic ARM
+@cindex ARM
-These commands are specific to ARM architecture v4 and v5,
-including all ARM7 or ARM9 systems and Intel XScale.
+These commands should be available on all ARM processors.
They are available in addition to other core-specific
commands that may be available.
-@deffn Command {armv4_5 core_state} [@option{arm}|@option{thumb}]
+@deffn Command {arm core_state} [@option{arm}|@option{thumb}]
Displays the core_state, optionally changing it to process
either @option{arm} or @option{thumb} instructions.
The target may later be resumed in the currently set core_state.
@@ -5532,7 +5530,7 @@ The target may later be resumed in the currently set core_state.
that is not currently supported in OpenOCD.)
@end deffn
-@deffn Command {armv4_5 disassemble} address [count [@option{thumb}]]
+@deffn Command {arm disassemble} address [count [@option{thumb}]]
@cindex disassemble
Disassembles @var{count} instructions starting at @var{address}.
If @var{count} is not specified, a single instruction is disassembled.
@@ -5543,7 +5541,7 @@ else ARM (32-bit) instructions are used.
those instructions are not currently understood by OpenOCD.)
@end deffn
-@deffn Command {armv4_5 reg}
+@deffn Command {arm reg}
Display a table of all banked core registers, fetching the current value from every
core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
register value.
diff --git a/src/helper/startup.tcl b/src/helper/startup.tcl
index 73c4cf1..096f03a 100644
--- a/src/helper/startup.tcl
+++ b/src/helper/startup.tcl
@@ -142,6 +142,15 @@ proc ocd_gdb_restart {target_id} {
reset halt
}
+#########
+
+# Temporary migration aid. May be removed starting in January 2011.
+proc armv4_5 params {
+ echo "DEPRECATED! use 'arm $params' not 'armv4_5 $params'"
+ arm $params
+}
+
+#########
# This reset logic may be overridden by board/target/... scripts as needed
# to provide a reset that, if possible, is close to a power-up reset.
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index e112e7b..7c4861f 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -363,10 +363,10 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
struct target *target = get_current_target(cmd_ctx);
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
- if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
+ if (!is_arm(armv4_5))
{
- command_print(cmd_ctx, "current target isn't an ARMV4/5 target");
- return ERROR_OK;
+ command_print(cmd_ctx, "current target isn't an ARM");
+ return ERROR_FAIL;
}
if (target->state != TARGET_HALTED)
@@ -412,10 +412,10 @@ COMMAND_HANDLER(handle_armv4_5_core_state_command)
struct target *target = get_current_target(cmd_ctx);
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
- if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
+ if (!is_arm(armv4_5))
{
- command_print(cmd_ctx, "current target isn't an ARMV4/5 target");
- return ERROR_OK;
+ command_print(cmd_ctx, "current target isn't an ARM");
+ return ERROR_FAIL;
}
if (argc > 0)
@@ -471,7 +471,7 @@ COMMAND_HANDLER(handle_armv4_5_disassemble_command)
default:
usage:
command_print(cmd_ctx,
- "usage: armv4_5 disassemble <address> [<count> ['thumb']]");
+ "usage: arm disassemble <address> [<count> ['thumb']]");
count = 0;
retval = ERROR_FAIL;
}
@@ -510,9 +510,9 @@ int armv4_5_register_commands(struct command_context *cmd_ctx)
{
struct command *armv4_5_cmd;
- armv4_5_cmd = register_command(cmd_ctx, NULL, "armv4_5",
+ armv4_5_cmd = register_command(cmd_ctx, NULL, "arm",
NULL, COMMAND_ANY,
- "armv4/5 specific commands");
+ "generic ARM commands");
register_command(cmd_ctx, armv4_5_cmd, "reg",
handle_armv4_5_reg_command, COMMAND_EXEC,
diff --git a/tcl/board/mini2440.cfg b/tcl/board/mini2440.cfg
index d17b107..0f7ebf8 100644
--- a/tcl/board/mini2440.cfg
+++ b/tcl/board/mini2440.cfg
@@ -292,7 +292,7 @@ proc load_uboot { } {
proc s {} {
step
reg
- armv4_5 disassemble 0x33F80068 0x10
+ arm disassemble 0x33F80068 0x10
}
proc help_2440 {} {
diff --git a/tcl/target/lpc1768.cfg b/tcl/target/lpc1768.cfg
index 9f6bcff..0b07d51 100644
--- a/tcl/target/lpc1768.cfg
+++ b/tcl/target/lpc1768.cfg
@@ -35,7 +35,7 @@ $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000 -work-a
$_TARGETNAME configure -event reset-init {
# Force target into ARM state
- armv4_5 core_state arm
+ arm core_state arm
#do not remap 0x0000-0x0020 to anything but the flash
# mwb 0xE01FC040 0x01
mwb 0xE000ED08 0x00
diff --git a/tcl/target/lpc2148.cfg b/tcl/target/lpc2148.cfg
index ce672c8..1f833e7 100644
--- a/tcl/target/lpc2148.cfg
+++ b/tcl/target/lpc2148.cfg
@@ -39,7 +39,7 @@ $_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-a
$_TARGETNAME configure -event reset-init {
# Force target into ARM state
- armv4_5 core_state arm
+ arm core_state arm
# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
# "User Flash Mode" where interrupt vectors are _not_ remapped,
diff --git a/tcl/target/lpc2378.cfg b/tcl/target/lpc2378.cfg
index 7f716f3..aa3fad2 100644
--- a/tcl/target/lpc2378.cfg
+++ b/tcl/target/lpc2378.cfg
@@ -35,7 +35,7 @@ $_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x8000 -work-a
$_TARGETNAME configure -event reset-init {
# Force target into ARM state
- armv4_5 core_state arm
+ arm core_state arm
#do not remap 0x0000-0x0020 to anything but the flash
mwb 0xE01FC040 0x01
}
diff --git a/tcl/target/lpc2478.cfg b/tcl/target/lpc2478.cfg
index e78afa1..b0af4c0 100644
--- a/tcl/target/lpc2478.cfg
+++ b/tcl/target/lpc2478.cfg
@@ -35,7 +35,7 @@ $_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x10000 -work-
$_TARGETNAME configure -event reset-init {
# Force target into ARM state
- armv4_5 core_state arm
+ arm core_state arm
# Do not remap 0x0000-0x0020 to anything but the Flash
mwb 0xE01FC040 0x01
}
commit 7c393679c0cd8f7609a0d6b2329a1877de0f3d31
Author: David Brownell <dbr...@us...>
Date: Mon Nov 16 16:36:03 2009 -0800
JTAG: fix autoprobe failure.
Fix bug noted by Ãyvind: terminate the IR length autoscan when
the IR is too long, or otherwise broken.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/jtag/core.c b/src/jtag/core.c
index da745d0..211b9d5 100644
--- a/src/jtag/core.c
+++ b/src/jtag/core.c
@@ -1224,7 +1224,14 @@ static int jtag_validate_ircapture(void)
/* If we're autoprobing, guess IR lengths. They must be at
* least two bits. Guessing will fail if (a) any TAP does
* not conform to the JTAG spec; or (b) when the upper bits
- * captured from some conforming TAP are nonzero.
+ * captured from some conforming TAP are nonzero. Or if
+ * (c) an IR length is longer than 32 bits -- which is only
+ * an implementation limit, which could someday be raised.
+ *
+ * REVISIT optimization: if there's a *single* TAP we can
+ * lift restrictions (a) and (b) by scanning a recognizable
+ * pattern before the all-ones BYPASS. Check for where the
+ * pattern starts in the result, instead of an 0...01 value.
*
* REVISIT alternative approach: escape to some tcl code
* which could provide more knowledge, based on IDCODE; and
@@ -1233,7 +1240,8 @@ static int jtag_validate_ircapture(void)
if (tap->ir_length == 0) {
tap->ir_length = 2;
while ((val = buf_get_u32(ir_test, chain_pos,
- tap->ir_length + 1)) == 1) {
+ tap->ir_length + 1)) == 1
+ && tap->ir_length <= 32) {
tap->ir_length++;
}
LOG_WARNING("AUTO %s - use \"... -irlen %d\"",
-----------------------------------------------------------------------
Summary of changes:
NEWS | 2 +
doc/openocd.texi | 40 ++++++++---------------
src/helper/startup.tcl | 9 +++++
src/jtag/core.c | 12 ++++++-
src/target/arm11.c | 2 +
src/target/armv4_5.c | 27 ++++++++++------
src/target/armv7a.c | 83 ------------------------------------------------
tcl/board/mini2440.cfg | 2 +-
tcl/target/lpc1768.cfg | 2 +-
tcl/target/lpc2148.cfg | 2 +-
tcl/target/lpc2378.cfg | 2 +-
tcl/target/lpc2478.cfg | 2 +-
12 files changed, 59 insertions(+), 126 deletions(-)
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