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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.2.0-421-ge98817c
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From: David B. <dbr...@us...> - 2009-10-25 21:09:35
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The branch, master has been updated
via e98817c4636f45b45db4332d2a5fbf36676f2f39 (commit)
via 2a8aa3b7efb590cabd7ee930dbb68fd64e028099 (commit)
from 0b436497e047a13ff3dbae46af0eb67376ea5acf (commit)
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- Log -----------------------------------------------------------------
commit e98817c4636f45b45db4332d2a5fbf36676f2f39
Author: David Brownell <dbr...@us...>
Date: Sun Oct 25 13:07:57 2009 -0700
JTAG: jtag_tap_init() bugfixes
Stop allocating three bytes per IR bit, and cope somewhat better
with IR lengths over 32 bits.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/jtag/core.c b/src/jtag/core.c
index 7c85839..08cfe43 100644
--- a/src/jtag/core.c
+++ b/src/jtag/core.c
@@ -1204,20 +1204,29 @@ done:
void jtag_tap_init(jtag_tap_t *tap)
{
+ unsigned ir_len_bits;
+ unsigned ir_len_bytes;
+
assert(0 != tap->ir_length);
- /// @todo fix, this allocates one byte per bit for all three fields!
- tap->expected = malloc(tap->ir_length);
- tap->expected_mask = malloc(tap->ir_length);
- tap->cur_instr = malloc(tap->ir_length);
+ ir_len_bits = tap->ir_length;
+ ir_len_bytes = CEIL(ir_len_bits, 8);
- /// @todo cope sanely with ir_length bigger than 32 bits
- buf_set_u32(tap->expected, 0, tap->ir_length, tap->ir_capture_value);
- buf_set_u32(tap->expected_mask, 0, tap->ir_length, tap->ir_capture_mask);
- buf_set_ones(tap->cur_instr, tap->ir_length);
+ tap->expected = calloc(1, ir_len_bytes);
+ tap->expected_mask = calloc(1, ir_len_bytes);
+ tap->cur_instr = malloc(ir_len_bytes);
+
+ /// @todo cope better with ir_length bigger than 32 bits
+ if (ir_len_bits > 32)
+ ir_len_bits = 32;
- // place TAP in bypass mode
+ buf_set_u32(tap->expected, 0, ir_len_bits, tap->ir_capture_value);
+ buf_set_u32(tap->expected_mask, 0, ir_len_bits, tap->ir_capture_mask);
+
+ // TAP will be in bypass mode after jtag_validate_ircapture()
tap->bypass = 1;
+ buf_set_ones(tap->cur_instr, tap->ir_length);
+
// register the reset callback for the TAP
jtag_register_event_callback(&jtag_reset_callback, tap);
commit 2a8aa3b7efb590cabd7ee930dbb68fd64e028099
Author: David Brownell <dbr...@us...>
Date: Sun Oct 25 13:06:47 2009 -0700
xscale: always reload handler after reset
Remove needless debug handler state.
- "handler_installed" became wrong as soon as the second TRST+SRST
reset was issued ... so the handler was never reloaded after the
reset removed it from the mini-icache.
This fixes the bug where subsequent resets fail on PXA255 (if the
first one even worked, which is uncommon). Other XScale chips
would have problems too; PXA270 seems to have, IXP425 maybe not.
- "handler_running" was never tested; it's pointless.
Plus a related bugfix: invalidate OpenOCD's ARM register cache on reset.
It was no more valid than the XScale's mini-icache. (Though ... such
invalidations might be better done in "SRST asserted" callbacks.)
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 640eb01..ee9d88d 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -890,8 +890,6 @@ static int xscale_arch_state(struct target_s *target)
static int xscale_poll(target_t *target)
{
int retval = ERROR_OK;
- armv4_5_common_t *armv4_5 = target->arch_info;
- xscale_common_t *xscale = armv4_5->arch_info;
if ((target->state == TARGET_RUNNING) || (target->state == TARGET_DEBUG_RUNNING))
{
@@ -900,8 +898,6 @@ static int xscale_poll(target_t *target)
{
/* there's data to read from the tx register, we entered debug state */
- xscale->handler_running = 1;
-
target->state = TARGET_HALTED;
/* process debug entry, fetching current mode regs */
@@ -1365,8 +1361,6 @@ static int xscale_resume(struct target_s *target, int current,
LOG_DEBUG("target resumed");
- xscale->handler_running = 1;
-
return ERROR_OK;
}
@@ -1574,7 +1568,17 @@ static int xscale_deassert_reset(target_t *target)
breakpoint = breakpoint->next;
}
- if (!xscale->handler_installed)
+ armv4_5_invalidate_core_regs(target);
+
+ /* FIXME mark hardware watchpoints got unset too. Also,
+ * at least some of the XScale registers are invalid...
+ */
+
+ /*
+ * REVISIT: *assumes* we had a SRST+TRST reset so the mini-icache
+ * contents got invalidated. Safer to force that, so writing new
+ * contents can't ever fail..
+ */
{
uint32_t address;
unsigned buf_cnt;
@@ -1599,10 +1603,6 @@ static int xscale_deassert_reset(target_t *target)
* it's using halt mode (not monitor mode), it runs in
* "Special Debug State" for access to registers, memory,
* coprocessors, trace data, etc.
- *
- * REVISIT: *assumes* we've had a SRST+TRST reset so the
- * mini-icache contents have been invalidated. Safest to
- * force that, so writing new contents is reliable...
*/
address = xscale->handler_address;
for (unsigned binary_size = sizeof xscale_debug_handler - 1;
@@ -1673,10 +1673,6 @@ static int xscale_deassert_reset(target_t *target)
xscale_resume(target, 1, 0x0, 1, 0);
}
}
- else
- {
- jtag_add_reset(0, 0);
- }
return ERROR_OK;
}
@@ -2967,8 +2963,6 @@ static int xscale_init_arch_info(target_t *target,
}
/* the debug handler isn't installed (and thus not running) at this time */
- xscale->handler_installed = 0;
- xscale->handler_running = 0;
xscale->handler_address = 0xfe000800;
/* clear the vectors we keep locally for reference */
diff --git a/src/target/xscale.h b/src/target/xscale.h
index a5d83ee..4b34cf8 100644
--- a/src/target/xscale.h
+++ b/src/target/xscale.h
@@ -86,8 +86,6 @@ typedef struct xscale_common_s
reg_cache_t *reg_cache;
/* current state of the debug handler */
- int handler_installed;
- int handler_running;
uint32_t handler_address;
/* target-endian buffers with exception vectors */
-----------------------------------------------------------------------
Summary of changes:
src/jtag/core.c | 27 ++++++++++++++++++---------
src/target/xscale.c | 28 +++++++++++-----------------
src/target/xscale.h | 2 --
3 files changed, 29 insertions(+), 28 deletions(-)
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