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[openocd-svn] Main OpenOCD repository branch, master, updated. 0.2.0-359-g6bff28f
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From: Øyvind H. <go...@us...> - 2009-10-13 12:11:44
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via adefaa944eac21156150a809b739cca692901db7 (commit)
via 40fe5b1428e054bae7a351fbdac9cc8c87fd6dc1 (commit)
from 1c2e48b000503f15abba9092e8a159e0914c587b (commit)
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- Log -----------------------------------------------------------------
commit 6bff28fbdb8ae97d29608e15deee8bcf9f9c2316
Author: Ãyvind Harboe <oyv...@zy...>
Date: Tue Oct 13 12:06:55 2009 +0200
Delete commented out code. Add a bit of error checking.
diff --git a/TODO b/TODO
index 6521c60..a57ed24 100644
--- a/TODO
+++ b/TODO
@@ -138,11 +138,9 @@ https://lists.berlios.de/pipermail/openocd-development/2009-July/009206.html
- ARM923EJS:
- reset run/halt/step is not robust; needs testing to map out problems.
- ARM11 improvements (MB?)
+ - add support for asserting srst to reset the core.
- Single stepping works, but should automatically
use hardware stepping if available.
- - hunt down and add timeouts to all infinite loops, e.g. arm11_run_instr_no_data would
- lock up in infinite loop if e.g. an "mdh" command tries to read memory from invalid memory location.
- Try mdh 0x40000000 on i.MX31 PDK
- mdb can return garbage data if read byte operation fails for
a memory region(16 & 32 byte access modes may be supported). Is this
a bug in the .MX31 PDK init script? Try on i.MX31 PDK:
diff --git a/src/target/arm11.c b/src/target/arm11.c
index 36ed6b8..c41adfa 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -608,6 +608,13 @@ int arm11_leave_debug_state(arm11_common_t * arm11)
if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
{
+ /*
+ The wDTR/rDTR two registers that are used to send/receive data to/from
+ the core in tandem with corresponding instruction codes that are
+ written into the core. The RDTR FULL/WDTR FULL flag indicates that the
+ registers hold data that was written by one side (CPU or JTAG) and not
+ read out by the other side.
+ */
LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR);
return ERROR_FAIL;
}
@@ -702,9 +709,6 @@ int arm11_poll(struct target_s *target)
arm11_common_t * arm11 = target->arch_info;
- if (arm11->trst_active)
- return ERROR_OK;
-
uint32_t dscr;
CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
@@ -784,12 +788,6 @@ int arm11_halt(struct target_s *target)
return ERROR_OK;
}
- if (arm11->trst_active)
- {
- arm11->halt_requested = true;
- return ERROR_OK;
- }
-
arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
CHECK_RETVAL(jtag_execute_queue());
@@ -1199,22 +1197,16 @@ int arm11_step(struct target_s *target, int current, uint32_t address, int handl
return ERROR_OK;
}
-/* target reset control */
-int arm11_assert_reset(struct target_s *target)
+int arm11_assert_reset(target_t *target)
{
FNC_INFO;
-#if 0
- /* assert reset lines */
- /* resets only the DBGTAP, not the ARM */
-
- jtag_add_reset(1, 0);
- jtag_add_sleep(5000);
-
- arm11_common_t * arm11 = target->arch_info;
- arm11->trst_active = true;
-#endif
-
+ /* FIX! we really should assert srst here, but
+ * how do we reset the target into the halted state?
+ *
+ * Also arm11 behaves "funny" when srst is asserted
+ * (as of writing the rules are not understood).
+ */
if (target->reset_halt)
{
CHECK_RETVAL(target_halt(target));
@@ -1223,25 +1215,8 @@ int arm11_assert_reset(struct target_s *target)
return ERROR_OK;
}
-int arm11_deassert_reset(struct target_s *target)
+int arm11_deassert_reset(target_t *target)
{
- FNC_INFO;
-
-#if 0
- LOG_DEBUG("target->state: %s",
- target_state_name(target));
-
-
- /* deassert reset lines */
- jtag_add_reset(0, 0);
-
- arm11_common_t * arm11 = target->arch_info;
- arm11->trst_active = false;
-
- if (arm11->halt_requested)
- return arm11_halt(target);
-#endif
-
return ERROR_OK;
}
@@ -1807,6 +1782,8 @@ int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target
/* talk to the target and set things up */
int arm11_examine(struct target_s *target)
{
+ int retval;
+
FNC_INFO;
arm11_common_t * arm11 = target->arch_info;
@@ -1874,7 +1851,9 @@ int arm11_examine(struct target_s *target)
* as suggested by the spec.
*/
- arm11_check_init(arm11, NULL);
+ retval = arm11_check_init(arm11, NULL);
+ if (retval != ERROR_OK)
+ return retval;
target_set_examined(target);
diff --git a/src/target/arm11.h b/src/target/arm11.h
index c93e5ab..61c5f7f 100644
--- a/src/target/arm11.h
+++ b/src/target/arm11.h
@@ -98,10 +98,6 @@ typedef struct arm11_common_s
uint32_t last_dscr; /**< Last retrieved DSCR value;
Use only for debug message generation */
- bool trst_active;
- bool halt_requested; /**< Keep track if arm11_halt() calls occured
- during reset. Otherwise do it ASAP. */
-
bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */
/** \name Shadow registers to save processor state */
commit adefaa944eac21156150a809b739cca692901db7
Author: Ãyvind Harboe <oyv...@zy...>
Date: Tue Oct 13 12:02:09 2009 +0200
arm11 seems to gate JTAG when srst is asserted
diff --git a/tcl/target/imx31.cfg b/tcl/target/imx31.cfg
index f579d6e..61a2925 100644
--- a/tcl/target/imx31.cfg
+++ b/tcl/target/imx31.cfg
@@ -1,7 +1,7 @@
# imx31 config
#
-reset_config trst_and_srst srst_nogate
+reset_config trst_and_srst srst_gates_jtag
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/imx35.cfg b/tcl/target/imx35.cfg
index 800e142..32748c5 100644
--- a/tcl/target/imx35.cfg
+++ b/tcl/target/imx35.cfg
@@ -1,8 +1,7 @@
# imx35 config
#
-reset_config trst_and_srst srst_nogate
-
+reset_config trst_and_srst srst_gates_jtag
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
commit 40fe5b1428e054bae7a351fbdac9cc8c87fd6dc1
Author: Ãyvind Harboe <oyv...@zy...>
Date: Tue Oct 13 11:29:05 2009 +0200
Propagate error from assert, deassert and halt on tcl target object.
diff --git a/src/target/target.c b/src/target/target.c
index 8bb9371..2b7d7e2 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -3452,6 +3452,10 @@ void target_all_handle_event(enum target_event e)
}
}
+
+/* FIX? should we propagate errors here rather than printing them
+ * and continuing?
+ */
void target_handle_event(target_t *target, enum target_event e)
{
target_event_action_t *teap;
@@ -4093,11 +4097,11 @@ static int tcl_target_func(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
/* do the assert */
if (n->value == NVP_ASSERT) {
- target->type->assert_reset(target);
+ e = target->type->assert_reset(target);
} else {
- target->type->deassert_reset(target);
+ e = target->type->deassert_reset(target);
}
- return JIM_OK;
+ return (e == ERROR_OK) ? JIM_OK : JIM_ERR;
case TS_CMD_HALT:
if (goi.argc) {
Jim_WrongNumArgs(goi.interp, 0, argv, "halt [no parameters]");
@@ -4105,8 +4109,8 @@ static int tcl_target_func(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
}
if (!target->tap->enabled)
goto err_tap_disabled;
- target->type->halt(target);
- return JIM_OK;
+ e = target->type->halt(target);
+ return (e == ERROR_OK) ? JIM_OK : JIM_ERR;
case TS_CMD_WAITSTATE:
/* params: <name> statename timeoutmsecs */
if (goi.argc != 2) {
-----------------------------------------------------------------------
Summary of changes:
TODO | 4 +--
src/target/arm11.c | 61 ++++++++++++++++---------------------------------
src/target/arm11.h | 4 ---
src/target/target.c | 14 +++++++----
tcl/target/imx31.cfg | 2 +-
tcl/target/imx35.cfg | 3 +-
6 files changed, 32 insertions(+), 56 deletions(-)
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